include/configs/T208xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 /*
   7  * T2080 RDB/PCIe board configuration file
   8  */
   9
  10 #ifndef __T2080RDB_H
  11 #define __T2080RDB_H
  12
  13 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  14 #define CONFIG_FSL_SATA_V2
  15
  16 /* High Level Configuration Options */
  17 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
  18 #define CONFIG_ENABLE_36BIT_PHYS
  19
  20 #ifdef CONFIG_PHYS_64BIT
  21 #define CONFIG_ADDR_MAP 1
  22 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  23 #endif
  24
  25 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  26 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  27 #define CONFIG_ENV_OVERWRITE
  28
  29 #ifdef CONFIG_RAMBOOT_PBL
  30 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
  31
  32 #define CONFIG_SPL_FLUSH_IMAGE
  33 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  34 #define CONFIG_SPL_PAD_TO               0x40000
  35 #define CONFIG_SPL_MAX_SIZE             0x28000
  36 #define RESET_VECTOR_OFFSET             0x27FFC
  37 #define BOOT_PAGE_OFFSET                0x27000
  38 #ifdef CONFIG_SPL_BUILD
  39 #define CONFIG_SPL_SKIP_RELOCATE
  40 #define CONFIG_SPL_COMMON_INIT_DDR
  41 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  42 #endif
  43
  44 #ifdef CONFIG_NAND
  45 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  46 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  47 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  48 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  49 #define CONFIG_SYS_LDSCRIPT  "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  50 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg
  51 #define CONFIG_SPL_NAND_BOOT
  52 #endif
  53
  54 #ifdef CONFIG_SPIFLASH
  55 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  56 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  57 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
  58 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
  59 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
  60 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
  61 #define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  62 #ifndef CONFIG_SPL_BUILD
  63 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  64 #endif
  65 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg
  66 #define CONFIG_SPL_SPI_BOOT
  67 #endif
  68
  69 #ifdef CONFIG_SDCARD
  70 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  71 #define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
  72 #define CONFIG_SYS_MMC_U_BOOT_DST      (0x00200000)
  73 #define CONFIG_SYS_MMC_U_BOOT_START    (0x00200000)
  74 #define CONFIG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
  75 #define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  76 #ifndef CONFIG_SPL_BUILD
  77 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  78 #endif
  79 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg
  80 #define CONFIG_SPL_MMC_BOOT
  81 #endif
  82
  83 #endif /* CONFIG_RAMBOOT_PBL */
  84
  85 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  86 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  87 /* Set 1M boot space */
  88 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  89 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  90                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  91 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  92 #endif
  93
  94 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  95 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  96 #endif
  97
  98 /*
  99  * These can be toggled for performance analysis, otherwise use default.
 100  */
 101 #define CONFIG_SYS_CACHE_STASHING
 102 #define CONFIG_BTB              /* toggle branch predition */
 103 #define CONFIG_DDR_ECC
 104 #ifdef CONFIG_DDR_ECC
 105 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 106 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 107 #endif
 108
 109 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
 110 #define CONFIG_SYS_MEMTEST_END          0x00400000
 111
 112 #if defined(CONFIG_SPIFLASH)
 113 #define CONFIG_ENV_SPI_BUS      0
 114 #define CONFIG_ENV_SPI_CS       0
 115 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 116 #define CONFIG_ENV_SPI_MODE     0
 117 #define CONFIG_ENV_SIZE         0x2000     /* 8KB */
 118 #define CONFIG_ENV_OFFSET       0x100000   /* 1MB */
 119 #define CONFIG_ENV_SECT_SIZE    0x10000
 120 #elif defined(CONFIG_SDCARD)
 121 #define CONFIG_SYS_MMC_ENV_DEV  0
 122 #define CONFIG_ENV_SIZE         0x2000
 123 #define CONFIG_ENV_OFFSET       (512 * 0x800)
 124 #elif defined(CONFIG_NAND)
 125 #define CONFIG_ENV_SIZE         0x2000
 126 #define CONFIG_ENV_OFFSET       (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
 127 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 128 #define CONFIG_ENV_ADDR         0xffe20000
 129 #define CONFIG_ENV_SIZE         0x2000
 130 #elif defined(CONFIG_ENV_IS_NOWHERE)
 131 #define CONFIG_ENV_SIZE         0x2000
 132 #else
 133 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 134 #define CONFIG_ENV_SIZE         0x2000
 135 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 136 #endif
 137
 138 #ifndef __ASSEMBLY__
 139 unsigned long get_board_sys_clk(void);
 140 unsigned long get_board_ddr_clk(void);
 141 #endif
 142
 143 #define CONFIG_SYS_CLK_FREQ     66660000
 144 #define CONFIG_DDR_CLK_FREQ     133330000
 145
 146 /*
 147  * Config the L3 Cache as L3 SRAM
 148  */
 149 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 150 #define CONFIG_SYS_L3_SIZE              (512 << 10)
 151 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 152 #ifdef CONFIG_RAMBOOT_PBL
 153 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 154 #endif
 155 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 156 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
 157 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 158
 159 #define CONFIG_SYS_DCSRBAR      0xf0000000
 160 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
 161
 162 /* EEPROM */
 163 #define CONFIG_ID_EEPROM
 164 #define CONFIG_SYS_I2C_EEPROM_NXID
 165 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 166 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 167 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 168
 169 /*
 170  * DDR Setup
 171  */
 172 #define CONFIG_VERY_BIG_RAM
 173 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 174 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 175 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 176 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 177 #define CONFIG_DDR_SPD
 178 #undef CONFIG_FSL_DDR_INTERACTIVE
 179 #define CONFIG_SYS_SPD_BUS_NUM  0
 180 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 181 #define SPD_EEPROM_ADDRESS1     0x51
 182 #define SPD_EEPROM_ADDRESS2     0x52
 183 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 184 #define CTRL_INTLV_PREFERED     cacheline
 185
 186 /*
 187  * IFC Definitions
 188  */
 189 #define CONFIG_SYS_FLASH_BASE           0xe8000000
 190 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 191 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 192 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 193                                 CSPR_PORT_SIZE_16 | \
 194                                 CSPR_MSEL_NOR | \
 195                                 CSPR_V)
 196 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 197
 198 /* NOR Flash Timing Params */
 199 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 200
 201 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 202                                 FTIM0_NOR_TEADC(0x5) | \
 203                                 FTIM0_NOR_TEAHC(0x5))
 204 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 205                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 206                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 207 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 208                                 FTIM2_NOR_TCH(0x4) | \
 209                                 FTIM2_NOR_TWPH(0x0E) | \
 210                                 FTIM2_NOR_TWP(0x1c))
 211 #define CONFIG_SYS_NOR_FTIM3    0x0
 212
 213 #define CONFIG_SYS_FLASH_QUIET_TEST
 214 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 215
 216 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 217 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 218 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 219 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 220 #define CONFIG_SYS_FLASH_EMPTY_INFO
 221 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS }
 222
 223 /* CPLD on IFC */
 224 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 225 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 226 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 227 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 228                                 | CSPR_PORT_SIZE_8 \
 229                                 | CSPR_MSEL_GPCM \
 230                                 | CSPR_V)
 231 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 232 #define CONFIG_SYS_CSOR2        0x0
 233
 234 /* CPLD Timing parameters for IFC CS2 */
 235 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 236                                         FTIM0_GPCM_TEADC(0x0e) | \
 237                                         FTIM0_GPCM_TEAHC(0x0e))
 238 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 239                                         FTIM1_GPCM_TRAD(0x1f))
 240 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 241                                         FTIM2_GPCM_TCH(0x8) | \
 242                                         FTIM2_GPCM_TWP(0x1f))
 243 #define CONFIG_SYS_CS2_FTIM3            0x0
 244
 245 /* NAND Flash on IFC */
 246 #define CONFIG_NAND_FSL_IFC
 247 #define CONFIG_SYS_NAND_BASE            0xff800000
 248 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 249
 250 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 251 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 252                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 253                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 254                                 | CSPR_V)
 255 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 256
 257 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 258                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 259                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 260                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 261                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 262                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 263                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 264
 265 #define CONFIG_SYS_NAND_ONFI_DETECTION
 266
 267 /* ONFI NAND Flash mode0 Timing Params */
 268 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 269                                         FTIM0_NAND_TWP(0x18)    | \
 270                                         FTIM0_NAND_TWCHT(0x07)  | \
 271                                         FTIM0_NAND_TWH(0x0a))
 272 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 273                                         FTIM1_NAND_TWBE(0x39)   | \
 274                                         FTIM1_NAND_TRR(0x0e)    | \
 275                                         FTIM1_NAND_TRP(0x18))
 276 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 277                                         FTIM2_NAND_TREH(0x0a)   | \
 278                                         FTIM2_NAND_TWHRE(0x1e))
 279 #define CONFIG_SYS_NAND_FTIM3           0x0
 280
 281 #define CONFIG_SYS_NAND_DDR_LAW         11
 282 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 283 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 284 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 285
 286 #if defined(CONFIG_NAND)
 287 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 288 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 289 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 290 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 291 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 292 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 293 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 294 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 295 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 296 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 297 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 298 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 299 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 300 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 301 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 302 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 303 #else
 304 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 305 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 306 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 307 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 308 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 309 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 310 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 311 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 312 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 313 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 314 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 315 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 316 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 317 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 318 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 319 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 320 #endif
 321
 322 #if defined(CONFIG_RAMBOOT_PBL)
 323 #define CONFIG_SYS_RAMBOOT
 324 #endif
 325
 326 #ifdef CONFIG_SPL_BUILD
 327 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SPL_TEXT_BASE
 328 #else
 329 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SYS_TEXT_BASE /* start of monitor */
 330 #endif
 331
 332 #define CONFIG_HWCONFIG
 333
 334 /* define to use L1 as initial stack */
 335 #define CONFIG_L1_INIT_RAM
 336 #define CONFIG_SYS_INIT_RAM_LOCK
 337 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 338 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 339 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 340 /* The assembler doesn't like typecast */
 341 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 342                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 343                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 344 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 345 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 346                                                 GENERATED_GBL_DATA_SIZE)
 347 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 348 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 349 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 350
 351 /*
 352  * Serial Port
 353  */
 354 #define CONFIG_SYS_NS16550_SERIAL
 355 #define CONFIG_SYS_NS16550_REG_SIZE     1
 356 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 357 #define CONFIG_SYS_BAUDRATE_TABLE       \
 358         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 359 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 360 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 361 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 362 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 363
 364 /*
 365  * I2C
 366  */
 367 #define CONFIG_SYS_I2C
 368 #define CONFIG_SYS_I2C_FSL
 369 #define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
 370 #define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
 371 #define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
 372 #define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
 373 #define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
 374 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
 375 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
 376 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
 377 #define CONFIG_SYS_FSL_I2C_SPEED   100000
 378 #define CONFIG_SYS_FSL_I2C2_SPEED  100000
 379 #define CONFIG_SYS_FSL_I2C3_SPEED  100000
 380 #define CONFIG_SYS_FSL_I2C4_SPEED  100000
 381 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 382 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 383 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 384 #define I2C_MUX_CH_DEFAULT      0x8
 385
 386 #define I2C_MUX_CH_VOL_MONITOR  0xa
 387
 388 #define CONFIG_VID_FLS_ENV              "t208xrdb_vdd_mv"
 389 #ifndef CONFIG_SPL_BUILD
 390 #define CONFIG_VID
 391 #endif
 392 #define CONFIG_VOL_MONITOR_IR36021_SET
 393 #define CONFIG_VOL_MONITOR_IR36021_READ
 394 /* The lowest and highest voltage allowed for T208xRDB */
 395 #define VDD_MV_MIN                      819
 396 #define VDD_MV_MAX                      1212
 397
 398 /*
 399  * RapidIO
 400  */
 401 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 402 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 403 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 404 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 405 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 406 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 407 /*
 408  * for slave u-boot IMAGE instored in master memory space,
 409  * PHYS must be aligned based on the SIZE
 410  */
 411 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 412 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 413 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 414 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 415 /*
 416  * for slave UCODE and ENV instored in master memory space,
 417  * PHYS must be aligned based on the SIZE
 418  */
 419 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 420 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 421 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 422
 423 /* slave core release by master*/
 424 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 425 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 426
 427 /*
 428  * SRIO_PCIE_BOOT - SLAVE
 429  */
 430 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 431 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 432 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 433                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 434 #endif
 435
 436 /*
 437  * eSPI - Enhanced SPI
 438  */
 439 #ifdef CONFIG_SPI_FLASH
 440 #define CONFIG_SPI_FLASH_BAR
 441 #define CONFIG_SF_DEFAULT_SPEED  10000000
 442 #define CONFIG_SF_DEFAULT_MODE    0
 443 #endif
 444
 445 /*
 446  * General PCI
 447  * Memory space is mapped 1-1, but I/O space must start from 0.
 448  */
 449 #define CONFIG_PCIE1            /* PCIE controller 1 */
 450 #define CONFIG_PCIE2            /* PCIE controller 2 */
 451 #define CONFIG_PCIE3            /* PCIE controller 3 */
 452 #define CONFIG_PCIE4            /* PCIE controller 4 */
 453 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 454 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 455 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 456 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 457 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 458 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 459 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 460 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 461 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 462 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 463 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 464
 465 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 466 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 467 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 468 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 469 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000 /* 256M */
 470 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 471 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 472 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 473 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 474
 475 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 476 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 477 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 478 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 479 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 480 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 481 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 482 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 483 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 484
 485 /* controller 4, Base address 203000 */
 486 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 487 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 488 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 489 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 490 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 491 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 492 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 493
 494 #ifdef CONFIG_PCI
 495 #define CONFIG_PCI_INDIRECT_BRIDGE
 496 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata LSZ ADD */
 497 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 498 #endif
 499
 500 /* Qman/Bman */
 501 #ifndef CONFIG_NOBQFMAN
 502 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 503 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 504 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 505 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 506 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 507 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 508 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 509 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 510 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 511                                         CONFIG_SYS_BMAN_CENA_SIZE)
 512 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 513 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 514 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 515 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 516 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 517 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 518 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 519 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 520 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 521 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 522 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 523                                         CONFIG_SYS_QMAN_CENA_SIZE)
 524 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 525 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 526
 527 #define CONFIG_SYS_DPAA_FMAN
 528 #define CONFIG_SYS_DPAA_PME
 529 #define CONFIG_SYS_PMAN
 530 #define CONFIG_SYS_DPAA_DCE
 531 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 532 #define CONFIG_SYS_INTERLAKEN
 533
 534 /* Default address of microcode for the Linux Fman driver */
 535 #if defined(CONFIG_SPIFLASH)
 536 /*
 537  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 538  * env, so we got 0x110000.
 539  */
 540 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 541 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
 542 #define CONFIG_SYS_FMAN_FW_ADDR         0x110000
 543 #define CONFIG_CORTINA_FW_ADDR          0x120000
 544
 545 #elif defined(CONFIG_SDCARD)
 546 /*
 547  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 548  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 549  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 550  */
 551 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 552 #define CONFIG_SYS_CORTINA_FW_IN_MMC
 553 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 554 #define CONFIG_CORTINA_FW_ADDR          (512 * 0x8a0)
 555
 556 #elif defined(CONFIG_NAND)
 557 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 558 #define CONFIG_SYS_CORTINA_FW_IN_NAND
 559 #define CONFIG_SYS_FMAN_FW_ADDR         (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 560 #define CONFIG_CORTINA_FW_ADDR          (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
 561 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 562 /*
 563  * Slave has no ucode locally, it can fetch this from remote. When implementing
 564  * in two corenet boards, slave's ucode could be stored in master's memory
 565  * space, the address can be mapped from slave TLB->slave LAW->
 566  * slave SRIO or PCIE outbound window->master inbound window->
 567  * master LAW->the ucode address in master's memory space.
 568  */
 569 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 570 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE
 571 #define CONFIG_SYS_FMAN_FW_ADDR         0xFFE00000
 572 #define CONFIG_CORTINA_FW_ADDR          0xFFE10000
 573 #else
 574 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 575 #define CONFIG_SYS_CORTINA_FW_IN_NOR
 576 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 577 #define CONFIG_CORTINA_FW_ADDR          0xEFE00000
 578 #endif
 579 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 580 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 581 #endif /* CONFIG_NOBQFMAN */
 582
 583 #ifdef CONFIG_SYS_DPAA_FMAN
 584 #define CONFIG_FMAN_ENET
 585 #define CONFIG_PHYLIB_10G
 586 #define CONFIG_PHY_AQUANTIA
 587 #define CONFIG_PHY_CORTINA
 588 #define CONFIG_PHY_REALTEK
 589 #define CONFIG_CORTINA_FW_LENGTH        0x40000
 590 #define RGMII_PHY1_ADDR         0x01  /* RealTek RTL8211E */
 591 #define RGMII_PHY2_ADDR         0x02
 592 #define CORTINA_PHY_ADDR1       0x0c  /* Cortina CS4315 */
 593 #define CORTINA_PHY_ADDR2       0x0d
 594 #define FM1_10GEC3_PHY_ADDR     0x00  /* Aquantia AQ1202 10G Base-T */
 595 #define FM1_10GEC4_PHY_ADDR     0x01
 596 #endif
 597
 598 #ifdef CONFIG_FMAN_ENET
 599 #define CONFIG_ETHPRIME         "FM1@DTSEC3"
 600 #endif
 601
 602 /*
 603  * SATA
 604  */
 605 #ifdef CONFIG_FSL_SATA_V2
 606 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 607 #define CONFIG_SATA1
 608 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 609 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 610 #define CONFIG_SATA2
 611 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 612 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 613 #define CONFIG_LBA48
 614 #endif
 615
 616 /*
 617  * USB
 618  */
 619 #ifdef CONFIG_USB_EHCI_HCD
 620 #define CONFIG_USB_EHCI_FSL
 621 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 622 #define CONFIG_HAS_FSL_DR_USB
 623 #endif
 624
 625 /*
 626  * SDHC
 627  */
 628 #ifdef CONFIG_MMC
 629 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 630 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 631 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 632 #endif
 633
 634 /*
 635  * Dynamic MTD Partition support with mtdparts
 636  */
 637
 638 /*
 639  * Environment
 640  */
 641
 642 /*
 643  * Miscellaneous configurable options
 644  */
 645 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
 646
 647 /*
 648  * For booting Linux, the board info and command line data
 649  * have to be in the first 64 MB of memory, since this is
 650  * the maximum mapped by the Linux kernel during initialization.
 651  */
 652 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 653 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 654
 655 #ifdef CONFIG_CMD_KGDB
 656 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 657 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 658 #endif
 659
 660 /*
 661  * Environment Configuration
 662  */
 663 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 664 #define CONFIG_BOOTFILE  "uImage"
 665 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 666
 667 /* default location for tftp and bootm */
 668 #define CONFIG_LOADADDR         1000000
 669 #define __USB_PHY_TYPE          utmi
 670
 671 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 672         "hwconfig=fsl_ddr:"                                     \
 673         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 674         "bank_intlv=auto;"                                      \
 675         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 676         "netdev=eth0\0"                                         \
 677         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 678         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 679         "tftpflash=tftpboot $loadaddr $uboot && "               \
 680         "protect off $ubootaddr +$filesize && "                 \
 681         "erase $ubootaddr +$filesize && "                       \
 682         "cp.b $loadaddr $ubootaddr $filesize && "               \
 683         "protect on $ubootaddr +$filesize && "                  \
 684         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 685         "consoledev=ttyS0\0"                                    \
 686         "ramdiskaddr=2000000\0"                                 \
 687         "ramdiskfile=t2080rdb/ramdisk.uboot\0"                  \
 688         "fdtaddr=1e00000\0"                                     \
 689         "fdtfile=t2080rdb/t2080rdb.dtb\0"                       \
 690         "bdev=sda3\0"
 691
 692 /*
 693  * For emulation this causes u-boot to jump to the start of the
 694  * proof point app code automatically
 695  */
 696 #define CONFIG_PROOF_POINTS                             \
 697         "setenv bootargs root=/dev/$bdev rw "           \
 698         "console=$consoledev,$baudrate $othbootargs;"   \
 699         "cpu 1 release 0x29000000 - - -;"               \
 700         "cpu 2 release 0x29000000 - - -;"               \
 701         "cpu 3 release 0x29000000 - - -;"               \
 702         "cpu 4 release 0x29000000 - - -;"               \
 703         "cpu 5 release 0x29000000 - - -;"               \
 704         "cpu 6 release 0x29000000 - - -;"               \
 705         "cpu 7 release 0x29000000 - - -;"               \
 706         "go 0x29000000"
 707
 708 #define CONFIG_HVBOOT                           \
 709         "setenv bootargs config-addr=0x60000000; "      \
 710         "bootm 0x01000000 - 0x00f00000"
 711
 712 #define CONFIG_ALU                              \
 713         "setenv bootargs root=/dev/$bdev rw "           \
 714         "console=$consoledev,$baudrate $othbootargs;"   \
 715         "cpu 1 release 0x01000000 - - -;"               \
 716         "cpu 2 release 0x01000000 - - -;"               \
 717         "cpu 3 release 0x01000000 - - -;"               \
 718         "cpu 4 release 0x01000000 - - -;"               \
 719         "cpu 5 release 0x01000000 - - -;"               \
 720         "cpu 6 release 0x01000000 - - -;"               \
 721         "cpu 7 release 0x01000000 - - -;"               \
 722         "go 0x01000000"
 723
 724 #define CONFIG_LINUX                            \
 725         "setenv bootargs root=/dev/ram rw "             \
 726         "console=$consoledev,$baudrate $othbootargs;"   \
 727         "setenv ramdiskaddr 0x02000000;"                \
 728         "setenv fdtaddr 0x00c00000;"                    \
 729         "setenv loadaddr 0x1000000;"                    \
 730         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 731
 732 #define CONFIG_HDBOOT                                   \
 733         "setenv bootargs root=/dev/$bdev rw "           \
 734         "console=$consoledev,$baudrate $othbootargs;"   \
 735         "tftp $loadaddr $bootfile;"                     \
 736         "tftp $fdtaddr $fdtfile;"                       \
 737         "bootm $loadaddr - $fdtaddr"
 738
 739 #define CONFIG_NFSBOOTCOMMAND                   \
 740         "setenv bootargs root=/dev/nfs rw "     \
 741         "nfsroot=$serverip:$rootpath "          \
 742         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 743         "console=$consoledev,$baudrate $othbootargs;"   \
 744         "tftp $loadaddr $bootfile;"             \
 745         "tftp $fdtaddr $fdtfile;"               \
 746         "bootm $loadaddr - $fdtaddr"
 747
 748 #define CONFIG_RAMBOOTCOMMAND                           \
 749         "setenv bootargs root=/dev/ram rw "             \
 750         "console=$consoledev,$baudrate $othbootargs;"   \
 751         "tftp $ramdiskaddr $ramdiskfile;"               \
 752         "tftp $loadaddr $bootfile;"                     \
 753         "tftp $fdtaddr $fdtfile;"                       \
 754         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 755
 756 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 757
 758 #include <asm/fsl_secure_boot.h>
 759
 760 #endif  /* __T2080RDB_H */