include/configs/T208xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T2080 RDB/PCIe board configuration file
   9  */
  10
  11 #ifndef __T2080RDB_H
  12 #define __T2080RDB_H
  13
  14 #include <linux/stringify.h>
  15
  16 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  17
  18 /* High Level Configuration Options */
  19
  20 #define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  21
  22 #ifdef CONFIG_RAMBOOT_PBL
  23 #define RESET_VECTOR_OFFSET             0x27FFC
  24 #define BOOT_PAGE_OFFSET                0x27000
  25
  26 #ifdef CONFIG_MTD_RAW_NAND
  27 #define CFG_SYS_NAND_U_BOOT_SIZE        (768 << 10)
  28 #define CFG_SYS_NAND_U_BOOT_DST 0x00200000
  29 #define CFG_SYS_NAND_U_BOOT_START       0x00200000
  30 #endif
  31
  32 #ifdef CONFIG_SPIFLASH
  33 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  34 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
  35 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
  36 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
  37 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
  38 #endif
  39
  40 #ifdef CONFIG_SDCARD
  41 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  42 #define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
  43 #define CONFIG_SYS_MMC_U_BOOT_DST      (0x00200000)
  44 #define CONFIG_SYS_MMC_U_BOOT_START    (0x00200000)
  45 #define CONFIG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
  46 #endif
  47
  48 #endif /* CONFIG_RAMBOOT_PBL */
  49
  50 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  51 /* Set 1M boot space */
  52 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
  53 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  54                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  55 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  56 #endif
  57
  58 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  59 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  60 #endif
  61
  62 /*
  63  * These can be toggled for performance analysis, otherwise use default.
  64  */
  65 #ifdef CONFIG_DDR_ECC
  66 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  67 #endif
  68
  69 /*
  70  * Config the L3 Cache as L3 SRAM
  71  */
  72 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
  73 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
  74
  75 #define CONFIG_SYS_DCSRBAR      0xf0000000
  76 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  77
  78 /*
  79  * DDR Setup
  80  */
  81 #define CONFIG_VERY_BIG_RAM
  82 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  83 #define CFG_SYS_SDRAM_BASE              CONFIG_SYS_DDR_SDRAM_BASE
  84 #define CFG_SYS_SDRAM_SIZE      2048    /* for fixed parameter use */
  85 #define SPD_EEPROM_ADDRESS1     0x51
  86 #define SPD_EEPROM_ADDRESS2     0x52
  87 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  88 #define CTRL_INTLV_PREFERED     cacheline
  89
  90 /*
  91  * IFC Definitions
  92  */
  93 #define CONFIG_SYS_FLASH_BASE           0xe8000000
  94 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  95 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
  96 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  97                                 CSPR_PORT_SIZE_16 | \
  98                                 CSPR_MSEL_NOR | \
  99                                 CSPR_V)
 100 #define CFG_SYS_NOR_AMASK       IFC_AMASK(128*1024*1024)
 101
 102 /* NOR Flash Timing Params */
 103 #define CFG_SYS_NOR_CSOR        CSOR_NAND_TRHZ_80
 104
 105 #define CFG_SYS_NOR_FTIM0       (FTIM0_NOR_TACSE(0x4) | \
 106                                 FTIM0_NOR_TEADC(0x5) | \
 107                                 FTIM0_NOR_TEAHC(0x5))
 108 #define CFG_SYS_NOR_FTIM1       (FTIM1_NOR_TACO(0x35) | \
 109                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 110                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 111 #define CFG_SYS_NOR_FTIM2       (FTIM2_NOR_TCS(0x4) | \
 112                                 FTIM2_NOR_TCH(0x4) | \
 113                                 FTIM2_NOR_TWPH(0x0E) | \
 114                                 FTIM2_NOR_TWP(0x1c))
 115 #define CFG_SYS_NOR_FTIM3       0x0
 116
 117 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 118
 119 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS }
 120
 121 /* CPLD on IFC */
 122 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 123 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 124 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 125 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 126                                 | CSPR_PORT_SIZE_8 \
 127                                 | CSPR_MSEL_GPCM \
 128                                 | CSPR_V)
 129 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 130 #define CONFIG_SYS_CSOR2        0x0
 131
 132 /* CPLD Timing parameters for IFC CS2 */
 133 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 134                                         FTIM0_GPCM_TEADC(0x0e) | \
 135                                         FTIM0_GPCM_TEAHC(0x0e))
 136 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 137                                         FTIM1_GPCM_TRAD(0x1f))
 138 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 139                                         FTIM2_GPCM_TCH(0x8) | \
 140                                         FTIM2_GPCM_TWP(0x1f))
 141 #define CONFIG_SYS_CS2_FTIM3            0x0
 142
 143 /* NAND Flash on IFC */
 144 #define CFG_SYS_NAND_BASE               0xff800000
 145 #define CFG_SYS_NAND_BASE_PHYS  (0xf00000000ull | CFG_SYS_NAND_BASE)
 146
 147 #define CFG_SYS_NAND_CSPR_EXT   (0xf)
 148 #define CFG_SYS_NAND_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 149                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 150                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 151                                 | CSPR_V)
 152 #define CFG_SYS_NAND_AMASK      IFC_AMASK(64*1024)
 153
 154 #define CFG_SYS_NAND_CSOR       (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 155                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 156                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 157                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 158                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 159                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 160                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 161
 162 /* ONFI NAND Flash mode0 Timing Params */
 163 #define CFG_SYS_NAND_FTIM0              (FTIM0_NAND_TCCST(0x07) | \
 164                                         FTIM0_NAND_TWP(0x18)    | \
 165                                         FTIM0_NAND_TWCHT(0x07)  | \
 166                                         FTIM0_NAND_TWH(0x0a))
 167 #define CFG_SYS_NAND_FTIM1              (FTIM1_NAND_TADLE(0x32) | \
 168                                         FTIM1_NAND_TWBE(0x39)   | \
 169                                         FTIM1_NAND_TRR(0x0e)    | \
 170                                         FTIM1_NAND_TRP(0x18))
 171 #define CFG_SYS_NAND_FTIM2              (FTIM2_NAND_TRAD(0x0f)  | \
 172                                         FTIM2_NAND_TREH(0x0a)   | \
 173                                         FTIM2_NAND_TWHRE(0x1e))
 174 #define CFG_SYS_NAND_FTIM3              0x0
 175
 176 #define CFG_SYS_NAND_BASE_LIST  { CFG_SYS_NAND_BASE }
 177
 178 #if defined(CONFIG_MTD_RAW_NAND)
 179 #define CONFIG_SYS_CSPR0_EXT            CFG_SYS_NAND_CSPR_EXT
 180 #define CONFIG_SYS_CSPR0                CFG_SYS_NAND_CSPR
 181 #define CONFIG_SYS_AMASK0               CFG_SYS_NAND_AMASK
 182 #define CONFIG_SYS_CSOR0                CFG_SYS_NAND_CSOR
 183 #define CONFIG_SYS_CS0_FTIM0            CFG_SYS_NAND_FTIM0
 184 #define CONFIG_SYS_CS0_FTIM1            CFG_SYS_NAND_FTIM1
 185 #define CONFIG_SYS_CS0_FTIM2            CFG_SYS_NAND_FTIM2
 186 #define CONFIG_SYS_CS0_FTIM3            CFG_SYS_NAND_FTIM3
 187 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 188 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 189 #define CONFIG_SYS_AMASK1               CFG_SYS_NOR_AMASK
 190 #define CONFIG_SYS_CSOR1                CFG_SYS_NOR_CSOR
 191 #define CONFIG_SYS_CS1_FTIM0            CFG_SYS_NOR_FTIM0
 192 #define CONFIG_SYS_CS1_FTIM1            CFG_SYS_NOR_FTIM1
 193 #define CONFIG_SYS_CS1_FTIM2            CFG_SYS_NOR_FTIM2
 194 #define CONFIG_SYS_CS1_FTIM3            CFG_SYS_NOR_FTIM3
 195 #else
 196 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 197 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 198 #define CONFIG_SYS_AMASK0               CFG_SYS_NOR_AMASK
 199 #define CONFIG_SYS_CSOR0                CFG_SYS_NOR_CSOR
 200 #define CONFIG_SYS_CS0_FTIM0            CFG_SYS_NOR_FTIM0
 201 #define CONFIG_SYS_CS0_FTIM1            CFG_SYS_NOR_FTIM1
 202 #define CONFIG_SYS_CS0_FTIM2            CFG_SYS_NOR_FTIM2
 203 #define CONFIG_SYS_CS0_FTIM3            CFG_SYS_NOR_FTIM3
 204 #define CONFIG_SYS_CSPR1_EXT            CFG_SYS_NAND_CSPR_EXT
 205 #define CONFIG_SYS_CSPR1                CFG_SYS_NAND_CSPR
 206 #define CONFIG_SYS_AMASK1               CFG_SYS_NAND_AMASK
 207 #define CONFIG_SYS_CSOR1                CFG_SYS_NAND_CSOR
 208 #define CONFIG_SYS_CS1_FTIM0            CFG_SYS_NAND_FTIM0
 209 #define CONFIG_SYS_CS1_FTIM1            CFG_SYS_NAND_FTIM1
 210 #define CONFIG_SYS_CS1_FTIM2            CFG_SYS_NAND_FTIM2
 211 #define CONFIG_SYS_CS1_FTIM3            CFG_SYS_NAND_FTIM3
 212 #endif
 213
 214 #define CONFIG_HWCONFIG
 215
 216 /* define to use L1 as initial stack */
 217 #define CONFIG_L1_INIT_RAM
 218 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 219 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 220 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 221 /* The assembler doesn't like typecast */
 222 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 223                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 224                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 225 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 226 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 227
 228 /*
 229  * Serial Port
 230  */
 231 #define CFG_SYS_NS16550_CLK             (get_bus_freq(0)/2)
 232 #define CONFIG_SYS_BAUDRATE_TABLE       \
 233         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 234 #define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 235 #define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 236 #define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 237 #define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 238
 239 /*
 240  * I2C
 241  */
 242
 243 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 244 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 245 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 246 #define I2C_MUX_CH_DEFAULT      0x8
 247
 248 #define I2C_MUX_CH_VOL_MONITOR  0xa
 249
 250 /* The lowest and highest voltage allowed for T208xRDB */
 251 #define VDD_MV_MIN                      819
 252 #define VDD_MV_MAX                      1212
 253
 254 /*
 255  * RapidIO
 256  */
 257 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 258 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 259 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 260 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 261 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 262 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 263 /*
 264  * for slave u-boot IMAGE instored in master memory space,
 265  * PHYS must be aligned based on the SIZE
 266  */
 267 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 268 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 269 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 270 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 271 /*
 272  * for slave UCODE and ENV instored in master memory space,
 273  * PHYS must be aligned based on the SIZE
 274  */
 275 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 276 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 277 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 278
 279 /* slave core release by master*/
 280 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 281 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 282
 283 /*
 284  * SRIO_PCIE_BOOT - SLAVE
 285  */
 286 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 287 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 288 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 289                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 290 #endif
 291
 292 /*
 293  * eSPI - Enhanced SPI
 294  */
 295
 296 /*
 297  * General PCI
 298  * Memory space is mapped 1-1, but I/O space must start from 0.
 299  */
 300 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 301 #define CFG_SYS_PCIE1_MEM_VIRT  0x80000000
 302 #define CFG_SYS_PCIE1_MEM_PHYS  0xc00000000ull
 303 #define CFG_SYS_PCIE1_IO_VIRT   0xf8000000
 304 #define CFG_SYS_PCIE1_IO_PHYS   0xff8000000ull
 305
 306 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 307 #define CFG_SYS_PCIE2_MEM_VIRT  0xa0000000
 308 #define CFG_SYS_PCIE2_MEM_PHYS  0xc20000000ull
 309 #define CFG_SYS_PCIE2_IO_VIRT   0xf8010000
 310 #define CFG_SYS_PCIE2_IO_PHYS   0xff8010000ull
 311
 312 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 313 #define CFG_SYS_PCIE3_MEM_VIRT  0xb0000000
 314 #define CFG_SYS_PCIE3_MEM_PHYS  0xc30000000ull
 315
 316 /* controller 4, Base address 203000 */
 317 #define CFG_SYS_PCIE4_MEM_VIRT       0xc0000000
 318 #define CFG_SYS_PCIE4_MEM_PHYS  0xc40000000ull
 319
 320 /* Qman/Bman */
 321 #ifndef CONFIG_NOBQFMAN
 322 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 323 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 324 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 325 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 326 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 327 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 328 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 329 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 330 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 331                                         CONFIG_SYS_BMAN_CENA_SIZE)
 332 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 333 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 334 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 335 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 336 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 337 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 338 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 339 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 340 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 341                                         CONFIG_SYS_QMAN_CENA_SIZE)
 342 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 343 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 344 #endif /* CONFIG_NOBQFMAN */
 345
 346 #ifdef CONFIG_SYS_DPAA_FMAN
 347 #define RGMII_PHY1_ADDR         0x01  /* RealTek RTL8211E */
 348 #define RGMII_PHY2_ADDR         0x02
 349 #define CORTINA_PHY_ADDR1       0x0c  /* Cortina CS4315 */
 350 #define CORTINA_PHY_ADDR2       0x0d
 351 /* Aquantia AQ1202 10G Base-T used by board revisions up to C */
 352 #define FM1_10GEC3_PHY_ADDR     0x00
 353 #define FM1_10GEC4_PHY_ADDR     0x01
 354 /* Aquantia AQR113C 10G Base-T used by board revisions D and up */
 355 #define AQR113C_PHY_ADDR1       0x00
 356 #define AQR113C_PHY_ADDR2       0x08
 357 #endif
 358
 359 /*
 360  * USB
 361  */
 362
 363 /*
 364  * SDHC
 365  */
 366 #ifdef CONFIG_MMC
 367 #define CFG_SYS_FSL_ESDHC_ADDR  CFG_SYS_MPC85xx_ESDHC_ADDR
 368 #endif
 369
 370 /*
 371  * Dynamic MTD Partition support with mtdparts
 372  */
 373
 374 /*
 375  * Environment
 376  */
 377
 378 /*
 379  * Miscellaneous configurable options
 380  */
 381
 382 /*
 383  * For booting Linux, the board info and command line data
 384  * have to be in the first 64 MB of memory, since this is
 385  * the maximum mapped by the Linux kernel during initialization.
 386  */
 387 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 388
 389 /*
 390  * Environment Configuration
 391  */
 392 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 393 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 394
 395 #define __USB_PHY_TYPE          utmi
 396
 397 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 398         "hwconfig=fsl_ddr:"                                     \
 399         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 400         "bank_intlv=auto;"                                      \
 401         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 402         "netdev=eth0\0"                                         \
 403         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 404         "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
 405         "tftpflash=tftpboot $loadaddr $uboot && "               \
 406         "protect off $ubootaddr +$filesize && "                 \
 407         "erase $ubootaddr +$filesize && "                       \
 408         "cp.b $loadaddr $ubootaddr $filesize && "               \
 409         "protect on $ubootaddr +$filesize && "                  \
 410         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 411         "consoledev=ttyS0\0"                                    \
 412         "ramdiskaddr=2000000\0"                                 \
 413         "ramdiskfile=t2080rdb/ramdisk.uboot\0"                  \
 414         "fdtaddr=1e00000\0"                                     \
 415         "fdtfile=t2080rdb/t2080rdb.dtb\0"                       \
 416         "bdev=sda3\0"
 417
 418 /*
 419  * For emulation this causes u-boot to jump to the start of the
 420  * proof point app code automatically
 421  */
 422 #define PROOF_POINTS                            \
 423         "setenv bootargs root=/dev/$bdev rw "           \
 424         "console=$consoledev,$baudrate $othbootargs;"   \
 425         "cpu 1 release 0x29000000 - - -;"               \
 426         "cpu 2 release 0x29000000 - - -;"               \
 427         "cpu 3 release 0x29000000 - - -;"               \
 428         "cpu 4 release 0x29000000 - - -;"               \
 429         "cpu 5 release 0x29000000 - - -;"               \
 430         "cpu 6 release 0x29000000 - - -;"               \
 431         "cpu 7 release 0x29000000 - - -;"               \
 432         "go 0x29000000"
 433
 434 #define HVBOOT                          \
 435         "setenv bootargs config-addr=0x60000000; "      \
 436         "bootm 0x01000000 - 0x00f00000"
 437
 438 #define ALU                             \
 439         "setenv bootargs root=/dev/$bdev rw "           \
 440         "console=$consoledev,$baudrate $othbootargs;"   \
 441         "cpu 1 release 0x01000000 - - -;"               \
 442         "cpu 2 release 0x01000000 - - -;"               \
 443         "cpu 3 release 0x01000000 - - -;"               \
 444         "cpu 4 release 0x01000000 - - -;"               \
 445         "cpu 5 release 0x01000000 - - -;"               \
 446         "cpu 6 release 0x01000000 - - -;"               \
 447         "cpu 7 release 0x01000000 - - -;"               \
 448         "go 0x01000000"
 449
 450 #include <asm/fsl_secure_boot.h>
 451
 452 #endif  /* __T2080RDB_H */