Merge tag 'efi-2020-01-rc5' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
[platform/kernel/u-boot.git] / include / configs / T208xRDB.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2014 Freescale Semiconductor, Inc.
4  */
5
6 /*
7  * T2080 RDB/PCIe board configuration file
8  */
9
10 #ifndef __T2080RDB_H
11 #define __T2080RDB_H
12
13 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
14 #define CONFIG_FSL_SATA_V2
15
16 /* High Level Configuration Options */
17 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
18 #define CONFIG_ENABLE_36BIT_PHYS
19
20 #ifdef CONFIG_PHYS_64BIT
21 #define CONFIG_ADDR_MAP 1
22 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
23 #endif
24
25 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
26 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
27 #define CONFIG_ENV_OVERWRITE
28
29 #ifdef CONFIG_RAMBOOT_PBL
30 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
31
32 #define CONFIG_SPL_FLUSH_IMAGE
33 #define CONFIG_SPL_PAD_TO               0x40000
34 #define CONFIG_SPL_MAX_SIZE             0x28000
35 #define RESET_VECTOR_OFFSET             0x27FFC
36 #define BOOT_PAGE_OFFSET                0x27000
37 #ifdef CONFIG_SPL_BUILD
38 #define CONFIG_SPL_SKIP_RELOCATE
39 #define CONFIG_SPL_COMMON_INIT_DDR
40 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
41 #endif
42
43 #ifdef CONFIG_NAND
44 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
45 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
46 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
47 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
48 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg
49 #endif
50
51 #ifdef CONFIG_SPIFLASH
52 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
53 #define CONFIG_SPL_SPI_FLASH_MINIMAL
54 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
55 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
56 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
57 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
58 #ifndef CONFIG_SPL_BUILD
59 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
60 #endif
61 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg
62 #endif
63
64 #ifdef CONFIG_SDCARD
65 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
66 #define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
67 #define CONFIG_SYS_MMC_U_BOOT_DST      (0x00200000)
68 #define CONFIG_SYS_MMC_U_BOOT_START    (0x00200000)
69 #define CONFIG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
70 #ifndef CONFIG_SPL_BUILD
71 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
72 #endif
73 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg
74 #endif
75
76 #endif /* CONFIG_RAMBOOT_PBL */
77
78 #define CONFIG_SRIO_PCIE_BOOT_MASTER
79 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
80 /* Set 1M boot space */
81 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
82 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
83                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
84 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
85 #endif
86
87 #ifndef CONFIG_RESET_VECTOR_ADDRESS
88 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
89 #endif
90
91 /*
92  * These can be toggled for performance analysis, otherwise use default.
93  */
94 #define CONFIG_SYS_CACHE_STASHING
95 #define CONFIG_BTB              /* toggle branch predition */
96 #define CONFIG_DDR_ECC
97 #ifdef CONFIG_DDR_ECC
98 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
99 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
100 #endif
101
102 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
103 #define CONFIG_SYS_MEMTEST_END          0x00400000
104
105 #if defined(CONFIG_SPIFLASH)
106 #elif defined(CONFIG_SDCARD)
107 #define CONFIG_SYS_MMC_ENV_DEV  0
108 #endif
109
110 #ifndef __ASSEMBLY__
111 unsigned long get_board_sys_clk(void);
112 unsigned long get_board_ddr_clk(void);
113 #endif
114
115 #define CONFIG_SYS_CLK_FREQ     66660000
116 #define CONFIG_DDR_CLK_FREQ     133330000
117
118 /*
119  * Config the L3 Cache as L3 SRAM
120  */
121 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
122 #define CONFIG_SYS_L3_SIZE              (512 << 10)
123 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
124 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
125 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
126 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
127 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
128
129 #define CONFIG_SYS_DCSRBAR      0xf0000000
130 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
131
132 /* EEPROM */
133 #define CONFIG_ID_EEPROM
134 #define CONFIG_SYS_I2C_EEPROM_NXID
135 #define CONFIG_SYS_EEPROM_BUS_NUM       0
136 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
137 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
138
139 /*
140  * DDR Setup
141  */
142 #define CONFIG_VERY_BIG_RAM
143 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
144 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
145 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
146 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
147 #define CONFIG_DDR_SPD
148 #define CONFIG_SYS_SPD_BUS_NUM  0
149 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
150 #define SPD_EEPROM_ADDRESS1     0x51
151 #define SPD_EEPROM_ADDRESS2     0x52
152 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
153 #define CTRL_INTLV_PREFERED     cacheline
154
155 /*
156  * IFC Definitions
157  */
158 #define CONFIG_SYS_FLASH_BASE           0xe8000000
159 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
160 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
161 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
162                                 CSPR_PORT_SIZE_16 | \
163                                 CSPR_MSEL_NOR | \
164                                 CSPR_V)
165 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
166
167 /* NOR Flash Timing Params */
168 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
169
170 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
171                                 FTIM0_NOR_TEADC(0x5) | \
172                                 FTIM0_NOR_TEAHC(0x5))
173 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
174                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
175                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
176 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
177                                 FTIM2_NOR_TCH(0x4) | \
178                                 FTIM2_NOR_TWPH(0x0E) | \
179                                 FTIM2_NOR_TWP(0x1c))
180 #define CONFIG_SYS_NOR_FTIM3    0x0
181
182 #define CONFIG_SYS_FLASH_QUIET_TEST
183 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
184
185 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
186 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
187 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
188 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
189 #define CONFIG_SYS_FLASH_EMPTY_INFO
190 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS }
191
192 /* CPLD on IFC */
193 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
194 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
195 #define CONFIG_SYS_CSPR2_EXT    (0xf)
196 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
197                                 | CSPR_PORT_SIZE_8 \
198                                 | CSPR_MSEL_GPCM \
199                                 | CSPR_V)
200 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
201 #define CONFIG_SYS_CSOR2        0x0
202
203 /* CPLD Timing parameters for IFC CS2 */
204 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
205                                         FTIM0_GPCM_TEADC(0x0e) | \
206                                         FTIM0_GPCM_TEAHC(0x0e))
207 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
208                                         FTIM1_GPCM_TRAD(0x1f))
209 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
210                                         FTIM2_GPCM_TCH(0x8) | \
211                                         FTIM2_GPCM_TWP(0x1f))
212 #define CONFIG_SYS_CS2_FTIM3            0x0
213
214 /* NAND Flash on IFC */
215 #define CONFIG_NAND_FSL_IFC
216 #define CONFIG_SYS_NAND_BASE            0xff800000
217 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
218
219 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
220 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
221                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
222                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
223                                 | CSPR_V)
224 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
225
226 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
227                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
228                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
229                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
230                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
231                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
232                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
233
234 #define CONFIG_SYS_NAND_ONFI_DETECTION
235
236 /* ONFI NAND Flash mode0 Timing Params */
237 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
238                                         FTIM0_NAND_TWP(0x18)    | \
239                                         FTIM0_NAND_TWCHT(0x07)  | \
240                                         FTIM0_NAND_TWH(0x0a))
241 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
242                                         FTIM1_NAND_TWBE(0x39)   | \
243                                         FTIM1_NAND_TRR(0x0e)    | \
244                                         FTIM1_NAND_TRP(0x18))
245 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
246                                         FTIM2_NAND_TREH(0x0a)   | \
247                                         FTIM2_NAND_TWHRE(0x1e))
248 #define CONFIG_SYS_NAND_FTIM3           0x0
249
250 #define CONFIG_SYS_NAND_DDR_LAW         11
251 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
252 #define CONFIG_SYS_MAX_NAND_DEVICE      1
253 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
254
255 #if defined(CONFIG_NAND)
256 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
257 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
258 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
259 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
260 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
261 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
262 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
263 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
264 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
265 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
266 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
267 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
268 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
269 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
270 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
271 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
272 #else
273 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
274 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
275 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
276 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
277 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
278 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
279 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
280 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
281 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
282 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
283 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
284 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
285 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
286 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
287 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
288 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
289 #endif
290
291 #if defined(CONFIG_RAMBOOT_PBL)
292 #define CONFIG_SYS_RAMBOOT
293 #endif
294
295 #ifdef CONFIG_SPL_BUILD
296 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SPL_TEXT_BASE
297 #else
298 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SYS_TEXT_BASE /* start of monitor */
299 #endif
300
301 #define CONFIG_HWCONFIG
302
303 /* define to use L1 as initial stack */
304 #define CONFIG_L1_INIT_RAM
305 #define CONFIG_SYS_INIT_RAM_LOCK
306 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
307 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
308 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
309 /* The assembler doesn't like typecast */
310 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
311                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
312                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
313 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
314 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
315                                                 GENERATED_GBL_DATA_SIZE)
316 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
317 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
318 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
319
320 /*
321  * Serial Port
322  */
323 #define CONFIG_SYS_NS16550_SERIAL
324 #define CONFIG_SYS_NS16550_REG_SIZE     1
325 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
326 #define CONFIG_SYS_BAUDRATE_TABLE       \
327         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
328 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
329 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
330 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
331 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
332
333 /*
334  * I2C
335  */
336 #define CONFIG_SYS_I2C
337 #define CONFIG_SYS_I2C_FSL
338 #define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
339 #define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
340 #define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
341 #define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
342 #define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
343 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
344 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
345 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
346 #define CONFIG_SYS_FSL_I2C_SPEED   100000
347 #define CONFIG_SYS_FSL_I2C2_SPEED  100000
348 #define CONFIG_SYS_FSL_I2C3_SPEED  100000
349 #define CONFIG_SYS_FSL_I2C4_SPEED  100000
350 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
351 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
352 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
353 #define I2C_MUX_CH_DEFAULT      0x8
354
355 #define I2C_MUX_CH_VOL_MONITOR  0xa
356
357 #define CONFIG_VID_FLS_ENV              "t208xrdb_vdd_mv"
358 #ifndef CONFIG_SPL_BUILD
359 #define CONFIG_VID
360 #endif
361 #define CONFIG_VOL_MONITOR_IR36021_SET
362 #define CONFIG_VOL_MONITOR_IR36021_READ
363 /* The lowest and highest voltage allowed for T208xRDB */
364 #define VDD_MV_MIN                      819
365 #define VDD_MV_MAX                      1212
366
367 /*
368  * RapidIO
369  */
370 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
371 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
372 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
373 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
374 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
375 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
376 /*
377  * for slave u-boot IMAGE instored in master memory space,
378  * PHYS must be aligned based on the SIZE
379  */
380 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
381 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
382 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
383 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
384 /*
385  * for slave UCODE and ENV instored in master memory space,
386  * PHYS must be aligned based on the SIZE
387  */
388 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
389 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
390 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
391
392 /* slave core release by master*/
393 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
394 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
395
396 /*
397  * SRIO_PCIE_BOOT - SLAVE
398  */
399 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
400 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
401 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
402                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
403 #endif
404
405 /*
406  * eSPI - Enhanced SPI
407  */
408
409 /*
410  * General PCI
411  * Memory space is mapped 1-1, but I/O space must start from 0.
412  */
413 #define CONFIG_PCIE1            /* PCIE controller 1 */
414 #define CONFIG_PCIE2            /* PCIE controller 2 */
415 #define CONFIG_PCIE3            /* PCIE controller 3 */
416 #define CONFIG_PCIE4            /* PCIE controller 4 */
417 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
418 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
419 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
420 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
421 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
422 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
423
424 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
425 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
426 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
427 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
428 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
429
430 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
431 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
432 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
433 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
434 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
435
436 /* controller 4, Base address 203000 */
437 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
438 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
439 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
440
441 #ifdef CONFIG_PCI
442 #if !defined(CONFIG_DM_PCI)
443 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
444 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
445 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
446 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
447 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
448 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
449 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000 /* 256M */
450 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
451 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
452 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
453 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
454 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
455 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
456 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
457 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
458 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
459 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
460 #define CONFIG_PCI_INDIRECT_BRIDGE
461 #endif
462 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
463 #endif
464
465 /* Qman/Bman */
466 #ifndef CONFIG_NOBQFMAN
467 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
468 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
469 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
470 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
471 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
472 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
473 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
474 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
475 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
476                                         CONFIG_SYS_BMAN_CENA_SIZE)
477 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
478 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
479 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
480 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
481 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
482 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
483 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
484 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
485 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
486 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
487 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
488                                         CONFIG_SYS_QMAN_CENA_SIZE)
489 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
490 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
491
492 #define CONFIG_SYS_DPAA_FMAN
493 #define CONFIG_SYS_DPAA_PME
494 #define CONFIG_SYS_PMAN
495 #define CONFIG_SYS_DPAA_DCE
496 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
497 #define CONFIG_SYS_INTERLAKEN
498
499 /* Default address of microcode for the Linux Fman driver */
500 #if defined(CONFIG_SPIFLASH)
501 /*
502  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
503  * env, so we got 0x110000.
504  */
505 #define CONFIG_SYS_FMAN_FW_ADDR         0x110000
506 #define CONFIG_CORTINA_FW_ADDR          0x120000
507
508 #elif defined(CONFIG_SDCARD)
509 /*
510  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
511  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
512  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
513  */
514 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
515 #define CONFIG_CORTINA_FW_ADDR          (512 * 0x8a0)
516
517 #elif defined(CONFIG_NAND)
518 #define CONFIG_SYS_FMAN_FW_ADDR         (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
519 #define CONFIG_CORTINA_FW_ADDR          (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
520 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
521 /*
522  * Slave has no ucode locally, it can fetch this from remote. When implementing
523  * in two corenet boards, slave's ucode could be stored in master's memory
524  * space, the address can be mapped from slave TLB->slave LAW->
525  * slave SRIO or PCIE outbound window->master inbound window->
526  * master LAW->the ucode address in master's memory space.
527  */
528 #define CONFIG_SYS_FMAN_FW_ADDR         0xFFE00000
529 #define CONFIG_CORTINA_FW_ADDR          0xFFE10000
530 #else
531 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
532 #define CONFIG_CORTINA_FW_ADDR          0xEFE00000
533 #endif
534 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
535 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
536 #endif /* CONFIG_NOBQFMAN */
537
538 #ifdef CONFIG_SYS_DPAA_FMAN
539 #define CONFIG_PHY_REALTEK
540 #define CONFIG_CORTINA_FW_LENGTH        0x40000
541 #define RGMII_PHY1_ADDR         0x01  /* RealTek RTL8211E */
542 #define RGMII_PHY2_ADDR         0x02
543 #define CORTINA_PHY_ADDR1       0x0c  /* Cortina CS4315 */
544 #define CORTINA_PHY_ADDR2       0x0d
545 #define FM1_10GEC3_PHY_ADDR     0x00  /* Aquantia AQ1202 10G Base-T */
546 #define FM1_10GEC4_PHY_ADDR     0x01
547 #endif
548
549 #ifdef CONFIG_FMAN_ENET
550 #define CONFIG_ETHPRIME         "FM1@DTSEC3"
551 #endif
552
553 /*
554  * SATA
555  */
556 #ifdef CONFIG_FSL_SATA_V2
557 #define CONFIG_SYS_SATA_MAX_DEVICE      2
558 #define CONFIG_SATA1
559 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
560 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
561 #define CONFIG_SATA2
562 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
563 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
564 #define CONFIG_LBA48
565 #endif
566
567 /*
568  * USB
569  */
570 #ifdef CONFIG_USB_EHCI_HCD
571 #define CONFIG_USB_EHCI_FSL
572 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
573 #define CONFIG_HAS_FSL_DR_USB
574 #endif
575
576 /*
577  * SDHC
578  */
579 #ifdef CONFIG_MMC
580 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
581 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
582 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
583 #endif
584
585 /*
586  * Dynamic MTD Partition support with mtdparts
587  */
588
589 /*
590  * Environment
591  */
592
593 /*
594  * Miscellaneous configurable options
595  */
596 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
597
598 /*
599  * For booting Linux, the board info and command line data
600  * have to be in the first 64 MB of memory, since this is
601  * the maximum mapped by the Linux kernel during initialization.
602  */
603 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
604 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
605
606 #ifdef CONFIG_CMD_KGDB
607 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
608 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
609 #endif
610
611 /*
612  * Environment Configuration
613  */
614 #define CONFIG_ROOTPATH  "/opt/nfsroot"
615 #define CONFIG_BOOTFILE  "uImage"
616 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
617
618 /* default location for tftp and bootm */
619 #define CONFIG_LOADADDR         1000000
620 #define __USB_PHY_TYPE          utmi
621
622 #define CONFIG_EXTRA_ENV_SETTINGS                               \
623         "hwconfig=fsl_ddr:"                                     \
624         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
625         "bank_intlv=auto;"                                      \
626         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
627         "netdev=eth0\0"                                         \
628         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
629         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
630         "tftpflash=tftpboot $loadaddr $uboot && "               \
631         "protect off $ubootaddr +$filesize && "                 \
632         "erase $ubootaddr +$filesize && "                       \
633         "cp.b $loadaddr $ubootaddr $filesize && "               \
634         "protect on $ubootaddr +$filesize && "                  \
635         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
636         "consoledev=ttyS0\0"                                    \
637         "ramdiskaddr=2000000\0"                                 \
638         "ramdiskfile=t2080rdb/ramdisk.uboot\0"                  \
639         "fdtaddr=1e00000\0"                                     \
640         "fdtfile=t2080rdb/t2080rdb.dtb\0"                       \
641         "bdev=sda3\0"
642
643 /*
644  * For emulation this causes u-boot to jump to the start of the
645  * proof point app code automatically
646  */
647 #define CONFIG_PROOF_POINTS                             \
648         "setenv bootargs root=/dev/$bdev rw "           \
649         "console=$consoledev,$baudrate $othbootargs;"   \
650         "cpu 1 release 0x29000000 - - -;"               \
651         "cpu 2 release 0x29000000 - - -;"               \
652         "cpu 3 release 0x29000000 - - -;"               \
653         "cpu 4 release 0x29000000 - - -;"               \
654         "cpu 5 release 0x29000000 - - -;"               \
655         "cpu 6 release 0x29000000 - - -;"               \
656         "cpu 7 release 0x29000000 - - -;"               \
657         "go 0x29000000"
658
659 #define CONFIG_HVBOOT                           \
660         "setenv bootargs config-addr=0x60000000; "      \
661         "bootm 0x01000000 - 0x00f00000"
662
663 #define CONFIG_ALU                              \
664         "setenv bootargs root=/dev/$bdev rw "           \
665         "console=$consoledev,$baudrate $othbootargs;"   \
666         "cpu 1 release 0x01000000 - - -;"               \
667         "cpu 2 release 0x01000000 - - -;"               \
668         "cpu 3 release 0x01000000 - - -;"               \
669         "cpu 4 release 0x01000000 - - -;"               \
670         "cpu 5 release 0x01000000 - - -;"               \
671         "cpu 6 release 0x01000000 - - -;"               \
672         "cpu 7 release 0x01000000 - - -;"               \
673         "go 0x01000000"
674
675 #define CONFIG_LINUX                            \
676         "setenv bootargs root=/dev/ram rw "             \
677         "console=$consoledev,$baudrate $othbootargs;"   \
678         "setenv ramdiskaddr 0x02000000;"                \
679         "setenv fdtaddr 0x00c00000;"                    \
680         "setenv loadaddr 0x1000000;"                    \
681         "bootm $loadaddr $ramdiskaddr $fdtaddr"
682
683 #define CONFIG_HDBOOT                                   \
684         "setenv bootargs root=/dev/$bdev rw "           \
685         "console=$consoledev,$baudrate $othbootargs;"   \
686         "tftp $loadaddr $bootfile;"                     \
687         "tftp $fdtaddr $fdtfile;"                       \
688         "bootm $loadaddr - $fdtaddr"
689
690 #define CONFIG_NFSBOOTCOMMAND                   \
691         "setenv bootargs root=/dev/nfs rw "     \
692         "nfsroot=$serverip:$rootpath "          \
693         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
694         "console=$consoledev,$baudrate $othbootargs;"   \
695         "tftp $loadaddr $bootfile;"             \
696         "tftp $fdtaddr $fdtfile;"               \
697         "bootm $loadaddr - $fdtaddr"
698
699 #define CONFIG_RAMBOOTCOMMAND                           \
700         "setenv bootargs root=/dev/ram rw "             \
701         "console=$consoledev,$baudrate $othbootargs;"   \
702         "tftp $ramdiskaddr $ramdiskfile;"               \
703         "tftp $loadaddr $bootfile;"                     \
704         "tftp $fdtaddr $fdtfile;"                       \
705         "bootm $loadaddr $ramdiskaddr $fdtaddr"
706
707 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
708
709 #include <asm/fsl_secure_boot.h>
710
711 #endif  /* __T2080RDB_H */