1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
8 * T2080 RDB/PCIe board configuration file
14 #include <linux/stringify.h>
16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
18 /* High Level Configuration Options */
20 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
22 #ifdef CONFIG_RAMBOOT_PBL
23 #define RESET_VECTOR_OFFSET 0x27FFC
24 #define BOOT_PAGE_OFFSET 0x27000
26 #ifdef CONFIG_MTD_RAW_NAND
27 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
28 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
29 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
32 #ifdef CONFIG_SPIFLASH
33 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
34 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
35 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
36 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
37 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
41 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
42 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
43 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
44 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
45 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
48 #endif /* CONFIG_RAMBOOT_PBL */
50 #define CONFIG_SRIO_PCIE_BOOT_MASTER
51 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
52 /* Set 1M boot space */
53 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
54 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
55 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
56 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
59 #ifndef CONFIG_RESET_VECTOR_ADDRESS
60 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
64 * These can be toggled for performance analysis, otherwise use default.
67 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
71 * Config the L3 Cache as L3 SRAM
73 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
74 #define CONFIG_SYS_L3_SIZE (512 << 10)
75 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
77 #define CONFIG_SYS_DCSRBAR 0xf0000000
78 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
81 #define CONFIG_SYS_I2C_EEPROM_NXID
82 #define CONFIG_SYS_EEPROM_BUS_NUM 0
87 #define CONFIG_VERY_BIG_RAM
88 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
89 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
90 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
91 #define SPD_EEPROM_ADDRESS1 0x51
92 #define SPD_EEPROM_ADDRESS2 0x52
93 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
94 #define CTRL_INTLV_PREFERED cacheline
99 #define CONFIG_SYS_FLASH_BASE 0xe8000000
100 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
101 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
102 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
103 CSPR_PORT_SIZE_16 | \
106 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
108 /* NOR Flash Timing Params */
109 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
111 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
112 FTIM0_NOR_TEADC(0x5) | \
113 FTIM0_NOR_TEAHC(0x5))
114 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
115 FTIM1_NOR_TRAD_NOR(0x1A) |\
116 FTIM1_NOR_TSEQRAD_NOR(0x13))
117 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
118 FTIM2_NOR_TCH(0x4) | \
119 FTIM2_NOR_TWPH(0x0E) | \
121 #define CONFIG_SYS_NOR_FTIM3 0x0
123 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
125 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS }
128 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
129 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
130 #define CONFIG_SYS_CSPR2_EXT (0xf)
131 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
135 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
136 #define CONFIG_SYS_CSOR2 0x0
138 /* CPLD Timing parameters for IFC CS2 */
139 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
140 FTIM0_GPCM_TEADC(0x0e) | \
141 FTIM0_GPCM_TEAHC(0x0e))
142 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
143 FTIM1_GPCM_TRAD(0x1f))
144 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
145 FTIM2_GPCM_TCH(0x8) | \
146 FTIM2_GPCM_TWP(0x1f))
147 #define CONFIG_SYS_CS2_FTIM3 0x0
149 /* NAND Flash on IFC */
150 #define CONFIG_SYS_NAND_BASE 0xff800000
151 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
153 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
154 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
155 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
156 | CSPR_MSEL_NAND /* MSEL = NAND */ \
158 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
160 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
161 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
162 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
163 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
164 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
165 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
166 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
168 /* ONFI NAND Flash mode0 Timing Params */
169 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
170 FTIM0_NAND_TWP(0x18) | \
171 FTIM0_NAND_TWCHT(0x07) | \
172 FTIM0_NAND_TWH(0x0a))
173 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
174 FTIM1_NAND_TWBE(0x39) | \
175 FTIM1_NAND_TRR(0x0e) | \
176 FTIM1_NAND_TRP(0x18))
177 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
178 FTIM2_NAND_TREH(0x0a) | \
179 FTIM2_NAND_TWHRE(0x1e))
180 #define CONFIG_SYS_NAND_FTIM3 0x0
182 #define CONFIG_SYS_NAND_DDR_LAW 11
183 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
184 #define CONFIG_SYS_MAX_NAND_DEVICE 1
186 #if defined(CONFIG_MTD_RAW_NAND)
187 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
188 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
189 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
190 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
191 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
192 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
193 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
194 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
195 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
196 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
197 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
198 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
199 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
200 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
201 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
202 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
204 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
205 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
206 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
207 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
208 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
209 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
210 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
211 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
212 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
213 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
214 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
215 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
216 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
217 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
218 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
219 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
222 #define CONFIG_HWCONFIG
224 /* define to use L1 as initial stack */
225 #define CONFIG_L1_INIT_RAM
226 #define CONFIG_SYS_INIT_RAM_LOCK
227 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
228 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
229 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
230 /* The assembler doesn't like typecast */
231 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
232 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
233 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
234 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
235 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
236 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
241 #define CONFIG_SYS_NS16550_SERIAL
242 #define CONFIG_SYS_NS16550_REG_SIZE 1
243 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
244 #define CONFIG_SYS_BAUDRATE_TABLE \
245 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
246 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
247 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
248 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
249 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
255 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
256 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
257 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
258 #define I2C_MUX_CH_DEFAULT 0x8
260 #define I2C_MUX_CH_VOL_MONITOR 0xa
262 /* The lowest and highest voltage allowed for T208xRDB */
263 #define VDD_MV_MIN 819
264 #define VDD_MV_MAX 1212
269 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
270 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
271 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
272 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
273 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
274 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
276 * for slave u-boot IMAGE instored in master memory space,
277 * PHYS must be aligned based on the SIZE
279 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
280 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
281 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
282 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
284 * for slave UCODE and ENV instored in master memory space,
285 * PHYS must be aligned based on the SIZE
287 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
288 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
289 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
291 /* slave core release by master*/
292 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
293 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
296 * SRIO_PCIE_BOOT - SLAVE
298 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
299 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
300 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
301 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
305 * eSPI - Enhanced SPI
310 * Memory space is mapped 1-1, but I/O space must start from 0.
312 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
313 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
314 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
315 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
316 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
318 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
319 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
320 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
321 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
322 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
324 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
325 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
326 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
327 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
328 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
330 /* controller 4, Base address 203000 */
331 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
332 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
333 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
336 #ifndef CONFIG_NOBQFMAN
337 #define CONFIG_SYS_BMAN_NUM_PORTALS 18
338 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
339 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
340 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
341 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
342 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
343 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
344 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
345 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
346 CONFIG_SYS_BMAN_CENA_SIZE)
347 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
348 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
349 #define CONFIG_SYS_QMAN_NUM_PORTALS 18
350 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
351 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
352 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
353 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
354 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
355 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
356 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
357 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
358 CONFIG_SYS_QMAN_CENA_SIZE)
359 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
360 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
362 #define CONFIG_SYS_DPAA_FMAN
363 #define CONFIG_SYS_DPAA_PME
364 #define CONFIG_SYS_PMAN
365 #define CONFIG_SYS_DPAA_DCE
366 #define CONFIG_SYS_DPAA_RMAN /* RMan */
367 #define CONFIG_SYS_INTERLAKEN
368 #endif /* CONFIG_NOBQFMAN */
370 #ifdef CONFIG_SYS_DPAA_FMAN
371 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
372 #define RGMII_PHY2_ADDR 0x02
373 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */
374 #define CORTINA_PHY_ADDR2 0x0d
375 /* Aquantia AQ1202 10G Base-T used by board revisions up to C */
376 #define FM1_10GEC3_PHY_ADDR 0x00
377 #define FM1_10GEC4_PHY_ADDR 0x01
378 /* Aquantia AQR113C 10G Base-T used by board revisions D and up */
379 #define AQR113C_PHY_ADDR1 0x00
380 #define AQR113C_PHY_ADDR2 0x08
391 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
395 * Dynamic MTD Partition support with mtdparts
403 * Miscellaneous configurable options
407 * For booting Linux, the board info and command line data
408 * have to be in the first 64 MB of memory, since this is
409 * the maximum mapped by the Linux kernel during initialization.
411 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
414 * Environment Configuration
416 #define CONFIG_ROOTPATH "/opt/nfsroot"
417 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
419 #define __USB_PHY_TYPE utmi
421 #define CONFIG_EXTRA_ENV_SETTINGS \
422 "hwconfig=fsl_ddr:" \
423 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
425 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
427 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
428 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
429 "tftpflash=tftpboot $loadaddr $uboot && " \
430 "protect off $ubootaddr +$filesize && " \
431 "erase $ubootaddr +$filesize && " \
432 "cp.b $loadaddr $ubootaddr $filesize && " \
433 "protect on $ubootaddr +$filesize && " \
434 "cmp.b $loadaddr $ubootaddr $filesize\0" \
435 "consoledev=ttyS0\0" \
436 "ramdiskaddr=2000000\0" \
437 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \
438 "fdtaddr=1e00000\0" \
439 "fdtfile=t2080rdb/t2080rdb.dtb\0" \
443 * For emulation this causes u-boot to jump to the start of the
444 * proof point app code automatically
446 #define PROOF_POINTS \
447 "setenv bootargs root=/dev/$bdev rw " \
448 "console=$consoledev,$baudrate $othbootargs;" \
449 "cpu 1 release 0x29000000 - - -;" \
450 "cpu 2 release 0x29000000 - - -;" \
451 "cpu 3 release 0x29000000 - - -;" \
452 "cpu 4 release 0x29000000 - - -;" \
453 "cpu 5 release 0x29000000 - - -;" \
454 "cpu 6 release 0x29000000 - - -;" \
455 "cpu 7 release 0x29000000 - - -;" \
459 "setenv bootargs config-addr=0x60000000; " \
460 "bootm 0x01000000 - 0x00f00000"
463 "setenv bootargs root=/dev/$bdev rw " \
464 "console=$consoledev,$baudrate $othbootargs;" \
465 "cpu 1 release 0x01000000 - - -;" \
466 "cpu 2 release 0x01000000 - - -;" \
467 "cpu 3 release 0x01000000 - - -;" \
468 "cpu 4 release 0x01000000 - - -;" \
469 "cpu 5 release 0x01000000 - - -;" \
470 "cpu 6 release 0x01000000 - - -;" \
471 "cpu 7 release 0x01000000 - - -;" \
474 #include <asm/fsl_secure_boot.h>
476 #endif /* __T2080RDB_H */