include/configs/T208xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 /*
   8  * T2080 RDB/PCIe board configuration file
   9  */
  10
  11 #ifndef __T2080RDB_H
  12 #define __T2080RDB_H
  13
  14 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  15 #define CONFIG_FSL_SATA_V2
  16
  17 /* High Level Configuration Options */
  18 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
  19 #define CONFIG_ENABLE_36BIT_PHYS
  20
  21 #ifdef CONFIG_PHYS_64BIT
  22 #define CONFIG_ADDR_MAP 1
  23 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  24 #endif
  25
  26 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  27 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  28 #define CONFIG_ENV_OVERWRITE
  29
  30 #ifdef CONFIG_RAMBOOT_PBL
  31 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
  32
  33 #define CONFIG_SPL_FLUSH_IMAGE
  34 #define CONFIG_SPL_PAD_TO               0x40000
  35 #define CONFIG_SPL_MAX_SIZE             0x28000
  36 #define RESET_VECTOR_OFFSET             0x27FFC
  37 #define BOOT_PAGE_OFFSET                0x27000
  38 #ifdef CONFIG_SPL_BUILD
  39 #define CONFIG_SPL_SKIP_RELOCATE
  40 #define CONFIG_SPL_COMMON_INIT_DDR
  41 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  42 #endif
  43
  44 #ifdef CONFIG_MTD_RAW_NAND
  45 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  46 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  47 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  48 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  49 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg
  50 #endif
  51
  52 #ifdef CONFIG_SPIFLASH
  53 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  54 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  55 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
  56 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
  57 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
  58 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
  59 #ifndef CONFIG_SPL_BUILD
  60 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  61 #endif
  62 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg
  63 #endif
  64
  65 #ifdef CONFIG_SDCARD
  66 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  67 #define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
  68 #define CONFIG_SYS_MMC_U_BOOT_DST      (0x00200000)
  69 #define CONFIG_SYS_MMC_U_BOOT_START    (0x00200000)
  70 #define CONFIG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
  71 #ifndef CONFIG_SPL_BUILD
  72 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  73 #endif
  74 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg
  75 #endif
  76
  77 #endif /* CONFIG_RAMBOOT_PBL */
  78
  79 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  80 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  81 /* Set 1M boot space */
  82 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  83 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  84                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  85 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  86 #endif
  87
  88 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  89 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  90 #endif
  91
  92 /*
  93  * These can be toggled for performance analysis, otherwise use default.
  94  */
  95 #define CONFIG_SYS_CACHE_STASHING
  96 #define CONFIG_BTB              /* toggle branch predition */
  97 #define CONFIG_DDR_ECC
  98 #ifdef CONFIG_DDR_ECC
  99 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 100 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 101 #endif
 102
 103 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
 104 #define CONFIG_SYS_MEMTEST_END          0x00400000
 105
 106 #if defined(CONFIG_SPIFLASH)
 107 #elif defined(CONFIG_SDCARD)
 108 #define CONFIG_SYS_MMC_ENV_DEV  0
 109 #endif
 110
 111 #ifndef __ASSEMBLY__
 112 unsigned long get_board_sys_clk(void);
 113 unsigned long get_board_ddr_clk(void);
 114 #endif
 115
 116 #define CONFIG_SYS_CLK_FREQ     66660000
 117 #define CONFIG_DDR_CLK_FREQ     133330000
 118
 119 /*
 120  * Config the L3 Cache as L3 SRAM
 121  */
 122 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 123 #define CONFIG_SYS_L3_SIZE              (512 << 10)
 124 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 125 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
 126 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 127 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
 128 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 129
 130 #define CONFIG_SYS_DCSRBAR      0xf0000000
 131 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
 132
 133 /* EEPROM */
 134 #define CONFIG_ID_EEPROM
 135 #define CONFIG_SYS_I2C_EEPROM_NXID
 136 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 137 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 138 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 139
 140 /*
 141  * DDR Setup
 142  */
 143 #define CONFIG_VERY_BIG_RAM
 144 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 145 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 146 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 147 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 148 #define CONFIG_DDR_SPD
 149 #define CONFIG_SYS_SPD_BUS_NUM  0
 150 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 151 #define SPD_EEPROM_ADDRESS1     0x51
 152 #define SPD_EEPROM_ADDRESS2     0x52
 153 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 154 #define CTRL_INTLV_PREFERED     cacheline
 155
 156 /*
 157  * IFC Definitions
 158  */
 159 #define CONFIG_SYS_FLASH_BASE           0xe8000000
 160 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 161 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 162 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 163                                 CSPR_PORT_SIZE_16 | \
 164                                 CSPR_MSEL_NOR | \
 165                                 CSPR_V)
 166 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 167
 168 /* NOR Flash Timing Params */
 169 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 170
 171 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 172                                 FTIM0_NOR_TEADC(0x5) | \
 173                                 FTIM0_NOR_TEAHC(0x5))
 174 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 175                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 176                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 177 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 178                                 FTIM2_NOR_TCH(0x4) | \
 179                                 FTIM2_NOR_TWPH(0x0E) | \
 180                                 FTIM2_NOR_TWP(0x1c))
 181 #define CONFIG_SYS_NOR_FTIM3    0x0
 182
 183 #define CONFIG_SYS_FLASH_QUIET_TEST
 184 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 185
 186 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 187 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 188 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 189 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 190 #define CONFIG_SYS_FLASH_EMPTY_INFO
 191 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS }
 192
 193 /* CPLD on IFC */
 194 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 195 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 196 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 197 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 198                                 | CSPR_PORT_SIZE_8 \
 199                                 | CSPR_MSEL_GPCM \
 200                                 | CSPR_V)
 201 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 202 #define CONFIG_SYS_CSOR2        0x0
 203
 204 /* CPLD Timing parameters for IFC CS2 */
 205 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 206                                         FTIM0_GPCM_TEADC(0x0e) | \
 207                                         FTIM0_GPCM_TEAHC(0x0e))
 208 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 209                                         FTIM1_GPCM_TRAD(0x1f))
 210 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 211                                         FTIM2_GPCM_TCH(0x8) | \
 212                                         FTIM2_GPCM_TWP(0x1f))
 213 #define CONFIG_SYS_CS2_FTIM3            0x0
 214
 215 /* NAND Flash on IFC */
 216 #define CONFIG_NAND_FSL_IFC
 217 #define CONFIG_SYS_NAND_BASE            0xff800000
 218 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 219
 220 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 221 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 222                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 223                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 224                                 | CSPR_V)
 225 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 226
 227 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 228                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 229                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 230                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 231                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 232                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 233                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 234
 235 #define CONFIG_SYS_NAND_ONFI_DETECTION
 236
 237 /* ONFI NAND Flash mode0 Timing Params */
 238 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 239                                         FTIM0_NAND_TWP(0x18)    | \
 240                                         FTIM0_NAND_TWCHT(0x07)  | \
 241                                         FTIM0_NAND_TWH(0x0a))
 242 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 243                                         FTIM1_NAND_TWBE(0x39)   | \
 244                                         FTIM1_NAND_TRR(0x0e)    | \
 245                                         FTIM1_NAND_TRP(0x18))
 246 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 247                                         FTIM2_NAND_TREH(0x0a)   | \
 248                                         FTIM2_NAND_TWHRE(0x1e))
 249 #define CONFIG_SYS_NAND_FTIM3           0x0
 250
 251 #define CONFIG_SYS_NAND_DDR_LAW         11
 252 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 253 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 254 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 255
 256 #if defined(CONFIG_MTD_RAW_NAND)
 257 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 258 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 259 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 260 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 261 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 262 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 263 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 264 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 265 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 266 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 267 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 268 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 269 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 270 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 271 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 272 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 273 #else
 274 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 275 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 276 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 277 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 278 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 279 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 280 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 281 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 282 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 283 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 284 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 285 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 286 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 287 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 288 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 289 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 290 #endif
 291
 292 #if defined(CONFIG_RAMBOOT_PBL)
 293 #define CONFIG_SYS_RAMBOOT
 294 #endif
 295
 296 #ifdef CONFIG_SPL_BUILD
 297 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SPL_TEXT_BASE
 298 #else
 299 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SYS_TEXT_BASE /* start of monitor */
 300 #endif
 301
 302 #define CONFIG_HWCONFIG
 303
 304 /* define to use L1 as initial stack */
 305 #define CONFIG_L1_INIT_RAM
 306 #define CONFIG_SYS_INIT_RAM_LOCK
 307 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 308 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 309 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 310 /* The assembler doesn't like typecast */
 311 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 312                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 313                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 314 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 315 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 316                                                 GENERATED_GBL_DATA_SIZE)
 317 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 318 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 319 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 320
 321 /*
 322  * Serial Port
 323  */
 324 #define CONFIG_SYS_NS16550_SERIAL
 325 #define CONFIG_SYS_NS16550_REG_SIZE     1
 326 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 327 #define CONFIG_SYS_BAUDRATE_TABLE       \
 328         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 329 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 330 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 331 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 332 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 333
 334 /*
 335  * I2C
 336  */
 337 #ifndef CONFIG_DM_I2C
 338 #define CONFIG_SYS_I2C
 339 #define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
 340 #define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
 341 #define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
 342 #define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
 343 #define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
 344 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
 345 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
 346 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
 347 #define CONFIG_SYS_FSL_I2C_SPEED   100000
 348 #define CONFIG_SYS_FSL_I2C2_SPEED  100000
 349 #define CONFIG_SYS_FSL_I2C3_SPEED  100000
 350 #define CONFIG_SYS_FSL_I2C4_SPEED  100000
 351 #else
 352 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
 353 #define CONFIG_I2C_DEFAULT_BUS_NUMBER   0
 354 #endif
 355
 356 #define CONFIG_SYS_I2C_FSL
 357
 358 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 359 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 360 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 361 #define I2C_MUX_CH_DEFAULT      0x8
 362
 363 #define I2C_MUX_CH_VOL_MONITOR  0xa
 364
 365 #define CONFIG_VID_FLS_ENV              "t208xrdb_vdd_mv"
 366 #ifndef CONFIG_SPL_BUILD
 367 #define CONFIG_VID
 368 #endif
 369 #define CONFIG_VOL_MONITOR_IR36021_SET
 370 #define CONFIG_VOL_MONITOR_IR36021_READ
 371 /* The lowest and highest voltage allowed for T208xRDB */
 372 #define VDD_MV_MIN                      819
 373 #define VDD_MV_MAX                      1212
 374
 375 /*
 376  * RapidIO
 377  */
 378 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 379 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 380 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 381 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 382 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 383 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 384 /*
 385  * for slave u-boot IMAGE instored in master memory space,
 386  * PHYS must be aligned based on the SIZE
 387  */
 388 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 389 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 390 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 391 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 392 /*
 393  * for slave UCODE and ENV instored in master memory space,
 394  * PHYS must be aligned based on the SIZE
 395  */
 396 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 397 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 398 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 399
 400 /* slave core release by master*/
 401 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 402 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 403
 404 /*
 405  * SRIO_PCIE_BOOT - SLAVE
 406  */
 407 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 408 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 409 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 410                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 411 #endif
 412
 413 /*
 414  * eSPI - Enhanced SPI
 415  */
 416
 417 /*
 418  * General PCI
 419  * Memory space is mapped 1-1, but I/O space must start from 0.
 420  */
 421 #define CONFIG_PCIE1            /* PCIE controller 1 */
 422 #define CONFIG_PCIE2            /* PCIE controller 2 */
 423 #define CONFIG_PCIE3            /* PCIE controller 3 */
 424 #define CONFIG_PCIE4            /* PCIE controller 4 */
 425 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 426 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 427 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 428 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 429 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 430 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 431
 432 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 433 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 434 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 435 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 436 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 437
 438 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 439 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 440 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 441 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 442 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 443
 444 /* controller 4, Base address 203000 */
 445 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 446 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 447 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 448
 449 #ifdef CONFIG_PCI
 450 #if !defined(CONFIG_DM_PCI)
 451 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 452 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 453 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 454 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 455 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 456 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 457 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000 /* 256M */
 458 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 459 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 460 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 461 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 462 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 463 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 464 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 465 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 466 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 467 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 468 #define CONFIG_PCI_INDIRECT_BRIDGE
 469 #endif
 470 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 471 #endif
 472
 473 /* Qman/Bman */
 474 #ifndef CONFIG_NOBQFMAN
 475 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 476 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 477 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 478 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 479 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 480 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 481 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 482 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 483 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 484                                         CONFIG_SYS_BMAN_CENA_SIZE)
 485 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 486 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 487 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 488 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 489 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 490 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 491 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 492 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 493 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 494 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 495 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 496                                         CONFIG_SYS_QMAN_CENA_SIZE)
 497 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 498 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 499
 500 #define CONFIG_SYS_DPAA_FMAN
 501 #define CONFIG_SYS_DPAA_PME
 502 #define CONFIG_SYS_PMAN
 503 #define CONFIG_SYS_DPAA_DCE
 504 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 505 #define CONFIG_SYS_INTERLAKEN
 506
 507 /* Default address of microcode for the Linux Fman driver */
 508 #if defined(CONFIG_SPIFLASH)
 509 /*
 510  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 511  * env, so we got 0x110000.
 512  */
 513 #define CONFIG_SYS_FMAN_FW_ADDR         0x110000
 514 #define CONFIG_CORTINA_FW_ADDR          0x120000
 515
 516 #elif defined(CONFIG_SDCARD)
 517 /*
 518  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 519  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 520  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 521  */
 522 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 523 #define CONFIG_CORTINA_FW_ADDR          (512 * 0x8a0)
 524
 525 #elif defined(CONFIG_MTD_RAW_NAND)
 526 #define CONFIG_SYS_FMAN_FW_ADDR         (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 527 #define CONFIG_CORTINA_FW_ADDR          (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
 528 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 529 /*
 530  * Slave has no ucode locally, it can fetch this from remote. When implementing
 531  * in two corenet boards, slave's ucode could be stored in master's memory
 532  * space, the address can be mapped from slave TLB->slave LAW->
 533  * slave SRIO or PCIE outbound window->master inbound window->
 534  * master LAW->the ucode address in master's memory space.
 535  */
 536 #define CONFIG_SYS_FMAN_FW_ADDR         0xFFE00000
 537 #define CONFIG_CORTINA_FW_ADDR          0xFFE10000
 538 #else
 539 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 540 #define CONFIG_CORTINA_FW_ADDR          0xEFE00000
 541 #endif
 542 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 543 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 544 #endif /* CONFIG_NOBQFMAN */
 545
 546 #ifdef CONFIG_SYS_DPAA_FMAN
 547 #define CONFIG_CORTINA_FW_LENGTH        0x40000
 548 #define RGMII_PHY1_ADDR         0x01  /* RealTek RTL8211E */
 549 #define RGMII_PHY2_ADDR         0x02
 550 #define CORTINA_PHY_ADDR1       0x0c  /* Cortina CS4315 */
 551 #define CORTINA_PHY_ADDR2       0x0d
 552 #define FM1_10GEC3_PHY_ADDR     0x00  /* Aquantia AQ1202 10G Base-T */
 553 #define FM1_10GEC4_PHY_ADDR     0x01
 554 #endif
 555
 556 #ifdef CONFIG_FMAN_ENET
 557 #define CONFIG_ETHPRIME         "FM1@DTSEC3"
 558 #endif
 559
 560 /*
 561  * SATA
 562  */
 563 #ifdef CONFIG_FSL_SATA_V2
 564 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 565 #define CONFIG_SATA1
 566 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 567 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 568 #define CONFIG_SATA2
 569 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 570 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 571 #define CONFIG_LBA48
 572 #endif
 573
 574 /*
 575  * USB
 576  */
 577 #ifdef CONFIG_USB_EHCI_HCD
 578 #define CONFIG_USB_EHCI_FSL
 579 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 580 #define CONFIG_HAS_FSL_DR_USB
 581 #endif
 582
 583 /*
 584  * SDHC
 585  */
 586 #ifdef CONFIG_MMC
 587 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 588 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 589 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 590 #endif
 591
 592 /*
 593  * Dynamic MTD Partition support with mtdparts
 594  */
 595
 596 /*
 597  * Environment
 598  */
 599
 600 /*
 601  * Miscellaneous configurable options
 602  */
 603 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
 604
 605 /*
 606  * For booting Linux, the board info and command line data
 607  * have to be in the first 64 MB of memory, since this is
 608  * the maximum mapped by the Linux kernel during initialization.
 609  */
 610 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 611 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 612
 613 #ifdef CONFIG_CMD_KGDB
 614 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 615 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 616 #endif
 617
 618 /*
 619  * Environment Configuration
 620  */
 621 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 622 #define CONFIG_BOOTFILE  "uImage"
 623 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 624
 625 /* default location for tftp and bootm */
 626 #define CONFIG_LOADADDR         1000000
 627 #define __USB_PHY_TYPE          utmi
 628
 629 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 630         "hwconfig=fsl_ddr:"                                     \
 631         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 632         "bank_intlv=auto;"                                      \
 633         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 634         "netdev=eth0\0"                                         \
 635         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 636         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 637         "tftpflash=tftpboot $loadaddr $uboot && "               \
 638         "protect off $ubootaddr +$filesize && "                 \
 639         "erase $ubootaddr +$filesize && "                       \
 640         "cp.b $loadaddr $ubootaddr $filesize && "               \
 641         "protect on $ubootaddr +$filesize && "                  \
 642         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 643         "consoledev=ttyS0\0"                                    \
 644         "ramdiskaddr=2000000\0"                                 \
 645         "ramdiskfile=t2080rdb/ramdisk.uboot\0"                  \
 646         "fdtaddr=1e00000\0"                                     \
 647         "fdtfile=t2080rdb/t2080rdb.dtb\0"                       \
 648         "bdev=sda3\0"
 649
 650 /*
 651  * For emulation this causes u-boot to jump to the start of the
 652  * proof point app code automatically
 653  */
 654 #define CONFIG_PROOF_POINTS                             \
 655         "setenv bootargs root=/dev/$bdev rw "           \
 656         "console=$consoledev,$baudrate $othbootargs;"   \
 657         "cpu 1 release 0x29000000 - - -;"               \
 658         "cpu 2 release 0x29000000 - - -;"               \
 659         "cpu 3 release 0x29000000 - - -;"               \
 660         "cpu 4 release 0x29000000 - - -;"               \
 661         "cpu 5 release 0x29000000 - - -;"               \
 662         "cpu 6 release 0x29000000 - - -;"               \
 663         "cpu 7 release 0x29000000 - - -;"               \
 664         "go 0x29000000"
 665
 666 #define CONFIG_HVBOOT                           \
 667         "setenv bootargs config-addr=0x60000000; "      \
 668         "bootm 0x01000000 - 0x00f00000"
 669
 670 #define CONFIG_ALU                              \
 671         "setenv bootargs root=/dev/$bdev rw "           \
 672         "console=$consoledev,$baudrate $othbootargs;"   \
 673         "cpu 1 release 0x01000000 - - -;"               \
 674         "cpu 2 release 0x01000000 - - -;"               \
 675         "cpu 3 release 0x01000000 - - -;"               \
 676         "cpu 4 release 0x01000000 - - -;"               \
 677         "cpu 5 release 0x01000000 - - -;"               \
 678         "cpu 6 release 0x01000000 - - -;"               \
 679         "cpu 7 release 0x01000000 - - -;"               \
 680         "go 0x01000000"
 681
 682 #define CONFIG_LINUX                            \
 683         "setenv bootargs root=/dev/ram rw "             \
 684         "console=$consoledev,$baudrate $othbootargs;"   \
 685         "setenv ramdiskaddr 0x02000000;"                \
 686         "setenv fdtaddr 0x00c00000;"                    \
 687         "setenv loadaddr 0x1000000;"                    \
 688         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 689
 690 #define CONFIG_HDBOOT                                   \
 691         "setenv bootargs root=/dev/$bdev rw "           \
 692         "console=$consoledev,$baudrate $othbootargs;"   \
 693         "tftp $loadaddr $bootfile;"                     \
 694         "tftp $fdtaddr $fdtfile;"                       \
 695         "bootm $loadaddr - $fdtaddr"
 696
 697 #define CONFIG_NFSBOOTCOMMAND                   \
 698         "setenv bootargs root=/dev/nfs rw "     \
 699         "nfsroot=$serverip:$rootpath "          \
 700         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 701         "console=$consoledev,$baudrate $othbootargs;"   \
 702         "tftp $loadaddr $bootfile;"             \
 703         "tftp $fdtaddr $fdtfile;"               \
 704         "bootm $loadaddr - $fdtaddr"
 705
 706 #define CONFIG_RAMBOOTCOMMAND                           \
 707         "setenv bootargs root=/dev/ram rw "             \
 708         "console=$consoledev,$baudrate $othbootargs;"   \
 709         "tftp $ramdiskaddr $ramdiskfile;"               \
 710         "tftp $loadaddr $bootfile;"                     \
 711         "tftp $fdtaddr $fdtfile;"                       \
 712         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 713
 714 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 715
 716 #include <asm/fsl_secure_boot.h>
 717
 718 #endif  /* __T2080RDB_H */