include/configs/T208xRDB.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * T2080 RDB/PCIe board configuration file
   9  */
  10
  11 #ifndef __T2080RDB_H
  12 #define __T2080RDB_H
  13
  14 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  15 #define CONFIG_USB_EHCI
  16 #define CONFIG_FSL_SATA_V2
  17
  18 /* High Level Configuration Options */
  19 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
  20 #define CONFIG_MP               /* support multiple processors */
  21 #define CONFIG_ENABLE_36BIT_PHYS
  22
  23 #ifdef CONFIG_PHYS_64BIT
  24 #define CONFIG_ADDR_MAP 1
  25 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  26 #endif
  27
  28 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  29 #define CONFIG_SYS_NUM_CPC      CONFIG_NUM_DDR_CONTROLLERS
  30 #define CONFIG_FSL_IFC          /* Enable IFC Support */
  31 #define CONFIG_FSL_CAAM         /* Enable SEC/CAAM */
  32 #define CONFIG_ENV_OVERWRITE
  33
  34 #ifdef CONFIG_RAMBOOT_PBL
  35 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
  36
  37 #define CONFIG_SPL_FLUSH_IMAGE
  38 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  39 #define CONFIG_SYS_TEXT_BASE            0x00201000
  40 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  41 #define CONFIG_SPL_PAD_TO               0x40000
  42 #define CONFIG_SPL_MAX_SIZE             0x28000
  43 #define RESET_VECTOR_OFFSET             0x27FFC
  44 #define BOOT_PAGE_OFFSET                0x27000
  45 #ifdef CONFIG_SPL_BUILD
  46 #define CONFIG_SPL_SKIP_RELOCATE
  47 #define CONFIG_SPL_COMMON_INIT_DDR
  48 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  49 #define CONFIG_SYS_NO_FLASH
  50 #endif
  51
  52 #ifdef CONFIG_NAND
  53 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  54 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  55 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  56 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  57 #define CONFIG_SYS_LDSCRIPT  "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  58 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg
  59 #define CONFIG_SPL_NAND_BOOT
  60 #endif
  61
  62 #ifdef CONFIG_SPIFLASH
  63 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  64 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
  66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
  67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
  68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
  69 #define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  70 #ifndef CONFIG_SPL_BUILD
  71 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  72 #endif
  73 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg
  74 #define CONFIG_SPL_SPI_BOOT
  75 #endif
  76
  77 #ifdef CONFIG_SDCARD
  78 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  79 #define CONFIG_SPL_MMC_MINIMAL
  80 #define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
  81 #define CONFIG_SYS_MMC_U_BOOT_DST      (0x00200000)
  82 #define CONFIG_SYS_MMC_U_BOOT_START    (0x00200000)
  83 #define CONFIG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
  84 #define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  85 #ifndef CONFIG_SPL_BUILD
  86 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  87 #endif
  88 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg
  89 #define CONFIG_SPL_MMC_BOOT
  90 #endif
  91
  92 #endif /* CONFIG_RAMBOOT_PBL */
  93
  94 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  95 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  96 /* Set 1M boot space */
  97 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  98 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  99                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 100 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 101 #define CONFIG_SYS_NO_FLASH
 102 #endif
 103
 104 #ifndef CONFIG_SYS_TEXT_BASE
 105 #define CONFIG_SYS_TEXT_BASE    0xeff40000
 106 #endif
 107
 108 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 109 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 110 #endif
 111
 112 /*
 113  * These can be toggled for performance analysis, otherwise use default.
 114  */
 115 #define CONFIG_SYS_CACHE_STASHING
 116 #define CONFIG_BTB              /* toggle branch predition */
 117 #define CONFIG_DDR_ECC
 118 #ifdef CONFIG_DDR_ECC
 119 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 120 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 121 #endif
 122
 123 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
 124 #define CONFIG_SYS_MEMTEST_END          0x00400000
 125 #define CONFIG_SYS_ALT_MEMTEST
 126
 127 #ifndef CONFIG_SYS_NO_FLASH
 128 #define CONFIG_FLASH_CFI_DRIVER
 129 #define CONFIG_SYS_FLASH_CFI
 130 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 131 #endif
 132
 133 #if defined(CONFIG_SPIFLASH)
 134 #define CONFIG_SYS_EXTRA_ENV_RELOC
 135 #define CONFIG_ENV_IS_IN_SPI_FLASH
 136 #define CONFIG_ENV_SPI_BUS      0
 137 #define CONFIG_ENV_SPI_CS       0
 138 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 139 #define CONFIG_ENV_SPI_MODE     0
 140 #define CONFIG_ENV_SIZE         0x2000     /* 8KB */
 141 #define CONFIG_ENV_OFFSET       0x100000   /* 1MB */
 142 #define CONFIG_ENV_SECT_SIZE    0x10000
 143 #elif defined(CONFIG_SDCARD)
 144 #define CONFIG_SYS_EXTRA_ENV_RELOC
 145 #define CONFIG_ENV_IS_IN_MMC
 146 #define CONFIG_SYS_MMC_ENV_DEV  0
 147 #define CONFIG_ENV_SIZE         0x2000
 148 #define CONFIG_ENV_OFFSET       (512 * 0x800)
 149 #elif defined(CONFIG_NAND)
 150 #define CONFIG_SYS_EXTRA_ENV_RELOC
 151 #define CONFIG_ENV_IS_IN_NAND
 152 #define CONFIG_ENV_SIZE         0x2000
 153 #define CONFIG_ENV_OFFSET       (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
 154 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 155 #define CONFIG_ENV_IS_IN_REMOTE
 156 #define CONFIG_ENV_ADDR         0xffe20000
 157 #define CONFIG_ENV_SIZE         0x2000
 158 #elif defined(CONFIG_ENV_IS_NOWHERE)
 159 #define CONFIG_ENV_SIZE         0x2000
 160 #else
 161 #define CONFIG_ENV_IS_IN_FLASH
 162 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 163 #define CONFIG_ENV_SIZE         0x2000
 164 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 165 #endif
 166
 167 #ifndef __ASSEMBLY__
 168 unsigned long get_board_sys_clk(void);
 169 unsigned long get_board_ddr_clk(void);
 170 #endif
 171
 172 #define CONFIG_SYS_CLK_FREQ     66660000
 173 #define CONFIG_DDR_CLK_FREQ     133330000
 174
 175 /*
 176  * Config the L3 Cache as L3 SRAM
 177  */
 178 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 179 #define CONFIG_SYS_L3_SIZE              (512 << 10)
 180 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 181 #ifdef CONFIG_RAMBOOT_PBL
 182 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 183 #endif
 184 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 185 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
 186 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 187 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 188
 189 #define CONFIG_SYS_DCSRBAR      0xf0000000
 190 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
 191
 192 /* EEPROM */
 193 #define CONFIG_ID_EEPROM
 194 #define CONFIG_SYS_I2C_EEPROM_NXID
 195 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 196 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 197 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 198
 199 /*
 200  * DDR Setup
 201  */
 202 #define CONFIG_VERY_BIG_RAM
 203 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 204 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 205 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 206 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 207 #define CONFIG_DDR_SPD
 208 #define CONFIG_SYS_FSL_DDR3
 209 #undef CONFIG_FSL_DDR_INTERACTIVE
 210 #define CONFIG_SYS_SPD_BUS_NUM  0
 211 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 212 #define SPD_EEPROM_ADDRESS1     0x51
 213 #define SPD_EEPROM_ADDRESS2     0x52
 214 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 215 #define CTRL_INTLV_PREFERED     cacheline
 216
 217 /*
 218  * IFC Definitions
 219  */
 220 #define CONFIG_SYS_FLASH_BASE           0xe8000000
 221 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 222 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 223 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 224                                 CSPR_PORT_SIZE_16 | \
 225                                 CSPR_MSEL_NOR | \
 226                                 CSPR_V)
 227 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 228
 229 /* NOR Flash Timing Params */
 230 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 231
 232 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 233                                 FTIM0_NOR_TEADC(0x5) | \
 234                                 FTIM0_NOR_TEAHC(0x5))
 235 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 236                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 237                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 238 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 239                                 FTIM2_NOR_TCH(0x4) | \
 240                                 FTIM2_NOR_TWPH(0x0E) | \
 241                                 FTIM2_NOR_TWP(0x1c))
 242 #define CONFIG_SYS_NOR_FTIM3    0x0
 243
 244 #define CONFIG_SYS_FLASH_QUIET_TEST
 245 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 246
 247 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 248 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 249 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 250 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 251 #define CONFIG_SYS_FLASH_EMPTY_INFO
 252 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS }
 253
 254 /* CPLD on IFC */
 255 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 256 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 257 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 258 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 259                                 | CSPR_PORT_SIZE_8 \
 260                                 | CSPR_MSEL_GPCM \
 261                                 | CSPR_V)
 262 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 263 #define CONFIG_SYS_CSOR2        0x0
 264
 265 /* CPLD Timing parameters for IFC CS2 */
 266 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 267                                         FTIM0_GPCM_TEADC(0x0e) | \
 268                                         FTIM0_GPCM_TEAHC(0x0e))
 269 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 270                                         FTIM1_GPCM_TRAD(0x1f))
 271 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 272                                         FTIM2_GPCM_TCH(0x8) | \
 273                                         FTIM2_GPCM_TWP(0x1f))
 274 #define CONFIG_SYS_CS2_FTIM3            0x0
 275
 276 /* NAND Flash on IFC */
 277 #define CONFIG_NAND_FSL_IFC
 278 #define CONFIG_SYS_NAND_BASE            0xff800000
 279 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 280
 281 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 282 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 283                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 284                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 285                                 | CSPR_V)
 286 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 287
 288 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 289                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 290                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 291                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 292                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 293                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 294                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 295
 296 #define CONFIG_SYS_NAND_ONFI_DETECTION
 297
 298 /* ONFI NAND Flash mode0 Timing Params */
 299 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 300                                         FTIM0_NAND_TWP(0x18)    | \
 301                                         FTIM0_NAND_TWCHT(0x07)  | \
 302                                         FTIM0_NAND_TWH(0x0a))
 303 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 304                                         FTIM1_NAND_TWBE(0x39)   | \
 305                                         FTIM1_NAND_TRR(0x0e)    | \
 306                                         FTIM1_NAND_TRP(0x18))
 307 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 308                                         FTIM2_NAND_TREH(0x0a)   | \
 309                                         FTIM2_NAND_TWHRE(0x1e))
 310 #define CONFIG_SYS_NAND_FTIM3           0x0
 311
 312 #define CONFIG_SYS_NAND_DDR_LAW         11
 313 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 314 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 315 #define CONFIG_CMD_NAND
 316 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 317
 318 #if defined(CONFIG_NAND)
 319 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 320 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 321 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 322 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 323 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 324 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 325 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 326 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 327 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 328 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 329 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 330 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 331 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 332 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 333 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 334 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 335 #else
 336 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 337 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 338 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 339 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 340 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 341 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 342 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 343 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 344 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 345 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 346 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 347 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 348 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 349 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 350 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 351 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 352 #endif
 353
 354 #if defined(CONFIG_RAMBOOT_PBL)
 355 #define CONFIG_SYS_RAMBOOT
 356 #endif
 357
 358 #ifdef CONFIG_SPL_BUILD
 359 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SPL_TEXT_BASE
 360 #else
 361 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SYS_TEXT_BASE /* start of monitor */
 362 #endif
 363
 364 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 365 #define CONFIG_MISC_INIT_R
 366 #define CONFIG_HWCONFIG
 367
 368 /* define to use L1 as initial stack */
 369 #define CONFIG_L1_INIT_RAM
 370 #define CONFIG_SYS_INIT_RAM_LOCK
 371 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 372 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 373 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 374 /* The assembler doesn't like typecast */
 375 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 376                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 377                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 378 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 379 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 380                                                 GENERATED_GBL_DATA_SIZE)
 381 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 382 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 383 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 384
 385 /*
 386  * Serial Port
 387  */
 388 #define CONFIG_CONS_INDEX               1
 389 #define CONFIG_SYS_NS16550_SERIAL
 390 #define CONFIG_SYS_NS16550_REG_SIZE     1
 391 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 392 #define CONFIG_SYS_BAUDRATE_TABLE       \
 393         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 394 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 395 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 396 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 397 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 398
 399 /*
 400  * I2C
 401  */
 402 #define CONFIG_SYS_I2C
 403 #define CONFIG_SYS_I2C_FSL
 404 #define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
 405 #define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
 406 #define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
 407 #define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
 408 #define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
 409 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
 410 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
 411 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
 412 #define CONFIG_SYS_FSL_I2C_SPEED   100000
 413 #define CONFIG_SYS_FSL_I2C2_SPEED  100000
 414 #define CONFIG_SYS_FSL_I2C3_SPEED  100000
 415 #define CONFIG_SYS_FSL_I2C4_SPEED  100000
 416 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 417 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 418 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 419 #define I2C_MUX_CH_DEFAULT      0x8
 420
 421 #define I2C_MUX_CH_VOL_MONITOR  0xa
 422
 423 #define CONFIG_VID_FLS_ENV              "t208xrdb_vdd_mv"
 424 #ifndef CONFIG_SPL_BUILD
 425 #define CONFIG_VID
 426 #endif
 427 #define CONFIG_VOL_MONITOR_IR36021_SET
 428 #define CONFIG_VOL_MONITOR_IR36021_READ
 429 /* The lowest and highest voltage allowed for T208xRDB */
 430 #define VDD_MV_MIN                      819
 431 #define VDD_MV_MAX                      1212
 432
 433 /*
 434  * RapidIO
 435  */
 436 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 437 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 438 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 439 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 440 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 441 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 442 /*
 443  * for slave u-boot IMAGE instored in master memory space,
 444  * PHYS must be aligned based on the SIZE
 445  */
 446 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 447 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 448 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 449 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 450 /*
 451  * for slave UCODE and ENV instored in master memory space,
 452  * PHYS must be aligned based on the SIZE
 453  */
 454 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 455 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 456 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 457
 458 /* slave core release by master*/
 459 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 460 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 461
 462 /*
 463  * SRIO_PCIE_BOOT - SLAVE
 464  */
 465 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 466 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 467 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 468                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 469 #endif
 470
 471 /*
 472  * eSPI - Enhanced SPI
 473  */
 474 #ifdef CONFIG_SPI_FLASH
 475 #define CONFIG_SPI_FLASH_BAR
 476 #define CONFIG_SF_DEFAULT_SPEED  10000000
 477 #define CONFIG_SF_DEFAULT_MODE    0
 478 #endif
 479
 480 /*
 481  * General PCI
 482  * Memory space is mapped 1-1, but I/O space must start from 0.
 483  */
 484 #define CONFIG_PCIE1            /* PCIE controller 1 */
 485 #define CONFIG_PCIE2            /* PCIE controller 2 */
 486 #define CONFIG_PCIE3            /* PCIE controller 3 */
 487 #define CONFIG_PCIE4            /* PCIE controller 4 */
 488 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 489 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 490 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 491 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 492 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 493 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 494 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 495 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 496 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 497 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 498 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 499
 500 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 501 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 502 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 503 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 504 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000 /* 256M */
 505 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 506 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 507 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 508 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 509
 510 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 511 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 512 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 513 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 514 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 515 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 516 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 517 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 518 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 519
 520 /* controller 4, Base address 203000 */
 521 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 522 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 523 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 524 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 525 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 526 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 527 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 528
 529 #ifdef CONFIG_PCI
 530 #define CONFIG_PCI_INDIRECT_BRIDGE
 531 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata LSZ ADD */
 532 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 533 #define CONFIG_DOS_PARTITION
 534 #endif
 535
 536 /* Qman/Bman */
 537 #ifndef CONFIG_NOBQFMAN
 538 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 539 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 540 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 541 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 542 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 543 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 544 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 545 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 546 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 547 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 548                                         CONFIG_SYS_BMAN_CENA_SIZE)
 549 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 550 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 551 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 552 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 553 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 554 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 555 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 556 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 557 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 558 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 559 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 560                                         CONFIG_SYS_QMAN_CENA_SIZE)
 561 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 562 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 563
 564 #define CONFIG_SYS_DPAA_FMAN
 565 #define CONFIG_SYS_DPAA_PME
 566 #define CONFIG_SYS_PMAN
 567 #define CONFIG_SYS_DPAA_DCE
 568 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 569 #define CONFIG_SYS_INTERLAKEN
 570
 571 /* Default address of microcode for the Linux Fman driver */
 572 #if defined(CONFIG_SPIFLASH)
 573 /*
 574  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 575  * env, so we got 0x110000.
 576  */
 577 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 578 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
 579 #define CONFIG_SYS_FMAN_FW_ADDR         0x110000
 580 #define CONFIG_CORTINA_FW_ADDR          0x120000
 581
 582 #elif defined(CONFIG_SDCARD)
 583 /*
 584  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 585  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 586  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 587  */
 588 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 589 #define CONFIG_SYS_CORTINA_FW_IN_MMC
 590 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 591 #define CONFIG_CORTINA_FW_ADDR          (512 * 0x8a0)
 592
 593 #elif defined(CONFIG_NAND)
 594 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 595 #define CONFIG_SYS_CORTINA_FW_IN_NAND
 596 #define CONFIG_SYS_FMAN_FW_ADDR         (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 597 #define CONFIG_CORTINA_FW_ADDR          (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
 598 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 599 /*
 600  * Slave has no ucode locally, it can fetch this from remote. When implementing
 601  * in two corenet boards, slave's ucode could be stored in master's memory
 602  * space, the address can be mapped from slave TLB->slave LAW->
 603  * slave SRIO or PCIE outbound window->master inbound window->
 604  * master LAW->the ucode address in master's memory space.
 605  */
 606 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 607 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE
 608 #define CONFIG_SYS_FMAN_FW_ADDR         0xFFE00000
 609 #define CONFIG_CORTINA_FW_ADDR          0xFFE10000
 610 #else
 611 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 612 #define CONFIG_SYS_CORTINA_FW_IN_NOR
 613 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 614 #define CONFIG_CORTINA_FW_ADDR          0xEFE00000
 615 #endif
 616 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 617 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 618 #endif /* CONFIG_NOBQFMAN */
 619
 620 #ifdef CONFIG_SYS_DPAA_FMAN
 621 #define CONFIG_FMAN_ENET
 622 #define CONFIG_PHYLIB_10G
 623 #define CONFIG_PHY_AQUANTIA
 624 #define CONFIG_PHY_CORTINA
 625 #define CONFIG_PHY_REALTEK
 626 #define CONFIG_CORTINA_FW_LENGTH        0x40000
 627 #define RGMII_PHY1_ADDR         0x01  /* RealTek RTL8211E */
 628 #define RGMII_PHY2_ADDR         0x02
 629 #define CORTINA_PHY_ADDR1       0x0c  /* Cortina CS4315 */
 630 #define CORTINA_PHY_ADDR2       0x0d
 631 #define FM1_10GEC3_PHY_ADDR     0x00  /* Aquantia AQ1202 10G Base-T */
 632 #define FM1_10GEC4_PHY_ADDR     0x01
 633 #endif
 634
 635 #ifdef CONFIG_FMAN_ENET
 636 #define CONFIG_MII              /* MII PHY management */
 637 #define CONFIG_ETHPRIME         "FM1@DTSEC3"
 638 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 639 #endif
 640
 641 /*
 642  * SATA
 643  */
 644 #ifdef CONFIG_FSL_SATA_V2
 645 #define CONFIG_LIBATA
 646 #define CONFIG_FSL_SATA
 647 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 648 #define CONFIG_SATA1
 649 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 650 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 651 #define CONFIG_SATA2
 652 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 653 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 654 #define CONFIG_LBA48
 655 #define CONFIG_CMD_SATA
 656 #define CONFIG_DOS_PARTITION
 657 #endif
 658
 659 /*
 660  * USB
 661  */
 662 #ifdef CONFIG_USB_EHCI
 663 #define CONFIG_USB_EHCI_FSL
 664 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 665 #define CONFIG_HAS_FSL_DR_USB
 666 #endif
 667
 668 /*
 669  * SDHC
 670  */
 671 #ifdef CONFIG_MMC
 672 #define CONFIG_FSL_ESDHC
 673 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 674 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 675 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 676 #define CONFIG_GENERIC_MMC
 677 #define CONFIG_DOS_PARTITION
 678 #endif
 679
 680 /*
 681  * Dynamic MTD Partition support with mtdparts
 682  */
 683 #ifndef CONFIG_SYS_NO_FLASH
 684 #define CONFIG_MTD_DEVICE
 685 #define CONFIG_MTD_PARTITIONS
 686 #define CONFIG_CMD_MTDPARTS
 687 #define CONFIG_FLASH_CFI_MTD
 688 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
 689                         "spi0=spife110000.1"
 690 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
 691                         "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
 692                         "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \
 693                         "1m(uboot),5m(kernel),128k(dtb),-(user)"
 694 #endif
 695
 696 /*
 697  * Environment
 698  */
 699
 700 /*
 701  * Command line configuration.
 702  */
 703 #define CONFIG_CMD_ERRATA
 704 #define CONFIG_CMD_REGINFO
 705
 706 #ifdef CONFIG_PCI
 707 #define CONFIG_CMD_PCI
 708 #endif
 709
 710 /* Hash command with SHA acceleration supported in hardware */
 711 #ifdef CONFIG_FSL_CAAM
 712 #define CONFIG_CMD_HASH
 713 #define CONFIG_SHA_HW_ACCEL
 714 #endif
 715
 716 /*
 717  * Miscellaneous configurable options
 718  */
 719 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 720 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 721 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support */
 722 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
 723 #ifdef CONFIG_CMD_KGDB
 724 #define CONFIG_SYS_CBSIZE       1024      /* Console I/O Buffer Size */
 725 #else
 726 #define CONFIG_SYS_CBSIZE       256       /* Console I/O Buffer Size */
 727 #endif
 728 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 729 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 730 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 731
 732 /*
 733  * For booting Linux, the board info and command line data
 734  * have to be in the first 64 MB of memory, since this is
 735  * the maximum mapped by the Linux kernel during initialization.
 736  */
 737 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 738 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 739
 740 #ifdef CONFIG_CMD_KGDB
 741 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 742 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 743 #endif
 744
 745 /*
 746  * Environment Configuration
 747  */
 748 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 749 #define CONFIG_BOOTFILE  "uImage"
 750 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 751
 752 /* default location for tftp and bootm */
 753 #define CONFIG_LOADADDR         1000000
 754 #define CONFIG_BAUDRATE         115200
 755 #define __USB_PHY_TYPE          utmi
 756
 757 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 758         "hwconfig=fsl_ddr:"                                     \
 759         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 760         "bank_intlv=auto;"                                      \
 761         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 762         "netdev=eth0\0"                                         \
 763         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 764         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 765         "tftpflash=tftpboot $loadaddr $uboot && "               \
 766         "protect off $ubootaddr +$filesize && "                 \
 767         "erase $ubootaddr +$filesize && "                       \
 768         "cp.b $loadaddr $ubootaddr $filesize && "               \
 769         "protect on $ubootaddr +$filesize && "                  \
 770         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 771         "consoledev=ttyS0\0"                                    \
 772         "ramdiskaddr=2000000\0"                                 \
 773         "ramdiskfile=t2080rdb/ramdisk.uboot\0"                  \
 774         "fdtaddr=1e00000\0"                                     \
 775         "fdtfile=t2080rdb/t2080rdb.dtb\0"                       \
 776         "bdev=sda3\0"
 777
 778 /*
 779  * For emulation this causes u-boot to jump to the start of the
 780  * proof point app code automatically
 781  */
 782 #define CONFIG_PROOF_POINTS                             \
 783         "setenv bootargs root=/dev/$bdev rw "           \
 784         "console=$consoledev,$baudrate $othbootargs;"   \
 785         "cpu 1 release 0x29000000 - - -;"               \
 786         "cpu 2 release 0x29000000 - - -;"               \
 787         "cpu 3 release 0x29000000 - - -;"               \
 788         "cpu 4 release 0x29000000 - - -;"               \
 789         "cpu 5 release 0x29000000 - - -;"               \
 790         "cpu 6 release 0x29000000 - - -;"               \
 791         "cpu 7 release 0x29000000 - - -;"               \
 792         "go 0x29000000"
 793
 794 #define CONFIG_HVBOOT                           \
 795         "setenv bootargs config-addr=0x60000000; "      \
 796         "bootm 0x01000000 - 0x00f00000"
 797
 798 #define CONFIG_ALU                              \
 799         "setenv bootargs root=/dev/$bdev rw "           \
 800         "console=$consoledev,$baudrate $othbootargs;"   \
 801         "cpu 1 release 0x01000000 - - -;"               \
 802         "cpu 2 release 0x01000000 - - -;"               \
 803         "cpu 3 release 0x01000000 - - -;"               \
 804         "cpu 4 release 0x01000000 - - -;"               \
 805         "cpu 5 release 0x01000000 - - -;"               \
 806         "cpu 6 release 0x01000000 - - -;"               \
 807         "cpu 7 release 0x01000000 - - -;"               \
 808         "go 0x01000000"
 809
 810 #define CONFIG_LINUX                            \
 811         "setenv bootargs root=/dev/ram rw "             \
 812         "console=$consoledev,$baudrate $othbootargs;"   \
 813         "setenv ramdiskaddr 0x02000000;"                \
 814         "setenv fdtaddr 0x00c00000;"                    \
 815         "setenv loadaddr 0x1000000;"                    \
 816         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 817
 818 #define CONFIG_HDBOOT                                   \
 819         "setenv bootargs root=/dev/$bdev rw "           \
 820         "console=$consoledev,$baudrate $othbootargs;"   \
 821         "tftp $loadaddr $bootfile;"                     \
 822         "tftp $fdtaddr $fdtfile;"                       \
 823         "bootm $loadaddr - $fdtaddr"
 824
 825 #define CONFIG_NFSBOOTCOMMAND                   \
 826         "setenv bootargs root=/dev/nfs rw "     \
 827         "nfsroot=$serverip:$rootpath "          \
 828         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 829         "console=$consoledev,$baudrate $othbootargs;"   \
 830         "tftp $loadaddr $bootfile;"             \
 831         "tftp $fdtaddr $fdtfile;"               \
 832         "bootm $loadaddr - $fdtaddr"
 833
 834 #define CONFIG_RAMBOOTCOMMAND                           \
 835         "setenv bootargs root=/dev/ram rw "             \
 836         "console=$consoledev,$baudrate $othbootargs;"   \
 837         "tftp $ramdiskaddr $ramdiskfile;"               \
 838         "tftp $loadaddr $bootfile;"                     \
 839         "tftp $fdtaddr $fdtfile;"                       \
 840         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 841
 842 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 843
 844 #include <asm/fsl_secure_boot.h>
 845
 846 #endif  /* __T2080RDB_H */