include/configs/T208xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 /*
   7  * T2080 RDB/PCIe board configuration file
   8  */
   9
  10 #ifndef __T2080RDB_H
  11 #define __T2080RDB_H
  12
  13 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  14 #define CONFIG_FSL_SATA_V2
  15
  16 /* High Level Configuration Options */
  17 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
  18 #define CONFIG_ENABLE_36BIT_PHYS
  19
  20 #ifdef CONFIG_PHYS_64BIT
  21 #define CONFIG_ADDR_MAP 1
  22 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  23 #endif
  24
  25 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  26 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  27 #define CONFIG_ENV_OVERWRITE
  28
  29 #ifdef CONFIG_RAMBOOT_PBL
  30 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
  31
  32 #define CONFIG_SPL_FLUSH_IMAGE
  33 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  34 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  35 #define CONFIG_SPL_PAD_TO               0x40000
  36 #define CONFIG_SPL_MAX_SIZE             0x28000
  37 #define RESET_VECTOR_OFFSET             0x27FFC
  38 #define BOOT_PAGE_OFFSET                0x27000
  39 #ifdef CONFIG_SPL_BUILD
  40 #define CONFIG_SPL_SKIP_RELOCATE
  41 #define CONFIG_SPL_COMMON_INIT_DDR
  42 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  43 #endif
  44
  45 #ifdef CONFIG_NAND
  46 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  47 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  48 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  49 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  50 #define CONFIG_SYS_LDSCRIPT  "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  51 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg
  52 #define CONFIG_SPL_NAND_BOOT
  53 #endif
  54
  55 #ifdef CONFIG_SPIFLASH
  56 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  57 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  58 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
  59 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
  60 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
  61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
  62 #define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  63 #ifndef CONFIG_SPL_BUILD
  64 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  65 #endif
  66 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg
  67 #define CONFIG_SPL_SPI_BOOT
  68 #endif
  69
  70 #ifdef CONFIG_SDCARD
  71 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  72 #define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
  73 #define CONFIG_SYS_MMC_U_BOOT_DST      (0x00200000)
  74 #define CONFIG_SYS_MMC_U_BOOT_START    (0x00200000)
  75 #define CONFIG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
  76 #define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  77 #ifndef CONFIG_SPL_BUILD
  78 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  79 #endif
  80 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg
  81 #define CONFIG_SPL_MMC_BOOT
  82 #endif
  83
  84 #endif /* CONFIG_RAMBOOT_PBL */
  85
  86 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  87 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  88 /* Set 1M boot space */
  89 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  90 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  91                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  92 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  93 #endif
  94
  95 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  96 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  97 #endif
  98
  99 /*
 100  * These can be toggled for performance analysis, otherwise use default.
 101  */
 102 #define CONFIG_SYS_CACHE_STASHING
 103 #define CONFIG_BTB              /* toggle branch predition */
 104 #define CONFIG_DDR_ECC
 105 #ifdef CONFIG_DDR_ECC
 106 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 107 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 108 #endif
 109
 110 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
 111 #define CONFIG_SYS_MEMTEST_END          0x00400000
 112
 113 #ifdef CONFIG_MTD_NOR_FLASH
 114 #define CONFIG_FLASH_CFI_DRIVER
 115 #define CONFIG_SYS_FLASH_CFI
 116 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 117 #endif
 118
 119 #if defined(CONFIG_SPIFLASH)
 120 #define CONFIG_SYS_EXTRA_ENV_RELOC
 121 #define CONFIG_ENV_SPI_BUS      0
 122 #define CONFIG_ENV_SPI_CS       0
 123 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 124 #define CONFIG_ENV_SPI_MODE     0
 125 #define CONFIG_ENV_SIZE         0x2000     /* 8KB */
 126 #define CONFIG_ENV_OFFSET       0x100000   /* 1MB */
 127 #define CONFIG_ENV_SECT_SIZE    0x10000
 128 #elif defined(CONFIG_SDCARD)
 129 #define CONFIG_SYS_EXTRA_ENV_RELOC
 130 #define CONFIG_SYS_MMC_ENV_DEV  0
 131 #define CONFIG_ENV_SIZE         0x2000
 132 #define CONFIG_ENV_OFFSET       (512 * 0x800)
 133 #elif defined(CONFIG_NAND)
 134 #define CONFIG_SYS_EXTRA_ENV_RELOC
 135 #define CONFIG_ENV_SIZE         0x2000
 136 #define CONFIG_ENV_OFFSET       (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
 137 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 138 #define CONFIG_ENV_ADDR         0xffe20000
 139 #define CONFIG_ENV_SIZE         0x2000
 140 #elif defined(CONFIG_ENV_IS_NOWHERE)
 141 #define CONFIG_ENV_SIZE         0x2000
 142 #else
 143 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 144 #define CONFIG_ENV_SIZE         0x2000
 145 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 146 #endif
 147
 148 #ifndef __ASSEMBLY__
 149 unsigned long get_board_sys_clk(void);
 150 unsigned long get_board_ddr_clk(void);
 151 #endif
 152
 153 #define CONFIG_SYS_CLK_FREQ     66660000
 154 #define CONFIG_DDR_CLK_FREQ     133330000
 155
 156 /*
 157  * Config the L3 Cache as L3 SRAM
 158  */
 159 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 160 #define CONFIG_SYS_L3_SIZE              (512 << 10)
 161 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 162 #ifdef CONFIG_RAMBOOT_PBL
 163 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 164 #endif
 165 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 166 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
 167 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 168
 169 #define CONFIG_SYS_DCSRBAR      0xf0000000
 170 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
 171
 172 /* EEPROM */
 173 #define CONFIG_ID_EEPROM
 174 #define CONFIG_SYS_I2C_EEPROM_NXID
 175 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 176 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 177 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 178
 179 /*
 180  * DDR Setup
 181  */
 182 #define CONFIG_VERY_BIG_RAM
 183 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 184 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 185 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 186 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 187 #define CONFIG_DDR_SPD
 188 #undef CONFIG_FSL_DDR_INTERACTIVE
 189 #define CONFIG_SYS_SPD_BUS_NUM  0
 190 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 191 #define SPD_EEPROM_ADDRESS1     0x51
 192 #define SPD_EEPROM_ADDRESS2     0x52
 193 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 194 #define CTRL_INTLV_PREFERED     cacheline
 195
 196 /*
 197  * IFC Definitions
 198  */
 199 #define CONFIG_SYS_FLASH_BASE           0xe8000000
 200 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 201 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 202 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 203                                 CSPR_PORT_SIZE_16 | \
 204                                 CSPR_MSEL_NOR | \
 205                                 CSPR_V)
 206 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 207
 208 /* NOR Flash Timing Params */
 209 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 210
 211 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 212                                 FTIM0_NOR_TEADC(0x5) | \
 213                                 FTIM0_NOR_TEAHC(0x5))
 214 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 215                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 216                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 217 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 218                                 FTIM2_NOR_TCH(0x4) | \
 219                                 FTIM2_NOR_TWPH(0x0E) | \
 220                                 FTIM2_NOR_TWP(0x1c))
 221 #define CONFIG_SYS_NOR_FTIM3    0x0
 222
 223 #define CONFIG_SYS_FLASH_QUIET_TEST
 224 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 225
 226 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 227 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 228 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 229 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 230 #define CONFIG_SYS_FLASH_EMPTY_INFO
 231 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS }
 232
 233 /* CPLD on IFC */
 234 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 235 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 236 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 237 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 238                                 | CSPR_PORT_SIZE_8 \
 239                                 | CSPR_MSEL_GPCM \
 240                                 | CSPR_V)
 241 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 242 #define CONFIG_SYS_CSOR2        0x0
 243
 244 /* CPLD Timing parameters for IFC CS2 */
 245 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 246                                         FTIM0_GPCM_TEADC(0x0e) | \
 247                                         FTIM0_GPCM_TEAHC(0x0e))
 248 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 249                                         FTIM1_GPCM_TRAD(0x1f))
 250 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 251                                         FTIM2_GPCM_TCH(0x8) | \
 252                                         FTIM2_GPCM_TWP(0x1f))
 253 #define CONFIG_SYS_CS2_FTIM3            0x0
 254
 255 /* NAND Flash on IFC */
 256 #define CONFIG_NAND_FSL_IFC
 257 #define CONFIG_SYS_NAND_BASE            0xff800000
 258 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 259
 260 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 261 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 262                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 263                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 264                                 | CSPR_V)
 265 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 266
 267 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 268                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 269                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 270                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 271                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 272                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 273                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 274
 275 #define CONFIG_SYS_NAND_ONFI_DETECTION
 276
 277 /* ONFI NAND Flash mode0 Timing Params */
 278 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 279                                         FTIM0_NAND_TWP(0x18)    | \
 280                                         FTIM0_NAND_TWCHT(0x07)  | \
 281                                         FTIM0_NAND_TWH(0x0a))
 282 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 283                                         FTIM1_NAND_TWBE(0x39)   | \
 284                                         FTIM1_NAND_TRR(0x0e)    | \
 285                                         FTIM1_NAND_TRP(0x18))
 286 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 287                                         FTIM2_NAND_TREH(0x0a)   | \
 288                                         FTIM2_NAND_TWHRE(0x1e))
 289 #define CONFIG_SYS_NAND_FTIM3           0x0
 290
 291 #define CONFIG_SYS_NAND_DDR_LAW         11
 292 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 293 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 294 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 295
 296 #if defined(CONFIG_NAND)
 297 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 298 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 299 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 300 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 301 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 302 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 303 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 304 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 305 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 306 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 307 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 308 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 309 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 310 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 311 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 312 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 313 #else
 314 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 315 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 316 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 317 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 318 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 319 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 320 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 321 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 322 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 323 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 324 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 325 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 326 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 327 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 328 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 329 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 330 #endif
 331
 332 #if defined(CONFIG_RAMBOOT_PBL)
 333 #define CONFIG_SYS_RAMBOOT
 334 #endif
 335
 336 #ifdef CONFIG_SPL_BUILD
 337 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SPL_TEXT_BASE
 338 #else
 339 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SYS_TEXT_BASE /* start of monitor */
 340 #endif
 341
 342 #define CONFIG_MISC_INIT_R
 343 #define CONFIG_HWCONFIG
 344
 345 /* define to use L1 as initial stack */
 346 #define CONFIG_L1_INIT_RAM
 347 #define CONFIG_SYS_INIT_RAM_LOCK
 348 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 349 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 350 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 351 /* The assembler doesn't like typecast */
 352 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 353                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 354                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 355 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 356 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 357                                                 GENERATED_GBL_DATA_SIZE)
 358 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 359 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 360 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 361
 362 /*
 363  * Serial Port
 364  */
 365 #define CONFIG_SYS_NS16550_SERIAL
 366 #define CONFIG_SYS_NS16550_REG_SIZE     1
 367 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 368 #define CONFIG_SYS_BAUDRATE_TABLE       \
 369         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 370 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 371 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 372 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 373 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 374
 375 /*
 376  * I2C
 377  */
 378 #define CONFIG_SYS_I2C
 379 #define CONFIG_SYS_I2C_FSL
 380 #define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
 381 #define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
 382 #define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
 383 #define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
 384 #define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
 385 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
 386 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
 387 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
 388 #define CONFIG_SYS_FSL_I2C_SPEED   100000
 389 #define CONFIG_SYS_FSL_I2C2_SPEED  100000
 390 #define CONFIG_SYS_FSL_I2C3_SPEED  100000
 391 #define CONFIG_SYS_FSL_I2C4_SPEED  100000
 392 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 393 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 394 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 395 #define I2C_MUX_CH_DEFAULT      0x8
 396
 397 #define I2C_MUX_CH_VOL_MONITOR  0xa
 398
 399 #define CONFIG_VID_FLS_ENV              "t208xrdb_vdd_mv"
 400 #ifndef CONFIG_SPL_BUILD
 401 #define CONFIG_VID
 402 #endif
 403 #define CONFIG_VOL_MONITOR_IR36021_SET
 404 #define CONFIG_VOL_MONITOR_IR36021_READ
 405 /* The lowest and highest voltage allowed for T208xRDB */
 406 #define VDD_MV_MIN                      819
 407 #define VDD_MV_MAX                      1212
 408
 409 /*
 410  * RapidIO
 411  */
 412 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 413 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 414 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 415 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 416 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 417 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 418 /*
 419  * for slave u-boot IMAGE instored in master memory space,
 420  * PHYS must be aligned based on the SIZE
 421  */
 422 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 423 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 424 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 425 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 426 /*
 427  * for slave UCODE and ENV instored in master memory space,
 428  * PHYS must be aligned based on the SIZE
 429  */
 430 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 431 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 432 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 433
 434 /* slave core release by master*/
 435 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 436 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 437
 438 /*
 439  * SRIO_PCIE_BOOT - SLAVE
 440  */
 441 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 442 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 443 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 444                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 445 #endif
 446
 447 /*
 448  * eSPI - Enhanced SPI
 449  */
 450 #ifdef CONFIG_SPI_FLASH
 451 #define CONFIG_SPI_FLASH_BAR
 452 #define CONFIG_SF_DEFAULT_SPEED  10000000
 453 #define CONFIG_SF_DEFAULT_MODE    0
 454 #endif
 455
 456 /*
 457  * General PCI
 458  * Memory space is mapped 1-1, but I/O space must start from 0.
 459  */
 460 #define CONFIG_PCIE1            /* PCIE controller 1 */
 461 #define CONFIG_PCIE2            /* PCIE controller 2 */
 462 #define CONFIG_PCIE3            /* PCIE controller 3 */
 463 #define CONFIG_PCIE4            /* PCIE controller 4 */
 464 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 465 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 466 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 467 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 468 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 469 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 470 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 471 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 472 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 473 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 474 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 475
 476 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 477 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 478 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 479 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 480 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000 /* 256M */
 481 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 482 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 483 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 484 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 485
 486 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 487 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 488 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 489 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 490 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 491 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 492 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 493 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 494 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 495
 496 /* controller 4, Base address 203000 */
 497 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 498 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 499 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 500 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 501 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 502 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 503 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 504
 505 #ifdef CONFIG_PCI
 506 #define CONFIG_PCI_INDIRECT_BRIDGE
 507 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata LSZ ADD */
 508 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 509 #endif
 510
 511 /* Qman/Bman */
 512 #ifndef CONFIG_NOBQFMAN
 513 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 514 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 515 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 516 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 517 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 518 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 519 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 520 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 521 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 522                                         CONFIG_SYS_BMAN_CENA_SIZE)
 523 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 524 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 525 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 526 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 527 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 528 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 529 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 530 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 531 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 532 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 533 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 534                                         CONFIG_SYS_QMAN_CENA_SIZE)
 535 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 536 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 537
 538 #define CONFIG_SYS_DPAA_FMAN
 539 #define CONFIG_SYS_DPAA_PME
 540 #define CONFIG_SYS_PMAN
 541 #define CONFIG_SYS_DPAA_DCE
 542 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 543 #define CONFIG_SYS_INTERLAKEN
 544
 545 /* Default address of microcode for the Linux Fman driver */
 546 #if defined(CONFIG_SPIFLASH)
 547 /*
 548  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 549  * env, so we got 0x110000.
 550  */
 551 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 552 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
 553 #define CONFIG_SYS_FMAN_FW_ADDR         0x110000
 554 #define CONFIG_CORTINA_FW_ADDR          0x120000
 555
 556 #elif defined(CONFIG_SDCARD)
 557 /*
 558  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 559  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 560  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 561  */
 562 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 563 #define CONFIG_SYS_CORTINA_FW_IN_MMC
 564 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 565 #define CONFIG_CORTINA_FW_ADDR          (512 * 0x8a0)
 566
 567 #elif defined(CONFIG_NAND)
 568 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 569 #define CONFIG_SYS_CORTINA_FW_IN_NAND
 570 #define CONFIG_SYS_FMAN_FW_ADDR         (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 571 #define CONFIG_CORTINA_FW_ADDR          (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
 572 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 573 /*
 574  * Slave has no ucode locally, it can fetch this from remote. When implementing
 575  * in two corenet boards, slave's ucode could be stored in master's memory
 576  * space, the address can be mapped from slave TLB->slave LAW->
 577  * slave SRIO or PCIE outbound window->master inbound window->
 578  * master LAW->the ucode address in master's memory space.
 579  */
 580 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 581 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE
 582 #define CONFIG_SYS_FMAN_FW_ADDR         0xFFE00000
 583 #define CONFIG_CORTINA_FW_ADDR          0xFFE10000
 584 #else
 585 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 586 #define CONFIG_SYS_CORTINA_FW_IN_NOR
 587 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 588 #define CONFIG_CORTINA_FW_ADDR          0xEFE00000
 589 #endif
 590 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 591 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 592 #endif /* CONFIG_NOBQFMAN */
 593
 594 #ifdef CONFIG_SYS_DPAA_FMAN
 595 #define CONFIG_FMAN_ENET
 596 #define CONFIG_PHYLIB_10G
 597 #define CONFIG_PHY_AQUANTIA
 598 #define CONFIG_PHY_CORTINA
 599 #define CONFIG_PHY_REALTEK
 600 #define CONFIG_CORTINA_FW_LENGTH        0x40000
 601 #define RGMII_PHY1_ADDR         0x01  /* RealTek RTL8211E */
 602 #define RGMII_PHY2_ADDR         0x02
 603 #define CORTINA_PHY_ADDR1       0x0c  /* Cortina CS4315 */
 604 #define CORTINA_PHY_ADDR2       0x0d
 605 #define FM1_10GEC3_PHY_ADDR     0x00  /* Aquantia AQ1202 10G Base-T */
 606 #define FM1_10GEC4_PHY_ADDR     0x01
 607 #endif
 608
 609 #ifdef CONFIG_FMAN_ENET
 610 #define CONFIG_MII              /* MII PHY management */
 611 #define CONFIG_ETHPRIME         "FM1@DTSEC3"
 612 #endif
 613
 614 /*
 615  * SATA
 616  */
 617 #ifdef CONFIG_FSL_SATA_V2
 618 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 619 #define CONFIG_SATA1
 620 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 621 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 622 #define CONFIG_SATA2
 623 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 624 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 625 #define CONFIG_LBA48
 626 #endif
 627
 628 /*
 629  * USB
 630  */
 631 #ifdef CONFIG_USB_EHCI_HCD
 632 #define CONFIG_USB_EHCI_FSL
 633 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 634 #define CONFIG_HAS_FSL_DR_USB
 635 #endif
 636
 637 /*
 638  * SDHC
 639  */
 640 #ifdef CONFIG_MMC
 641 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 642 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 643 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 644 #endif
 645
 646 /*
 647  * Dynamic MTD Partition support with mtdparts
 648  */
 649 #ifdef CONFIG_MTD_NOR_FLASH
 650 #define CONFIG_FLASH_CFI_MTD
 651 #endif
 652
 653 /*
 654  * Environment
 655  */
 656
 657 /*
 658  * Miscellaneous configurable options
 659  */
 660 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
 661
 662 /*
 663  * For booting Linux, the board info and command line data
 664  * have to be in the first 64 MB of memory, since this is
 665  * the maximum mapped by the Linux kernel during initialization.
 666  */
 667 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 668 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 669
 670 #ifdef CONFIG_CMD_KGDB
 671 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 672 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 673 #endif
 674
 675 /*
 676  * Environment Configuration
 677  */
 678 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 679 #define CONFIG_BOOTFILE  "uImage"
 680 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 681
 682 /* default location for tftp and bootm */
 683 #define CONFIG_LOADADDR         1000000
 684 #define __USB_PHY_TYPE          utmi
 685
 686 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 687         "hwconfig=fsl_ddr:"                                     \
 688         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 689         "bank_intlv=auto;"                                      \
 690         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 691         "netdev=eth0\0"                                         \
 692         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 693         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 694         "tftpflash=tftpboot $loadaddr $uboot && "               \
 695         "protect off $ubootaddr +$filesize && "                 \
 696         "erase $ubootaddr +$filesize && "                       \
 697         "cp.b $loadaddr $ubootaddr $filesize && "               \
 698         "protect on $ubootaddr +$filesize && "                  \
 699         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 700         "consoledev=ttyS0\0"                                    \
 701         "ramdiskaddr=2000000\0"                                 \
 702         "ramdiskfile=t2080rdb/ramdisk.uboot\0"                  \
 703         "fdtaddr=1e00000\0"                                     \
 704         "fdtfile=t2080rdb/t2080rdb.dtb\0"                       \
 705         "bdev=sda3\0"
 706
 707 /*
 708  * For emulation this causes u-boot to jump to the start of the
 709  * proof point app code automatically
 710  */
 711 #define CONFIG_PROOF_POINTS                             \
 712         "setenv bootargs root=/dev/$bdev rw "           \
 713         "console=$consoledev,$baudrate $othbootargs;"   \
 714         "cpu 1 release 0x29000000 - - -;"               \
 715         "cpu 2 release 0x29000000 - - -;"               \
 716         "cpu 3 release 0x29000000 - - -;"               \
 717         "cpu 4 release 0x29000000 - - -;"               \
 718         "cpu 5 release 0x29000000 - - -;"               \
 719         "cpu 6 release 0x29000000 - - -;"               \
 720         "cpu 7 release 0x29000000 - - -;"               \
 721         "go 0x29000000"
 722
 723 #define CONFIG_HVBOOT                           \
 724         "setenv bootargs config-addr=0x60000000; "      \
 725         "bootm 0x01000000 - 0x00f00000"
 726
 727 #define CONFIG_ALU                              \
 728         "setenv bootargs root=/dev/$bdev rw "           \
 729         "console=$consoledev,$baudrate $othbootargs;"   \
 730         "cpu 1 release 0x01000000 - - -;"               \
 731         "cpu 2 release 0x01000000 - - -;"               \
 732         "cpu 3 release 0x01000000 - - -;"               \
 733         "cpu 4 release 0x01000000 - - -;"               \
 734         "cpu 5 release 0x01000000 - - -;"               \
 735         "cpu 6 release 0x01000000 - - -;"               \
 736         "cpu 7 release 0x01000000 - - -;"               \
 737         "go 0x01000000"
 738
 739 #define CONFIG_LINUX                            \
 740         "setenv bootargs root=/dev/ram rw "             \
 741         "console=$consoledev,$baudrate $othbootargs;"   \
 742         "setenv ramdiskaddr 0x02000000;"                \
 743         "setenv fdtaddr 0x00c00000;"                    \
 744         "setenv loadaddr 0x1000000;"                    \
 745         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 746
 747 #define CONFIG_HDBOOT                                   \
 748         "setenv bootargs root=/dev/$bdev rw "           \
 749         "console=$consoledev,$baudrate $othbootargs;"   \
 750         "tftp $loadaddr $bootfile;"                     \
 751         "tftp $fdtaddr $fdtfile;"                       \
 752         "bootm $loadaddr - $fdtaddr"
 753
 754 #define CONFIG_NFSBOOTCOMMAND                   \
 755         "setenv bootargs root=/dev/nfs rw "     \
 756         "nfsroot=$serverip:$rootpath "          \
 757         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 758         "console=$consoledev,$baudrate $othbootargs;"   \
 759         "tftp $loadaddr $bootfile;"             \
 760         "tftp $fdtaddr $fdtfile;"               \
 761         "bootm $loadaddr - $fdtaddr"
 762
 763 #define CONFIG_RAMBOOTCOMMAND                           \
 764         "setenv bootargs root=/dev/ram rw "             \
 765         "console=$consoledev,$baudrate $othbootargs;"   \
 766         "tftp $ramdiskaddr $ramdiskfile;"               \
 767         "tftp $loadaddr $bootfile;"                     \
 768         "tftp $fdtaddr $fdtfile;"                       \
 769         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 770
 771 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 772
 773 #include <asm/fsl_secure_boot.h>
 774
 775 #endif  /* __T2080RDB_H */