1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
8 * T2080 RDB/PCIe board configuration file
14 #include <linux/stringify.h>
16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
17 #define CONFIG_FSL_SATA_V2
19 /* High Level Configuration Options */
20 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
21 #define CONFIG_ENABLE_36BIT_PHYS
23 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
24 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
26 #ifdef CONFIG_RAMBOOT_PBL
27 #define RESET_VECTOR_OFFSET 0x27FFC
28 #define BOOT_PAGE_OFFSET 0x27000
29 #define CONFIG_SPL_COMMON_INIT_DDR
31 #ifdef CONFIG_MTD_RAW_NAND
32 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
33 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
34 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
35 #ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
36 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
40 #ifdef CONFIG_SPIFLASH
41 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
42 #define CONFIG_SPL_SPI_FLASH_MINIMAL
43 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
44 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
45 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
46 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
47 #ifndef CONFIG_SPL_BUILD
48 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
53 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
54 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
55 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
56 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
57 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
58 #ifndef CONFIG_SPL_BUILD
59 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
63 #endif /* CONFIG_RAMBOOT_PBL */
65 #define CONFIG_SRIO_PCIE_BOOT_MASTER
66 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
67 /* Set 1M boot space */
68 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
69 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
70 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
71 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
74 #ifndef CONFIG_RESET_VECTOR_ADDRESS
75 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
79 * These can be toggled for performance analysis, otherwise use default.
81 #define CONFIG_SYS_CACHE_STASHING
83 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
87 * Config the L3 Cache as L3 SRAM
89 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
90 #define CONFIG_SYS_L3_SIZE (512 << 10)
91 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
92 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
93 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
94 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
95 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
97 #define CONFIG_SYS_DCSRBAR 0xf0000000
98 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
101 #define CONFIG_SYS_I2C_EEPROM_NXID
102 #define CONFIG_SYS_EEPROM_BUS_NUM 0
107 #define CONFIG_VERY_BIG_RAM
108 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
109 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
110 #define CONFIG_SYS_SPD_BUS_NUM 0
111 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
112 #define SPD_EEPROM_ADDRESS1 0x51
113 #define SPD_EEPROM_ADDRESS2 0x52
114 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
115 #define CTRL_INTLV_PREFERED cacheline
120 #define CONFIG_SYS_FLASH_BASE 0xe8000000
121 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
122 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
123 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
124 CSPR_PORT_SIZE_16 | \
127 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
129 /* NOR Flash Timing Params */
130 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
132 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
133 FTIM0_NOR_TEADC(0x5) | \
134 FTIM0_NOR_TEAHC(0x5))
135 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
136 FTIM1_NOR_TRAD_NOR(0x1A) |\
137 FTIM1_NOR_TSEQRAD_NOR(0x13))
138 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
139 FTIM2_NOR_TCH(0x4) | \
140 FTIM2_NOR_TWPH(0x0E) | \
142 #define CONFIG_SYS_NOR_FTIM3 0x0
144 #define CONFIG_SYS_FLASH_QUIET_TEST
145 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
147 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
148 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
149 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
150 #define CONFIG_SYS_FLASH_EMPTY_INFO
151 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS }
154 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
155 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
156 #define CONFIG_SYS_CSPR2_EXT (0xf)
157 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
161 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
162 #define CONFIG_SYS_CSOR2 0x0
164 /* CPLD Timing parameters for IFC CS2 */
165 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
166 FTIM0_GPCM_TEADC(0x0e) | \
167 FTIM0_GPCM_TEAHC(0x0e))
168 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
169 FTIM1_GPCM_TRAD(0x1f))
170 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
171 FTIM2_GPCM_TCH(0x8) | \
172 FTIM2_GPCM_TWP(0x1f))
173 #define CONFIG_SYS_CS2_FTIM3 0x0
175 /* NAND Flash on IFC */
176 #define CONFIG_SYS_NAND_BASE 0xff800000
177 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
179 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
180 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
181 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
182 | CSPR_MSEL_NAND /* MSEL = NAND */ \
184 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
186 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
187 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
188 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
189 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
190 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
191 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
192 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
194 /* ONFI NAND Flash mode0 Timing Params */
195 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
196 FTIM0_NAND_TWP(0x18) | \
197 FTIM0_NAND_TWCHT(0x07) | \
198 FTIM0_NAND_TWH(0x0a))
199 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
200 FTIM1_NAND_TWBE(0x39) | \
201 FTIM1_NAND_TRR(0x0e) | \
202 FTIM1_NAND_TRP(0x18))
203 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
204 FTIM2_NAND_TREH(0x0a) | \
205 FTIM2_NAND_TWHRE(0x1e))
206 #define CONFIG_SYS_NAND_FTIM3 0x0
208 #define CONFIG_SYS_NAND_DDR_LAW 11
209 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
210 #define CONFIG_SYS_MAX_NAND_DEVICE 1
212 #if defined(CONFIG_MTD_RAW_NAND)
213 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
214 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
215 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
216 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
217 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
218 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
219 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
220 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
221 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
222 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
223 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
224 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
225 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
226 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
227 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
228 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
230 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
231 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
232 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
233 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
234 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
235 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
236 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
237 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
238 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
239 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
240 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
241 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
242 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
243 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
244 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
245 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
248 #if defined(CONFIG_RAMBOOT_PBL)
249 #define CONFIG_SYS_RAMBOOT
252 #define CONFIG_HWCONFIG
254 /* define to use L1 as initial stack */
255 #define CONFIG_L1_INIT_RAM
256 #define CONFIG_SYS_INIT_RAM_LOCK
257 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
258 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
259 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
260 /* The assembler doesn't like typecast */
261 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
262 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
263 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
264 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
265 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
266 GENERATED_GBL_DATA_SIZE)
267 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
268 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
273 #define CONFIG_SYS_NS16550_SERIAL
274 #define CONFIG_SYS_NS16550_REG_SIZE 1
275 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
276 #define CONFIG_SYS_BAUDRATE_TABLE \
277 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
278 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
279 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
280 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
281 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
287 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
288 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
289 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
290 #define I2C_MUX_CH_DEFAULT 0x8
292 #define I2C_MUX_CH_VOL_MONITOR 0xa
294 /* The lowest and highest voltage allowed for T208xRDB */
295 #define VDD_MV_MIN 819
296 #define VDD_MV_MAX 1212
301 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
302 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
303 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
304 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
305 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
306 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
308 * for slave u-boot IMAGE instored in master memory space,
309 * PHYS must be aligned based on the SIZE
311 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
312 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
313 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
314 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
316 * for slave UCODE and ENV instored in master memory space,
317 * PHYS must be aligned based on the SIZE
319 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
320 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
321 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
323 /* slave core release by master*/
324 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
325 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
328 * SRIO_PCIE_BOOT - SLAVE
330 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
331 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
332 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
333 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
337 * eSPI - Enhanced SPI
342 * Memory space is mapped 1-1, but I/O space must start from 0.
344 #define CONFIG_PCIE1 /* PCIE controller 1 */
345 #define CONFIG_PCIE2 /* PCIE controller 2 */
346 #define CONFIG_PCIE3 /* PCIE controller 3 */
347 #define CONFIG_PCIE4 /* PCIE controller 4 */
348 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
349 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
350 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
351 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
352 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
354 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
355 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
356 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
357 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
358 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
360 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
361 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
362 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
363 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
364 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
366 /* controller 4, Base address 203000 */
367 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
368 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
369 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
372 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
376 #ifndef CONFIG_NOBQFMAN
377 #define CONFIG_SYS_BMAN_NUM_PORTALS 18
378 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
379 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
380 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
381 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
382 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
383 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
384 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
385 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
386 CONFIG_SYS_BMAN_CENA_SIZE)
387 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
388 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
389 #define CONFIG_SYS_QMAN_NUM_PORTALS 18
390 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
391 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
392 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
393 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
394 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
395 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
396 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
397 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
398 CONFIG_SYS_QMAN_CENA_SIZE)
399 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
400 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
402 #define CONFIG_SYS_DPAA_FMAN
403 #define CONFIG_SYS_DPAA_PME
404 #define CONFIG_SYS_PMAN
405 #define CONFIG_SYS_DPAA_DCE
406 #define CONFIG_SYS_DPAA_RMAN /* RMan */
407 #define CONFIG_SYS_INTERLAKEN
409 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
410 #endif /* CONFIG_NOBQFMAN */
412 #ifdef CONFIG_SYS_DPAA_FMAN
413 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
414 #define RGMII_PHY2_ADDR 0x02
415 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */
416 #define CORTINA_PHY_ADDR2 0x0d
417 /* Aquantia AQ1202 10G Base-T used by board revisions up to C */
418 #define FM1_10GEC3_PHY_ADDR 0x00
419 #define FM1_10GEC4_PHY_ADDR 0x01
420 /* Aquantia AQR113C 10G Base-T used by board revisions D and up */
421 #define AQR113C_PHY_ADDR1 0x00
422 #define AQR113C_PHY_ADDR2 0x08
428 #ifdef CONFIG_FSL_SATA_V2
430 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
431 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
433 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
434 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
441 #ifdef CONFIG_USB_EHCI_HCD
442 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
443 #define CONFIG_HAS_FSL_DR_USB
450 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
451 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
455 * Dynamic MTD Partition support with mtdparts
463 * Miscellaneous configurable options
467 * For booting Linux, the board info and command line data
468 * have to be in the first 64 MB of memory, since this is
469 * the maximum mapped by the Linux kernel during initialization.
471 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
472 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
475 * Environment Configuration
477 #define CONFIG_ROOTPATH "/opt/nfsroot"
478 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
480 #define __USB_PHY_TYPE utmi
482 #define CONFIG_EXTRA_ENV_SETTINGS \
483 "hwconfig=fsl_ddr:" \
484 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
486 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
488 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
489 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
490 "tftpflash=tftpboot $loadaddr $uboot && " \
491 "protect off $ubootaddr +$filesize && " \
492 "erase $ubootaddr +$filesize && " \
493 "cp.b $loadaddr $ubootaddr $filesize && " \
494 "protect on $ubootaddr +$filesize && " \
495 "cmp.b $loadaddr $ubootaddr $filesize\0" \
496 "consoledev=ttyS0\0" \
497 "ramdiskaddr=2000000\0" \
498 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \
499 "fdtaddr=1e00000\0" \
500 "fdtfile=t2080rdb/t2080rdb.dtb\0" \
504 * For emulation this causes u-boot to jump to the start of the
505 * proof point app code automatically
507 #define PROOF_POINTS \
508 "setenv bootargs root=/dev/$bdev rw " \
509 "console=$consoledev,$baudrate $othbootargs;" \
510 "cpu 1 release 0x29000000 - - -;" \
511 "cpu 2 release 0x29000000 - - -;" \
512 "cpu 3 release 0x29000000 - - -;" \
513 "cpu 4 release 0x29000000 - - -;" \
514 "cpu 5 release 0x29000000 - - -;" \
515 "cpu 6 release 0x29000000 - - -;" \
516 "cpu 7 release 0x29000000 - - -;" \
520 "setenv bootargs config-addr=0x60000000; " \
521 "bootm 0x01000000 - 0x00f00000"
524 "setenv bootargs root=/dev/$bdev rw " \
525 "console=$consoledev,$baudrate $othbootargs;" \
526 "cpu 1 release 0x01000000 - - -;" \
527 "cpu 2 release 0x01000000 - - -;" \
528 "cpu 3 release 0x01000000 - - -;" \
529 "cpu 4 release 0x01000000 - - -;" \
530 "cpu 5 release 0x01000000 - - -;" \
531 "cpu 6 release 0x01000000 - - -;" \
532 "cpu 7 release 0x01000000 - - -;" \
535 #include <asm/fsl_secure_boot.h>
537 #endif /* __T2080RDB_H */