1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
8 * T2080 RDB/PCIe board configuration file
14 #include <linux/stringify.h>
16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
17 #define CONFIG_FSL_SATA_V2
19 /* High Level Configuration Options */
20 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
21 #define CONFIG_ENABLE_36BIT_PHYS
23 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
24 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
26 #ifdef CONFIG_RAMBOOT_PBL
27 #define RESET_VECTOR_OFFSET 0x27FFC
28 #define BOOT_PAGE_OFFSET 0x27000
30 #ifdef CONFIG_MTD_RAW_NAND
31 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
32 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
33 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
34 #ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
35 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
39 #ifdef CONFIG_SPIFLASH
40 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
41 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
42 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
43 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
44 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
45 #ifndef CONFIG_SPL_BUILD
46 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
51 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
52 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
53 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
54 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
55 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
56 #ifndef CONFIG_SPL_BUILD
57 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
61 #endif /* CONFIG_RAMBOOT_PBL */
63 #define CONFIG_SRIO_PCIE_BOOT_MASTER
64 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
65 /* Set 1M boot space */
66 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
67 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
68 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
69 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
72 #ifndef CONFIG_RESET_VECTOR_ADDRESS
73 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
77 * These can be toggled for performance analysis, otherwise use default.
79 #define CONFIG_SYS_CACHE_STASHING
81 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
85 * Config the L3 Cache as L3 SRAM
87 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
88 #define CONFIG_SYS_L3_SIZE (512 << 10)
89 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
91 #define CONFIG_SYS_DCSRBAR 0xf0000000
92 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
95 #define CONFIG_SYS_I2C_EEPROM_NXID
96 #define CONFIG_SYS_EEPROM_BUS_NUM 0
101 #define CONFIG_VERY_BIG_RAM
102 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
103 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
104 #define CONFIG_SYS_SPD_BUS_NUM 0
105 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
106 #define SPD_EEPROM_ADDRESS1 0x51
107 #define SPD_EEPROM_ADDRESS2 0x52
108 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
109 #define CTRL_INTLV_PREFERED cacheline
114 #define CONFIG_SYS_FLASH_BASE 0xe8000000
115 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
116 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
117 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
118 CSPR_PORT_SIZE_16 | \
121 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
123 /* NOR Flash Timing Params */
124 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
126 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
127 FTIM0_NOR_TEADC(0x5) | \
128 FTIM0_NOR_TEAHC(0x5))
129 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
130 FTIM1_NOR_TRAD_NOR(0x1A) |\
131 FTIM1_NOR_TSEQRAD_NOR(0x13))
132 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
133 FTIM2_NOR_TCH(0x4) | \
134 FTIM2_NOR_TWPH(0x0E) | \
136 #define CONFIG_SYS_NOR_FTIM3 0x0
138 #define CONFIG_SYS_FLASH_QUIET_TEST
139 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
141 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
142 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
143 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
144 #define CONFIG_SYS_FLASH_EMPTY_INFO
145 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS }
148 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
149 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
150 #define CONFIG_SYS_CSPR2_EXT (0xf)
151 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
155 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
156 #define CONFIG_SYS_CSOR2 0x0
158 /* CPLD Timing parameters for IFC CS2 */
159 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
160 FTIM0_GPCM_TEADC(0x0e) | \
161 FTIM0_GPCM_TEAHC(0x0e))
162 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
163 FTIM1_GPCM_TRAD(0x1f))
164 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
165 FTIM2_GPCM_TCH(0x8) | \
166 FTIM2_GPCM_TWP(0x1f))
167 #define CONFIG_SYS_CS2_FTIM3 0x0
169 /* NAND Flash on IFC */
170 #define CONFIG_SYS_NAND_BASE 0xff800000
171 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
173 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
174 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
175 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
176 | CSPR_MSEL_NAND /* MSEL = NAND */ \
178 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
180 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
181 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
182 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
183 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
184 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
185 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
186 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
188 /* ONFI NAND Flash mode0 Timing Params */
189 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
190 FTIM0_NAND_TWP(0x18) | \
191 FTIM0_NAND_TWCHT(0x07) | \
192 FTIM0_NAND_TWH(0x0a))
193 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
194 FTIM1_NAND_TWBE(0x39) | \
195 FTIM1_NAND_TRR(0x0e) | \
196 FTIM1_NAND_TRP(0x18))
197 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
198 FTIM2_NAND_TREH(0x0a) | \
199 FTIM2_NAND_TWHRE(0x1e))
200 #define CONFIG_SYS_NAND_FTIM3 0x0
202 #define CONFIG_SYS_NAND_DDR_LAW 11
203 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
204 #define CONFIG_SYS_MAX_NAND_DEVICE 1
206 #if defined(CONFIG_MTD_RAW_NAND)
207 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
208 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
209 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
210 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
211 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
212 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
213 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
214 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
215 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
216 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
217 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
218 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
219 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
220 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
221 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
222 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
224 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
225 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
226 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
227 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
228 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
229 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
230 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
231 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
232 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
233 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
234 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
235 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
236 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
237 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
238 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
239 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
242 #if defined(CONFIG_RAMBOOT_PBL)
243 #define CONFIG_SYS_RAMBOOT
246 #define CONFIG_HWCONFIG
248 /* define to use L1 as initial stack */
249 #define CONFIG_L1_INIT_RAM
250 #define CONFIG_SYS_INIT_RAM_LOCK
251 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
252 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
253 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
254 /* The assembler doesn't like typecast */
255 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
256 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
257 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
258 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
259 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
260 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
265 #define CONFIG_SYS_NS16550_SERIAL
266 #define CONFIG_SYS_NS16550_REG_SIZE 1
267 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
268 #define CONFIG_SYS_BAUDRATE_TABLE \
269 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
270 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
271 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
272 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
273 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
279 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
280 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
281 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
282 #define I2C_MUX_CH_DEFAULT 0x8
284 #define I2C_MUX_CH_VOL_MONITOR 0xa
286 /* The lowest and highest voltage allowed for T208xRDB */
287 #define VDD_MV_MIN 819
288 #define VDD_MV_MAX 1212
293 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
294 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
295 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
296 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
297 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
298 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
300 * for slave u-boot IMAGE instored in master memory space,
301 * PHYS must be aligned based on the SIZE
303 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
304 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
305 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
306 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
308 * for slave UCODE and ENV instored in master memory space,
309 * PHYS must be aligned based on the SIZE
311 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
312 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
313 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
315 /* slave core release by master*/
316 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
317 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
320 * SRIO_PCIE_BOOT - SLAVE
322 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
323 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
324 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
325 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
329 * eSPI - Enhanced SPI
334 * Memory space is mapped 1-1, but I/O space must start from 0.
336 #define CONFIG_PCIE1 /* PCIE controller 1 */
337 #define CONFIG_PCIE2 /* PCIE controller 2 */
338 #define CONFIG_PCIE3 /* PCIE controller 3 */
339 #define CONFIG_PCIE4 /* PCIE controller 4 */
340 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
341 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
342 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
343 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
344 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
346 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
347 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
348 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
349 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
350 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
352 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
353 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
354 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
355 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
356 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
358 /* controller 4, Base address 203000 */
359 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
360 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
361 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
364 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
368 #ifndef CONFIG_NOBQFMAN
369 #define CONFIG_SYS_BMAN_NUM_PORTALS 18
370 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
371 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
372 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
373 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
374 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
375 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
376 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
377 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
378 CONFIG_SYS_BMAN_CENA_SIZE)
379 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
380 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
381 #define CONFIG_SYS_QMAN_NUM_PORTALS 18
382 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
383 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
384 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
385 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
386 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
387 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
388 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
389 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
390 CONFIG_SYS_QMAN_CENA_SIZE)
391 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
392 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
394 #define CONFIG_SYS_DPAA_FMAN
395 #define CONFIG_SYS_DPAA_PME
396 #define CONFIG_SYS_PMAN
397 #define CONFIG_SYS_DPAA_DCE
398 #define CONFIG_SYS_DPAA_RMAN /* RMan */
399 #define CONFIG_SYS_INTERLAKEN
401 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
402 #endif /* CONFIG_NOBQFMAN */
404 #ifdef CONFIG_SYS_DPAA_FMAN
405 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
406 #define RGMII_PHY2_ADDR 0x02
407 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */
408 #define CORTINA_PHY_ADDR2 0x0d
409 /* Aquantia AQ1202 10G Base-T used by board revisions up to C */
410 #define FM1_10GEC3_PHY_ADDR 0x00
411 #define FM1_10GEC4_PHY_ADDR 0x01
412 /* Aquantia AQR113C 10G Base-T used by board revisions D and up */
413 #define AQR113C_PHY_ADDR1 0x00
414 #define AQR113C_PHY_ADDR2 0x08
420 #ifdef CONFIG_FSL_SATA_V2
422 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
423 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
425 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
426 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
438 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
439 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
443 * Dynamic MTD Partition support with mtdparts
451 * Miscellaneous configurable options
455 * For booting Linux, the board info and command line data
456 * have to be in the first 64 MB of memory, since this is
457 * the maximum mapped by the Linux kernel during initialization.
459 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
460 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
463 * Environment Configuration
465 #define CONFIG_ROOTPATH "/opt/nfsroot"
466 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
468 #define __USB_PHY_TYPE utmi
470 #define CONFIG_EXTRA_ENV_SETTINGS \
471 "hwconfig=fsl_ddr:" \
472 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
474 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
476 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
477 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
478 "tftpflash=tftpboot $loadaddr $uboot && " \
479 "protect off $ubootaddr +$filesize && " \
480 "erase $ubootaddr +$filesize && " \
481 "cp.b $loadaddr $ubootaddr $filesize && " \
482 "protect on $ubootaddr +$filesize && " \
483 "cmp.b $loadaddr $ubootaddr $filesize\0" \
484 "consoledev=ttyS0\0" \
485 "ramdiskaddr=2000000\0" \
486 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \
487 "fdtaddr=1e00000\0" \
488 "fdtfile=t2080rdb/t2080rdb.dtb\0" \
492 * For emulation this causes u-boot to jump to the start of the
493 * proof point app code automatically
495 #define PROOF_POINTS \
496 "setenv bootargs root=/dev/$bdev rw " \
497 "console=$consoledev,$baudrate $othbootargs;" \
498 "cpu 1 release 0x29000000 - - -;" \
499 "cpu 2 release 0x29000000 - - -;" \
500 "cpu 3 release 0x29000000 - - -;" \
501 "cpu 4 release 0x29000000 - - -;" \
502 "cpu 5 release 0x29000000 - - -;" \
503 "cpu 6 release 0x29000000 - - -;" \
504 "cpu 7 release 0x29000000 - - -;" \
508 "setenv bootargs config-addr=0x60000000; " \
509 "bootm 0x01000000 - 0x00f00000"
512 "setenv bootargs root=/dev/$bdev rw " \
513 "console=$consoledev,$baudrate $othbootargs;" \
514 "cpu 1 release 0x01000000 - - -;" \
515 "cpu 2 release 0x01000000 - - -;" \
516 "cpu 3 release 0x01000000 - - -;" \
517 "cpu 4 release 0x01000000 - - -;" \
518 "cpu 5 release 0x01000000 - - -;" \
519 "cpu 6 release 0x01000000 - - -;" \
520 "cpu 7 release 0x01000000 - - -;" \
523 #include <asm/fsl_secure_boot.h>
525 #endif /* __T2080RDB_H */