1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
8 * T2080 RDB/PCIe board configuration file
14 #include <linux/stringify.h>
16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
17 #define CONFIG_FSL_SATA_V2
19 /* High Level Configuration Options */
20 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
21 #define CONFIG_ENABLE_36BIT_PHYS
23 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
24 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
26 #ifdef CONFIG_RAMBOOT_PBL
27 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
29 #define CONFIG_SPL_FLUSH_IMAGE
30 #define CONFIG_SPL_PAD_TO 0x40000
31 #define CONFIG_SPL_MAX_SIZE 0x28000
32 #define RESET_VECTOR_OFFSET 0x27FFC
33 #define BOOT_PAGE_OFFSET 0x27000
34 #ifdef CONFIG_SPL_BUILD
35 #define CONFIG_SPL_SKIP_RELOCATE
36 #define CONFIG_SPL_COMMON_INIT_DDR
37 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
40 #ifdef CONFIG_MTD_RAW_NAND
41 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
42 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
43 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
44 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
45 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg
48 #ifdef CONFIG_SPIFLASH
49 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
50 #define CONFIG_SPL_SPI_FLASH_MINIMAL
51 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
52 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
53 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
54 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
55 #ifndef CONFIG_SPL_BUILD
56 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
58 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg
62 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
63 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
64 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
65 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
66 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
67 #ifndef CONFIG_SPL_BUILD
68 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
70 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg
73 #endif /* CONFIG_RAMBOOT_PBL */
75 #define CONFIG_SRIO_PCIE_BOOT_MASTER
76 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
77 /* Set 1M boot space */
78 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
79 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
80 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
81 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
84 #ifndef CONFIG_RESET_VECTOR_ADDRESS
85 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
89 * These can be toggled for performance analysis, otherwise use default.
91 #define CONFIG_SYS_CACHE_STASHING
92 #define CONFIG_BTB /* toggle branch predition */
93 #define CONFIG_DDR_ECC
95 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
96 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
100 unsigned long get_board_sys_clk(void);
101 unsigned long get_board_ddr_clk(void);
104 #define CONFIG_SYS_CLK_FREQ 66660000
105 #define CONFIG_DDR_CLK_FREQ 133330000
108 * Config the L3 Cache as L3 SRAM
110 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
111 #define CONFIG_SYS_L3_SIZE (512 << 10)
112 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
113 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
114 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
115 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
116 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
118 #define CONFIG_SYS_DCSRBAR 0xf0000000
119 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
122 #define CONFIG_SYS_I2C_EEPROM_NXID
123 #define CONFIG_SYS_EEPROM_BUS_NUM 0
128 #define CONFIG_VERY_BIG_RAM
129 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
130 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
131 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
132 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
133 #define CONFIG_DDR_SPD
134 #define CONFIG_SYS_SPD_BUS_NUM 0
135 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
136 #define SPD_EEPROM_ADDRESS1 0x51
137 #define SPD_EEPROM_ADDRESS2 0x52
138 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
139 #define CTRL_INTLV_PREFERED cacheline
144 #define CONFIG_SYS_FLASH_BASE 0xe8000000
145 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
146 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
147 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
148 CSPR_PORT_SIZE_16 | \
151 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
153 /* NOR Flash Timing Params */
154 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
156 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
157 FTIM0_NOR_TEADC(0x5) | \
158 FTIM0_NOR_TEAHC(0x5))
159 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
160 FTIM1_NOR_TRAD_NOR(0x1A) |\
161 FTIM1_NOR_TSEQRAD_NOR(0x13))
162 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
163 FTIM2_NOR_TCH(0x4) | \
164 FTIM2_NOR_TWPH(0x0E) | \
166 #define CONFIG_SYS_NOR_FTIM3 0x0
168 #define CONFIG_SYS_FLASH_QUIET_TEST
169 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
171 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
172 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
173 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
174 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
175 #define CONFIG_SYS_FLASH_EMPTY_INFO
176 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS }
179 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
180 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
181 #define CONFIG_SYS_CSPR2_EXT (0xf)
182 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
186 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
187 #define CONFIG_SYS_CSOR2 0x0
189 /* CPLD Timing parameters for IFC CS2 */
190 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
191 FTIM0_GPCM_TEADC(0x0e) | \
192 FTIM0_GPCM_TEAHC(0x0e))
193 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
194 FTIM1_GPCM_TRAD(0x1f))
195 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
196 FTIM2_GPCM_TCH(0x8) | \
197 FTIM2_GPCM_TWP(0x1f))
198 #define CONFIG_SYS_CS2_FTIM3 0x0
200 /* NAND Flash on IFC */
201 #define CONFIG_NAND_FSL_IFC
202 #define CONFIG_SYS_NAND_BASE 0xff800000
203 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
205 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
206 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
207 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
208 | CSPR_MSEL_NAND /* MSEL = NAND */ \
210 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
212 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
213 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
214 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
215 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
216 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
217 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
218 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
220 #define CONFIG_SYS_NAND_ONFI_DETECTION
222 /* ONFI NAND Flash mode0 Timing Params */
223 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
224 FTIM0_NAND_TWP(0x18) | \
225 FTIM0_NAND_TWCHT(0x07) | \
226 FTIM0_NAND_TWH(0x0a))
227 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
228 FTIM1_NAND_TWBE(0x39) | \
229 FTIM1_NAND_TRR(0x0e) | \
230 FTIM1_NAND_TRP(0x18))
231 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
232 FTIM2_NAND_TREH(0x0a) | \
233 FTIM2_NAND_TWHRE(0x1e))
234 #define CONFIG_SYS_NAND_FTIM3 0x0
236 #define CONFIG_SYS_NAND_DDR_LAW 11
237 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
238 #define CONFIG_SYS_MAX_NAND_DEVICE 1
239 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
241 #if defined(CONFIG_MTD_RAW_NAND)
242 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
243 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
244 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
245 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
246 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
247 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
248 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
249 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
250 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
251 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
252 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
253 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
254 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
255 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
256 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
257 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
259 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
260 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
261 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
262 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
263 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
264 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
265 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
266 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
267 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
268 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
269 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
270 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
271 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
272 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
273 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
274 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
277 #if defined(CONFIG_RAMBOOT_PBL)
278 #define CONFIG_SYS_RAMBOOT
281 #ifdef CONFIG_SPL_BUILD
282 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
284 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
287 #define CONFIG_HWCONFIG
289 /* define to use L1 as initial stack */
290 #define CONFIG_L1_INIT_RAM
291 #define CONFIG_SYS_INIT_RAM_LOCK
292 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
293 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
294 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
295 /* The assembler doesn't like typecast */
296 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
297 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
298 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
299 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
300 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
301 GENERATED_GBL_DATA_SIZE)
302 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
303 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
304 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
309 #define CONFIG_SYS_NS16550_SERIAL
310 #define CONFIG_SYS_NS16550_REG_SIZE 1
311 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
312 #define CONFIG_SYS_BAUDRATE_TABLE \
313 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
314 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
315 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
316 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
317 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
322 #if !CONFIG_IS_ENABLED(DM_I2C)
323 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
324 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
325 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
326 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
327 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
328 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
329 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
330 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
331 #define CONFIG_SYS_FSL_I2C_SPEED 100000
332 #define CONFIG_SYS_FSL_I2C2_SPEED 100000
333 #define CONFIG_SYS_FSL_I2C3_SPEED 100000
334 #define CONFIG_SYS_FSL_I2C4_SPEED 100000
336 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
337 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
340 #define CONFIG_SYS_I2C_FSL
342 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
343 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
344 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
345 #define I2C_MUX_CH_DEFAULT 0x8
347 #define I2C_MUX_CH_VOL_MONITOR 0xa
349 #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv"
350 #ifndef CONFIG_SPL_BUILD
353 #define CONFIG_VOL_MONITOR_IR36021_SET
354 #define CONFIG_VOL_MONITOR_IR36021_READ
355 /* The lowest and highest voltage allowed for T208xRDB */
356 #define VDD_MV_MIN 819
357 #define VDD_MV_MAX 1212
362 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
363 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
364 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
365 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
366 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
367 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
369 * for slave u-boot IMAGE instored in master memory space,
370 * PHYS must be aligned based on the SIZE
372 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
373 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
374 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
375 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
377 * for slave UCODE and ENV instored in master memory space,
378 * PHYS must be aligned based on the SIZE
380 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
381 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
382 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
384 /* slave core release by master*/
385 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
386 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
389 * SRIO_PCIE_BOOT - SLAVE
391 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
392 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
393 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
394 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
398 * eSPI - Enhanced SPI
403 * Memory space is mapped 1-1, but I/O space must start from 0.
405 #define CONFIG_PCIE1 /* PCIE controller 1 */
406 #define CONFIG_PCIE2 /* PCIE controller 2 */
407 #define CONFIG_PCIE3 /* PCIE controller 3 */
408 #define CONFIG_PCIE4 /* PCIE controller 4 */
409 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
410 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
411 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
412 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
413 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
414 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
416 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
417 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
418 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
419 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
420 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
422 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
423 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
424 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
425 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
426 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
428 /* controller 4, Base address 203000 */
429 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
430 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
431 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
434 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
438 #ifndef CONFIG_NOBQFMAN
439 #define CONFIG_SYS_BMAN_NUM_PORTALS 18
440 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
441 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
442 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
443 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
444 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
445 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
446 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
447 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
448 CONFIG_SYS_BMAN_CENA_SIZE)
449 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
450 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
451 #define CONFIG_SYS_QMAN_NUM_PORTALS 18
452 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
453 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
454 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
455 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
456 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
457 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
458 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
459 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
460 CONFIG_SYS_QMAN_CENA_SIZE)
461 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
462 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
464 #define CONFIG_SYS_DPAA_FMAN
465 #define CONFIG_SYS_DPAA_PME
466 #define CONFIG_SYS_PMAN
467 #define CONFIG_SYS_DPAA_DCE
468 #define CONFIG_SYS_DPAA_RMAN /* RMan */
469 #define CONFIG_SYS_INTERLAKEN
471 /* Default address of microcode for the Linux Fman driver */
472 #if defined(CONFIG_SPIFLASH)
474 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
475 * env, so we got 0x110000.
477 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
479 #elif defined(CONFIG_SDCARD)
481 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
482 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
483 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
485 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
487 #elif defined(CONFIG_MTD_RAW_NAND)
488 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
489 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
491 * Slave has no ucode locally, it can fetch this from remote. When implementing
492 * in two corenet boards, slave's ucode could be stored in master's memory
493 * space, the address can be mapped from slave TLB->slave LAW->
494 * slave SRIO or PCIE outbound window->master inbound window->
495 * master LAW->the ucode address in master's memory space.
497 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
499 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
501 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
502 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
503 #endif /* CONFIG_NOBQFMAN */
505 #ifdef CONFIG_SYS_DPAA_FMAN
506 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
507 #define RGMII_PHY2_ADDR 0x02
508 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */
509 #define CORTINA_PHY_ADDR2 0x0d
510 /* Aquantia AQ1202 10G Base-T used by board revisions up to C */
511 #define FM1_10GEC3_PHY_ADDR 0x00
512 #define FM1_10GEC4_PHY_ADDR 0x01
513 /* Aquantia AQR113C 10G Base-T used by board revisions D and up */
514 #define AQR113C_PHY_ADDR1 0x00
515 #define AQR113C_PHY_ADDR2 0x08
518 #ifdef CONFIG_FMAN_ENET
519 #define CONFIG_ETHPRIME "FM1@DTSEC3"
525 #ifdef CONFIG_FSL_SATA_V2
526 #define CONFIG_SYS_SATA_MAX_DEVICE 2
528 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
529 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
531 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
532 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
539 #ifdef CONFIG_USB_EHCI_HCD
540 #define CONFIG_USB_EHCI_FSL
541 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
542 #define CONFIG_HAS_FSL_DR_USB
549 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
550 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
554 * Dynamic MTD Partition support with mtdparts
562 * Miscellaneous configurable options
564 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
567 * For booting Linux, the board info and command line data
568 * have to be in the first 64 MB of memory, since this is
569 * the maximum mapped by the Linux kernel during initialization.
571 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
572 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
574 #ifdef CONFIG_CMD_KGDB
575 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
576 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
580 * Environment Configuration
582 #define CONFIG_ROOTPATH "/opt/nfsroot"
583 #define CONFIG_BOOTFILE "uImage"
584 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
586 /* default location for tftp and bootm */
587 #define CONFIG_LOADADDR 1000000
588 #define __USB_PHY_TYPE utmi
590 #define CONFIG_EXTRA_ENV_SETTINGS \
591 "hwconfig=fsl_ddr:" \
592 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
594 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
596 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
597 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
598 "tftpflash=tftpboot $loadaddr $uboot && " \
599 "protect off $ubootaddr +$filesize && " \
600 "erase $ubootaddr +$filesize && " \
601 "cp.b $loadaddr $ubootaddr $filesize && " \
602 "protect on $ubootaddr +$filesize && " \
603 "cmp.b $loadaddr $ubootaddr $filesize\0" \
604 "consoledev=ttyS0\0" \
605 "ramdiskaddr=2000000\0" \
606 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \
607 "fdtaddr=1e00000\0" \
608 "fdtfile=t2080rdb/t2080rdb.dtb\0" \
612 * For emulation this causes u-boot to jump to the start of the
613 * proof point app code automatically
615 #define CONFIG_PROOF_POINTS \
616 "setenv bootargs root=/dev/$bdev rw " \
617 "console=$consoledev,$baudrate $othbootargs;" \
618 "cpu 1 release 0x29000000 - - -;" \
619 "cpu 2 release 0x29000000 - - -;" \
620 "cpu 3 release 0x29000000 - - -;" \
621 "cpu 4 release 0x29000000 - - -;" \
622 "cpu 5 release 0x29000000 - - -;" \
623 "cpu 6 release 0x29000000 - - -;" \
624 "cpu 7 release 0x29000000 - - -;" \
627 #define CONFIG_HVBOOT \
628 "setenv bootargs config-addr=0x60000000; " \
629 "bootm 0x01000000 - 0x00f00000"
632 "setenv bootargs root=/dev/$bdev rw " \
633 "console=$consoledev,$baudrate $othbootargs;" \
634 "cpu 1 release 0x01000000 - - -;" \
635 "cpu 2 release 0x01000000 - - -;" \
636 "cpu 3 release 0x01000000 - - -;" \
637 "cpu 4 release 0x01000000 - - -;" \
638 "cpu 5 release 0x01000000 - - -;" \
639 "cpu 6 release 0x01000000 - - -;" \
640 "cpu 7 release 0x01000000 - - -;" \
643 #define CONFIG_LINUX \
644 "setenv bootargs root=/dev/ram rw " \
645 "console=$consoledev,$baudrate $othbootargs;" \
646 "setenv ramdiskaddr 0x02000000;" \
647 "setenv fdtaddr 0x00c00000;" \
648 "setenv loadaddr 0x1000000;" \
649 "bootm $loadaddr $ramdiskaddr $fdtaddr"
651 #define CONFIG_HDBOOT \
652 "setenv bootargs root=/dev/$bdev rw " \
653 "console=$consoledev,$baudrate $othbootargs;" \
654 "tftp $loadaddr $bootfile;" \
655 "tftp $fdtaddr $fdtfile;" \
656 "bootm $loadaddr - $fdtaddr"
658 #define CONFIG_NFSBOOTCOMMAND \
659 "setenv bootargs root=/dev/nfs rw " \
660 "nfsroot=$serverip:$rootpath " \
661 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
662 "console=$consoledev,$baudrate $othbootargs;" \
663 "tftp $loadaddr $bootfile;" \
664 "tftp $fdtaddr $fdtfile;" \
665 "bootm $loadaddr - $fdtaddr"
667 #define CONFIG_RAMBOOTCOMMAND \
668 "setenv bootargs root=/dev/ram rw " \
669 "console=$consoledev,$baudrate $othbootargs;" \
670 "tftp $ramdiskaddr $ramdiskfile;" \
671 "tftp $loadaddr $bootfile;" \
672 "tftp $fdtaddr $fdtfile;" \
673 "bootm $loadaddr $ramdiskaddr $fdtaddr"
675 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
677 #include <asm/fsl_secure_boot.h>
679 #endif /* __T2080RDB_H */