include/configs/T208xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T2080 RDB/PCIe board configuration file
   9  */
  10
  11 #ifndef __T2080RDB_H
  12 #define __T2080RDB_H
  13
  14 #include <linux/stringify.h>
  15
  16 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  17
  18 /* High Level Configuration Options */
  19
  20 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  21 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  22
  23 #ifdef CONFIG_RAMBOOT_PBL
  24 #define RESET_VECTOR_OFFSET             0x27FFC
  25 #define BOOT_PAGE_OFFSET                0x27000
  26
  27 #ifdef CONFIG_MTD_RAW_NAND
  28 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  29 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  30 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  31 #endif
  32
  33 #ifdef CONFIG_SPIFLASH
  34 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  35 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
  36 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
  37 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
  38 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
  39 #endif
  40
  41 #ifdef CONFIG_SDCARD
  42 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  43 #define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
  44 #define CONFIG_SYS_MMC_U_BOOT_DST      (0x00200000)
  45 #define CONFIG_SYS_MMC_U_BOOT_START    (0x00200000)
  46 #define CONFIG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
  47 #endif
  48
  49 #endif /* CONFIG_RAMBOOT_PBL */
  50
  51 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  52 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  53 /* Set 1M boot space */
  54 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  55 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  56                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  57 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  58 #endif
  59
  60 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  61 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  62 #endif
  63
  64 /*
  65  * These can be toggled for performance analysis, otherwise use default.
  66  */
  67 #define CONFIG_SYS_CACHE_STASHING
  68 #ifdef CONFIG_DDR_ECC
  69 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  70 #endif
  71
  72 /*
  73  * Config the L3 Cache as L3 SRAM
  74  */
  75 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
  76 #define CONFIG_SYS_L3_SIZE              (512 << 10)
  77 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
  78
  79 #define CONFIG_SYS_DCSRBAR      0xf0000000
  80 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  81
  82 /* EEPROM */
  83 #define CONFIG_SYS_I2C_EEPROM_NXID
  84 #define CONFIG_SYS_EEPROM_BUS_NUM       0
  85
  86 /*
  87  * DDR Setup
  88  */
  89 #define CONFIG_VERY_BIG_RAM
  90 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  91 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  92 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
  93 #define SPD_EEPROM_ADDRESS1     0x51
  94 #define SPD_EEPROM_ADDRESS2     0x52
  95 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  96 #define CTRL_INTLV_PREFERED     cacheline
  97
  98 /*
  99  * IFC Definitions
 100  */
 101 #define CONFIG_SYS_FLASH_BASE           0xe8000000
 102 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 103 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 104 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 105                                 CSPR_PORT_SIZE_16 | \
 106                                 CSPR_MSEL_NOR | \
 107                                 CSPR_V)
 108 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 109
 110 /* NOR Flash Timing Params */
 111 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 112
 113 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 114                                 FTIM0_NOR_TEADC(0x5) | \
 115                                 FTIM0_NOR_TEAHC(0x5))
 116 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 117                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 118                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 119 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 120                                 FTIM2_NOR_TCH(0x4) | \
 121                                 FTIM2_NOR_TWPH(0x0E) | \
 122                                 FTIM2_NOR_TWP(0x1c))
 123 #define CONFIG_SYS_NOR_FTIM3    0x0
 124
 125 #define CONFIG_SYS_FLASH_QUIET_TEST
 126 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 127
 128 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 129 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 130 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 131 #define CONFIG_SYS_FLASH_EMPTY_INFO
 132 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS }
 133
 134 /* CPLD on IFC */
 135 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 136 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 137 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 138 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 139                                 | CSPR_PORT_SIZE_8 \
 140                                 | CSPR_MSEL_GPCM \
 141                                 | CSPR_V)
 142 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 143 #define CONFIG_SYS_CSOR2        0x0
 144
 145 /* CPLD Timing parameters for IFC CS2 */
 146 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 147                                         FTIM0_GPCM_TEADC(0x0e) | \
 148                                         FTIM0_GPCM_TEAHC(0x0e))
 149 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 150                                         FTIM1_GPCM_TRAD(0x1f))
 151 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 152                                         FTIM2_GPCM_TCH(0x8) | \
 153                                         FTIM2_GPCM_TWP(0x1f))
 154 #define CONFIG_SYS_CS2_FTIM3            0x0
 155
 156 /* NAND Flash on IFC */
 157 #define CONFIG_SYS_NAND_BASE            0xff800000
 158 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 159
 160 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 161 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 162                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 163                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 164                                 | CSPR_V)
 165 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 166
 167 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 168                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 169                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 170                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 171                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 172                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 173                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 174
 175 /* ONFI NAND Flash mode0 Timing Params */
 176 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 177                                         FTIM0_NAND_TWP(0x18)    | \
 178                                         FTIM0_NAND_TWCHT(0x07)  | \
 179                                         FTIM0_NAND_TWH(0x0a))
 180 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 181                                         FTIM1_NAND_TWBE(0x39)   | \
 182                                         FTIM1_NAND_TRR(0x0e)    | \
 183                                         FTIM1_NAND_TRP(0x18))
 184 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 185                                         FTIM2_NAND_TREH(0x0a)   | \
 186                                         FTIM2_NAND_TWHRE(0x1e))
 187 #define CONFIG_SYS_NAND_FTIM3           0x0
 188
 189 #define CONFIG_SYS_NAND_DDR_LAW         11
 190 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 191 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 192
 193 #if defined(CONFIG_MTD_RAW_NAND)
 194 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 195 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 196 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 197 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 198 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 199 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 200 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 201 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 202 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 203 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 204 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 205 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 206 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 207 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 208 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 209 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 210 #else
 211 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 212 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 213 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 214 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 215 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 216 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 217 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 218 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 219 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 220 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 221 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 222 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 223 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 224 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 225 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 226 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 227 #endif
 228
 229 #if defined(CONFIG_RAMBOOT_PBL)
 230 #define CONFIG_SYS_RAMBOOT
 231 #endif
 232
 233 #define CONFIG_HWCONFIG
 234
 235 /* define to use L1 as initial stack */
 236 #define CONFIG_L1_INIT_RAM
 237 #define CONFIG_SYS_INIT_RAM_LOCK
 238 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 239 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 240 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 241 /* The assembler doesn't like typecast */
 242 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 243                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 244                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 245 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 246 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 247 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 248
 249 /*
 250  * Serial Port
 251  */
 252 #define CONFIG_SYS_NS16550_SERIAL
 253 #define CONFIG_SYS_NS16550_REG_SIZE     1
 254 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 255 #define CONFIG_SYS_BAUDRATE_TABLE       \
 256         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 257 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 258 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 259 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 260 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 261
 262 /*
 263  * I2C
 264  */
 265
 266 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 267 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 268 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 269 #define I2C_MUX_CH_DEFAULT      0x8
 270
 271 #define I2C_MUX_CH_VOL_MONITOR  0xa
 272
 273 /* The lowest and highest voltage allowed for T208xRDB */
 274 #define VDD_MV_MIN                      819
 275 #define VDD_MV_MAX                      1212
 276
 277 /*
 278  * RapidIO
 279  */
 280 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 281 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 282 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 283 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 284 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 285 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 286 /*
 287  * for slave u-boot IMAGE instored in master memory space,
 288  * PHYS must be aligned based on the SIZE
 289  */
 290 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 291 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 292 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 293 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 294 /*
 295  * for slave UCODE and ENV instored in master memory space,
 296  * PHYS must be aligned based on the SIZE
 297  */
 298 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 299 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 300 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 301
 302 /* slave core release by master*/
 303 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 304 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 305
 306 /*
 307  * SRIO_PCIE_BOOT - SLAVE
 308  */
 309 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 310 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 311 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 312                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 313 #endif
 314
 315 /*
 316  * eSPI - Enhanced SPI
 317  */
 318
 319 /*
 320  * General PCI
 321  * Memory space is mapped 1-1, but I/O space must start from 0.
 322  */
 323 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 324 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 325 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 326 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 327 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 328
 329 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 330 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 331 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 332 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 333 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 334
 335 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 336 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 337 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 338 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 339 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 340
 341 /* controller 4, Base address 203000 */
 342 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 343 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 344 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 345
 346 /* Qman/Bman */
 347 #ifndef CONFIG_NOBQFMAN
 348 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 349 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 350 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 351 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 352 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 353 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 354 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 355 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 356 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 357                                         CONFIG_SYS_BMAN_CENA_SIZE)
 358 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 359 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 360 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 361 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 362 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 363 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 364 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 365 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 366 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 367 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 368 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 369                                         CONFIG_SYS_QMAN_CENA_SIZE)
 370 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 371 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 372
 373 #define CONFIG_SYS_DPAA_FMAN
 374 #define CONFIG_SYS_DPAA_PME
 375 #define CONFIG_SYS_PMAN
 376 #define CONFIG_SYS_DPAA_DCE
 377 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 378 #define CONFIG_SYS_INTERLAKEN
 379
 380 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 381 #endif /* CONFIG_NOBQFMAN */
 382
 383 #ifdef CONFIG_SYS_DPAA_FMAN
 384 #define RGMII_PHY1_ADDR         0x01  /* RealTek RTL8211E */
 385 #define RGMII_PHY2_ADDR         0x02
 386 #define CORTINA_PHY_ADDR1       0x0c  /* Cortina CS4315 */
 387 #define CORTINA_PHY_ADDR2       0x0d
 388 /* Aquantia AQ1202 10G Base-T used by board revisions up to C */
 389 #define FM1_10GEC3_PHY_ADDR     0x00
 390 #define FM1_10GEC4_PHY_ADDR     0x01
 391 /* Aquantia AQR113C 10G Base-T used by board revisions D and up */
 392 #define AQR113C_PHY_ADDR1       0x00
 393 #define AQR113C_PHY_ADDR2       0x08
 394 #endif
 395
 396 /*
 397  * USB
 398  */
 399
 400 /*
 401  * SDHC
 402  */
 403 #ifdef CONFIG_MMC
 404 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 405 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 406 #endif
 407
 408 /*
 409  * Dynamic MTD Partition support with mtdparts
 410  */
 411
 412 /*
 413  * Environment
 414  */
 415
 416 /*
 417  * Miscellaneous configurable options
 418  */
 419
 420 /*
 421  * For booting Linux, the board info and command line data
 422  * have to be in the first 64 MB of memory, since this is
 423  * the maximum mapped by the Linux kernel during initialization.
 424  */
 425 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 426 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 427
 428 /*
 429  * Environment Configuration
 430  */
 431 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 432 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 433
 434 #define __USB_PHY_TYPE          utmi
 435
 436 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 437         "hwconfig=fsl_ddr:"                                     \
 438         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 439         "bank_intlv=auto;"                                      \
 440         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 441         "netdev=eth0\0"                                         \
 442         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 443         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 444         "tftpflash=tftpboot $loadaddr $uboot && "               \
 445         "protect off $ubootaddr +$filesize && "                 \
 446         "erase $ubootaddr +$filesize && "                       \
 447         "cp.b $loadaddr $ubootaddr $filesize && "               \
 448         "protect on $ubootaddr +$filesize && "                  \
 449         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 450         "consoledev=ttyS0\0"                                    \
 451         "ramdiskaddr=2000000\0"                                 \
 452         "ramdiskfile=t2080rdb/ramdisk.uboot\0"                  \
 453         "fdtaddr=1e00000\0"                                     \
 454         "fdtfile=t2080rdb/t2080rdb.dtb\0"                       \
 455         "bdev=sda3\0"
 456
 457 /*
 458  * For emulation this causes u-boot to jump to the start of the
 459  * proof point app code automatically
 460  */
 461 #define PROOF_POINTS                            \
 462         "setenv bootargs root=/dev/$bdev rw "           \
 463         "console=$consoledev,$baudrate $othbootargs;"   \
 464         "cpu 1 release 0x29000000 - - -;"               \
 465         "cpu 2 release 0x29000000 - - -;"               \
 466         "cpu 3 release 0x29000000 - - -;"               \
 467         "cpu 4 release 0x29000000 - - -;"               \
 468         "cpu 5 release 0x29000000 - - -;"               \
 469         "cpu 6 release 0x29000000 - - -;"               \
 470         "cpu 7 release 0x29000000 - - -;"               \
 471         "go 0x29000000"
 472
 473 #define HVBOOT                          \
 474         "setenv bootargs config-addr=0x60000000; "      \
 475         "bootm 0x01000000 - 0x00f00000"
 476
 477 #define ALU                             \
 478         "setenv bootargs root=/dev/$bdev rw "           \
 479         "console=$consoledev,$baudrate $othbootargs;"   \
 480         "cpu 1 release 0x01000000 - - -;"               \
 481         "cpu 2 release 0x01000000 - - -;"               \
 482         "cpu 3 release 0x01000000 - - -;"               \
 483         "cpu 4 release 0x01000000 - - -;"               \
 484         "cpu 5 release 0x01000000 - - -;"               \
 485         "cpu 6 release 0x01000000 - - -;"               \
 486         "cpu 7 release 0x01000000 - - -;"               \
 487         "go 0x01000000"
 488
 489 #include <asm/fsl_secure_boot.h>
 490
 491 #endif  /* __T2080RDB_H */