include/configs/T208xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T2080 RDB/PCIe board configuration file
   9  */
  10
  11 #ifndef __T2080RDB_H
  12 #define __T2080RDB_H
  13
  14 #include <linux/stringify.h>
  15
  16 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  17
  18 /* High Level Configuration Options */
  19
  20 #define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  21
  22 #ifdef CONFIG_RAMBOOT_PBL
  23 #define RESET_VECTOR_OFFSET             0x27FFC
  24 #define BOOT_PAGE_OFFSET                0x27000
  25
  26 #ifdef CONFIG_MTD_RAW_NAND
  27 #define CFG_SYS_NAND_U_BOOT_SIZE        (768 << 10)
  28 #define CFG_SYS_NAND_U_BOOT_DST 0x00200000
  29 #define CFG_SYS_NAND_U_BOOT_START       0x00200000
  30 #endif
  31
  32 #ifdef CONFIG_SPIFLASH
  33 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  34 #define CFG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
  35 #define CFG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
  36 #define CFG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
  37 #define CFG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
  38 #endif
  39
  40 #ifdef CONFIG_SDCARD
  41 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  42 #define CFG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
  43 #define CFG_SYS_MMC_U_BOOT_DST      (0x00200000)
  44 #define CFG_SYS_MMC_U_BOOT_START    (0x00200000)
  45 #define CFG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
  46 #endif
  47
  48 #endif /* CONFIG_RAMBOOT_PBL */
  49
  50 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  51 /* Set 1M boot space */
  52 #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
  53 #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  54                 (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  55 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  56 #endif
  57
  58 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  59 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  60 #endif
  61
  62 /*
  63  * These can be toggled for performance analysis, otherwise use default.
  64  */
  65 #ifdef CONFIG_DDR_ECC
  66 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  67 #endif
  68
  69 /*
  70  * Config the L3 Cache as L3 SRAM
  71  */
  72 #define CFG_SYS_INIT_L3_ADDR            0xFFFC0000
  73 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
  74
  75 #define CFG_SYS_DCSRBAR 0xf0000000
  76 #define CFG_SYS_DCSRBAR_PHYS    0xf00000000ull
  77
  78 /*
  79  * DDR Setup
  80  */
  81 #define CFG_SYS_DDR_SDRAM_BASE  0x00000000
  82 #define CFG_SYS_SDRAM_BASE              CFG_SYS_DDR_SDRAM_BASE
  83 #define CFG_SYS_SDRAM_SIZE      2048    /* for fixed parameter use */
  84 #define SPD_EEPROM_ADDRESS1     0x51
  85 #define SPD_EEPROM_ADDRESS2     0x52
  86 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  87 #define CTRL_INTLV_PREFERED     cacheline
  88
  89 /*
  90  * IFC Definitions
  91  */
  92 #define CFG_SYS_FLASH_BASE              0xe8000000
  93 #define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
  94 #define CFG_SYS_NOR0_CSPR_EXT   (0xf)
  95 #define CFG_SYS_NOR0_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
  96                                 CSPR_PORT_SIZE_16 | \
  97                                 CSPR_MSEL_NOR | \
  98                                 CSPR_V)
  99 #define CFG_SYS_NOR_AMASK       IFC_AMASK(128*1024*1024)
 100
 101 /* NOR Flash Timing Params */
 102 #define CFG_SYS_NOR_CSOR        CSOR_NAND_TRHZ_80
 103
 104 #define CFG_SYS_NOR_FTIM0       (FTIM0_NOR_TACSE(0x4) | \
 105                                 FTIM0_NOR_TEADC(0x5) | \
 106                                 FTIM0_NOR_TEAHC(0x5))
 107 #define CFG_SYS_NOR_FTIM1       (FTIM1_NOR_TACO(0x35) | \
 108                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 109                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 110 #define CFG_SYS_NOR_FTIM2       (FTIM2_NOR_TCS(0x4) | \
 111                                 FTIM2_NOR_TCH(0x4) | \
 112                                 FTIM2_NOR_TWPH(0x0E) | \
 113                                 FTIM2_NOR_TWP(0x1c))
 114 #define CFG_SYS_NOR_FTIM3       0x0
 115
 116 #define CFG_SYS_FLASH_BANKS_LIST        {CFG_SYS_FLASH_BASE_PHYS }
 117
 118 /* CPLD on IFC */
 119 #define CFG_SYS_CPLD_BASE       0xffdf0000
 120 #define CFG_SYS_CPLD_BASE_PHYS  (0xf00000000ull | CFG_SYS_CPLD_BASE)
 121 #define CFG_SYS_CSPR2_EXT       (0xf)
 122 #define CFG_SYS_CSPR2   (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE) \
 123                                 | CSPR_PORT_SIZE_8 \
 124                                 | CSPR_MSEL_GPCM \
 125                                 | CSPR_V)
 126 #define CFG_SYS_AMASK2  IFC_AMASK(64*1024)
 127 #define CFG_SYS_CSOR2   0x0
 128
 129 /* CPLD Timing parameters for IFC CS2 */
 130 #define CFG_SYS_CS2_FTIM0               (FTIM0_GPCM_TACSE(0x0e) | \
 131                                         FTIM0_GPCM_TEADC(0x0e) | \
 132                                         FTIM0_GPCM_TEAHC(0x0e))
 133 #define CFG_SYS_CS2_FTIM1               (FTIM1_GPCM_TACO(0x0e) | \
 134                                         FTIM1_GPCM_TRAD(0x1f))
 135 #define CFG_SYS_CS2_FTIM2               (FTIM2_GPCM_TCS(0x0e) | \
 136                                         FTIM2_GPCM_TCH(0x8) | \
 137                                         FTIM2_GPCM_TWP(0x1f))
 138 #define CFG_SYS_CS2_FTIM3               0x0
 139
 140 /* NAND Flash on IFC */
 141 #define CFG_SYS_NAND_BASE               0xff800000
 142 #define CFG_SYS_NAND_BASE_PHYS  (0xf00000000ull | CFG_SYS_NAND_BASE)
 143
 144 #define CFG_SYS_NAND_CSPR_EXT   (0xf)
 145 #define CFG_SYS_NAND_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 146                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 147                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 148                                 | CSPR_V)
 149 #define CFG_SYS_NAND_AMASK      IFC_AMASK(64*1024)
 150
 151 #define CFG_SYS_NAND_CSOR       (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 152                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 153                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 154                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 155                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 156                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 157                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 158
 159 /* ONFI NAND Flash mode0 Timing Params */
 160 #define CFG_SYS_NAND_FTIM0              (FTIM0_NAND_TCCST(0x07) | \
 161                                         FTIM0_NAND_TWP(0x18)    | \
 162                                         FTIM0_NAND_TWCHT(0x07)  | \
 163                                         FTIM0_NAND_TWH(0x0a))
 164 #define CFG_SYS_NAND_FTIM1              (FTIM1_NAND_TADLE(0x32) | \
 165                                         FTIM1_NAND_TWBE(0x39)   | \
 166                                         FTIM1_NAND_TRR(0x0e)    | \
 167                                         FTIM1_NAND_TRP(0x18))
 168 #define CFG_SYS_NAND_FTIM2              (FTIM2_NAND_TRAD(0x0f)  | \
 169                                         FTIM2_NAND_TREH(0x0a)   | \
 170                                         FTIM2_NAND_TWHRE(0x1e))
 171 #define CFG_SYS_NAND_FTIM3              0x0
 172
 173 #define CFG_SYS_NAND_BASE_LIST  { CFG_SYS_NAND_BASE }
 174
 175 #if defined(CONFIG_MTD_RAW_NAND)
 176 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NAND_CSPR_EXT
 177 #define CFG_SYS_CSPR0           CFG_SYS_NAND_CSPR
 178 #define CFG_SYS_AMASK0          CFG_SYS_NAND_AMASK
 179 #define CFG_SYS_CSOR0           CFG_SYS_NAND_CSOR
 180 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NAND_FTIM0
 181 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NAND_FTIM1
 182 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NAND_FTIM2
 183 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NAND_FTIM3
 184 #define CFG_SYS_CSPR1_EXT               CFG_SYS_NOR0_CSPR_EXT
 185 #define CFG_SYS_CSPR1           CFG_SYS_NOR0_CSPR
 186 #define CFG_SYS_AMASK1          CFG_SYS_NOR_AMASK
 187 #define CFG_SYS_CSOR1           CFG_SYS_NOR_CSOR
 188 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NOR_FTIM0
 189 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NOR_FTIM1
 190 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NOR_FTIM2
 191 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NOR_FTIM3
 192 #else
 193 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NOR0_CSPR_EXT
 194 #define CFG_SYS_CSPR0           CFG_SYS_NOR0_CSPR
 195 #define CFG_SYS_AMASK0          CFG_SYS_NOR_AMASK
 196 #define CFG_SYS_CSOR0           CFG_SYS_NOR_CSOR
 197 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NOR_FTIM0
 198 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NOR_FTIM1
 199 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NOR_FTIM2
 200 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NOR_FTIM3
 201 #define CFG_SYS_CSPR1_EXT               CFG_SYS_NAND_CSPR_EXT
 202 #define CFG_SYS_CSPR1           CFG_SYS_NAND_CSPR
 203 #define CFG_SYS_AMASK1          CFG_SYS_NAND_AMASK
 204 #define CFG_SYS_CSOR1           CFG_SYS_NAND_CSOR
 205 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NAND_FTIM0
 206 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NAND_FTIM1
 207 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NAND_FTIM2
 208 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NAND_FTIM3
 209 #endif
 210
 211 /* define to use L1 as initial stack */
 212 #define CFG_SYS_INIT_RAM_ADDR   0xfdd00000 /* Initial L1 address */
 213 #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 214 #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW  0xfe03c000
 215 /* The assembler doesn't like typecast */
 216 #define CFG_SYS_INIT_RAM_ADDR_PHYS \
 217                         ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 218                         CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 219 #define CFG_SYS_INIT_RAM_SIZE   0x00004000
 220 #define CFG_SYS_INIT_SP_OFFSET  (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 221
 222 /*
 223  * Serial Port
 224  */
 225 #define CFG_SYS_NS16550_CLK             (get_bus_freq(0)/2)
 226 #define CFG_SYS_BAUDRATE_TABLE  \
 227         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 228 #define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
 229 #define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600)
 230 #define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500)
 231 #define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
 232
 233 /*
 234  * I2C
 235  */
 236
 237 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 238 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 239 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 240 #define I2C_MUX_CH_DEFAULT      0x8
 241
 242 #define I2C_MUX_CH_VOL_MONITOR  0xa
 243
 244 /* The lowest and highest voltage allowed for T208xRDB */
 245 #define VDD_MV_MIN                      819
 246 #define VDD_MV_MAX                      1212
 247
 248 /*
 249  * RapidIO
 250  */
 251 #define CFG_SYS_SRIO1_MEM_VIRT  0xa0000000
 252 #define CFG_SYS_SRIO1_MEM_PHYS  0xc20000000ull
 253 #define CFG_SYS_SRIO1_MEM_SIZE  0x10000000 /* 256M */
 254 #define CFG_SYS_SRIO2_MEM_VIRT  0xb0000000
 255 #define CFG_SYS_SRIO2_MEM_PHYS  0xc30000000ull
 256 #define CFG_SYS_SRIO2_MEM_SIZE  0x10000000 /* 256M */
 257 /*
 258  * for slave u-boot IMAGE instored in master memory space,
 259  * PHYS must be aligned based on the SIZE
 260  */
 261 #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 262 #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 263 #define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 264 #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 265 /*
 266  * for slave UCODE and ENV instored in master memory space,
 267  * PHYS must be aligned based on the SIZE
 268  */
 269 #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 270 #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 271 #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000    /* 256K */
 272
 273 /* slave core release by master*/
 274 #define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 275 #define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 276
 277 /*
 278  * SRIO_PCIE_BOOT - SLAVE
 279  */
 280 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 281 #define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 282 #define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 283                 (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 284 #endif
 285
 286 /*
 287  * eSPI - Enhanced SPI
 288  */
 289
 290 /*
 291  * General PCI
 292  * Memory space is mapped 1-1, but I/O space must start from 0.
 293  */
 294 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 295 #define CFG_SYS_PCIE1_MEM_VIRT  0x80000000
 296 #define CFG_SYS_PCIE1_MEM_PHYS  0xc00000000ull
 297 #define CFG_SYS_PCIE1_IO_VIRT   0xf8000000
 298 #define CFG_SYS_PCIE1_IO_PHYS   0xff8000000ull
 299
 300 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 301 #define CFG_SYS_PCIE2_MEM_VIRT  0xa0000000
 302 #define CFG_SYS_PCIE2_MEM_PHYS  0xc20000000ull
 303 #define CFG_SYS_PCIE2_IO_VIRT   0xf8010000
 304 #define CFG_SYS_PCIE2_IO_PHYS   0xff8010000ull
 305
 306 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 307 #define CFG_SYS_PCIE3_MEM_VIRT  0xb0000000
 308 #define CFG_SYS_PCIE3_MEM_PHYS  0xc30000000ull
 309
 310 /* controller 4, Base address 203000 */
 311 #define CFG_SYS_PCIE4_MEM_VIRT       0xc0000000
 312 #define CFG_SYS_PCIE4_MEM_PHYS  0xc40000000ull
 313
 314 /* Qman/Bman */
 315 #ifndef CONFIG_NOBQFMAN
 316 #define CFG_SYS_BMAN_NUM_PORTALS        18
 317 #define CFG_SYS_BMAN_MEM_BASE   0xf4000000
 318 #define CFG_SYS_BMAN_MEM_PHYS   0xff4000000ull
 319 #define CFG_SYS_BMAN_MEM_SIZE   0x02000000
 320 #define CFG_SYS_BMAN_SP_CENA_SIZE    0x4000
 321 #define CFG_SYS_BMAN_SP_CINH_SIZE    0x1000
 322 #define CFG_SYS_BMAN_CENA_BASE       CFG_SYS_BMAN_MEM_BASE
 323 #define CFG_SYS_BMAN_CENA_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
 324 #define CFG_SYS_BMAN_CINH_BASE       (CFG_SYS_BMAN_MEM_BASE + \
 325                                         CFG_SYS_BMAN_CENA_SIZE)
 326 #define CFG_SYS_BMAN_CINH_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
 327 #define CFG_SYS_BMAN_SWP_ISDR_REG       0xE08
 328 #define CFG_SYS_QMAN_NUM_PORTALS        18
 329 #define CFG_SYS_QMAN_MEM_BASE   0xf6000000
 330 #define CFG_SYS_QMAN_MEM_PHYS   0xff6000000ull
 331 #define CFG_SYS_QMAN_MEM_SIZE   0x02000000
 332 #define CFG_SYS_QMAN_SP_CINH_SIZE    0x1000
 333 #define CFG_SYS_QMAN_CENA_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
 334 #define CFG_SYS_QMAN_CINH_BASE       (CFG_SYS_QMAN_MEM_BASE + \
 335                                         CFG_SYS_QMAN_CENA_SIZE)
 336 #define CFG_SYS_QMAN_CINH_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
 337 #define CFG_SYS_QMAN_SWP_ISDR_REG       0xE08
 338 #endif /* CONFIG_NOBQFMAN */
 339
 340 #ifdef CONFIG_SYS_DPAA_FMAN
 341 #define RGMII_PHY1_ADDR         0x01  /* RealTek RTL8211E */
 342 #define RGMII_PHY2_ADDR         0x02
 343 #define CORTINA_PHY_ADDR1       0x0c  /* Cortina CS4315 */
 344 #define CORTINA_PHY_ADDR2       0x0d
 345 /* Aquantia AQ1202 10G Base-T used by board revisions up to C */
 346 #define FM1_10GEC3_PHY_ADDR     0x00
 347 #define FM1_10GEC4_PHY_ADDR     0x01
 348 /* Aquantia AQR113C 10G Base-T used by board revisions D and up */
 349 #define AQR113C_PHY_ADDR1       0x00
 350 #define AQR113C_PHY_ADDR2       0x08
 351 #endif
 352
 353 /*
 354  * USB
 355  */
 356
 357 /*
 358  * SDHC
 359  */
 360 #ifdef CONFIG_MMC
 361 #define CFG_SYS_FSL_ESDHC_ADDR  CFG_SYS_MPC85xx_ESDHC_ADDR
 362 #endif
 363
 364 /*
 365  * Dynamic MTD Partition support with mtdparts
 366  */
 367
 368 /*
 369  * Environment
 370  */
 371
 372 /*
 373  * Miscellaneous configurable options
 374  */
 375
 376 /*
 377  * For booting Linux, the board info and command line data
 378  * have to be in the first 64 MB of memory, since this is
 379  * the maximum mapped by the Linux kernel during initialization.
 380  */
 381 #define CFG_SYS_BOOTMAPSZ       (64 << 20)      /* Initial map for Linux*/
 382
 383 /*
 384  * Environment Configuration
 385  */
 386
 387 #define __USB_PHY_TYPE          utmi
 388
 389 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 390         "hwconfig=fsl_ddr:"                                     \
 391         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 392         "bank_intlv=auto;"                                      \
 393         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 394         "netdev=eth0\0"                                         \
 395         "uboot=" CONFIG_UBOOTPATH "\0"          \
 396         "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
 397         "tftpflash=tftpboot $loadaddr $uboot && "               \
 398         "protect off $ubootaddr +$filesize && "                 \
 399         "erase $ubootaddr +$filesize && "                       \
 400         "cp.b $loadaddr $ubootaddr $filesize && "               \
 401         "protect on $ubootaddr +$filesize && "                  \
 402         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 403         "consoledev=ttyS0\0"                                    \
 404         "ramdiskaddr=2000000\0"                                 \
 405         "ramdiskfile=t2080rdb/ramdisk.uboot\0"                  \
 406         "fdtaddr=1e00000\0"                                     \
 407         "fdtfile=t2080rdb/t2080rdb.dtb\0"                       \
 408         "bdev=sda3\0"
 409
 410 /*
 411  * For emulation this causes u-boot to jump to the start of the
 412  * proof point app code automatically
 413  */
 414 #define PROOF_POINTS                            \
 415         "setenv bootargs root=/dev/$bdev rw "           \
 416         "console=$consoledev,$baudrate $othbootargs;"   \
 417         "cpu 1 release 0x29000000 - - -;"               \
 418         "cpu 2 release 0x29000000 - - -;"               \
 419         "cpu 3 release 0x29000000 - - -;"               \
 420         "cpu 4 release 0x29000000 - - -;"               \
 421         "cpu 5 release 0x29000000 - - -;"               \
 422         "cpu 6 release 0x29000000 - - -;"               \
 423         "cpu 7 release 0x29000000 - - -;"               \
 424         "go 0x29000000"
 425
 426 #define HVBOOT                          \
 427         "setenv bootargs config-addr=0x60000000; "      \
 428         "bootm 0x01000000 - 0x00f00000"
 429
 430 #define ALU                             \
 431         "setenv bootargs root=/dev/$bdev rw "           \
 432         "console=$consoledev,$baudrate $othbootargs;"   \
 433         "cpu 1 release 0x01000000 - - -;"               \
 434         "cpu 2 release 0x01000000 - - -;"               \
 435         "cpu 3 release 0x01000000 - - -;"               \
 436         "cpu 4 release 0x01000000 - - -;"               \
 437         "cpu 5 release 0x01000000 - - -;"               \
 438         "cpu 6 release 0x01000000 - - -;"               \
 439         "cpu 7 release 0x01000000 - - -;"               \
 440         "go 0x01000000"
 441
 442 #include <asm/fsl_secure_boot.h>
 443
 444 #endif  /* __T2080RDB_H */