1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
8 * T2080 RDB/PCIe board configuration file
14 #include <linux/stringify.h>
16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
18 /* High Level Configuration Options */
20 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
22 #ifdef CONFIG_RAMBOOT_PBL
23 #define RESET_VECTOR_OFFSET 0x27FFC
24 #define BOOT_PAGE_OFFSET 0x27000
26 #ifdef CONFIG_MTD_RAW_NAND
27 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
28 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
29 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
32 #ifdef CONFIG_SPIFLASH
33 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
34 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
35 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
36 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
37 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
41 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
42 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
43 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
44 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
45 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
48 #endif /* CONFIG_RAMBOOT_PBL */
50 #define CONFIG_SRIO_PCIE_BOOT_MASTER
51 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
52 /* Set 1M boot space */
53 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
54 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
55 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
56 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
59 #ifndef CONFIG_RESET_VECTOR_ADDRESS
60 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
64 * These can be toggled for performance analysis, otherwise use default.
67 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
71 * Config the L3 Cache as L3 SRAM
73 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
74 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
76 #define CONFIG_SYS_DCSRBAR 0xf0000000
77 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
82 #define CONFIG_VERY_BIG_RAM
83 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
84 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
85 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
86 #define SPD_EEPROM_ADDRESS1 0x51
87 #define SPD_EEPROM_ADDRESS2 0x52
88 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
89 #define CTRL_INTLV_PREFERED cacheline
94 #define CONFIG_SYS_FLASH_BASE 0xe8000000
95 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
96 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
97 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
101 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
103 /* NOR Flash Timing Params */
104 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
106 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
107 FTIM0_NOR_TEADC(0x5) | \
108 FTIM0_NOR_TEAHC(0x5))
109 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
110 FTIM1_NOR_TRAD_NOR(0x1A) |\
111 FTIM1_NOR_TSEQRAD_NOR(0x13))
112 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
113 FTIM2_NOR_TCH(0x4) | \
114 FTIM2_NOR_TWPH(0x0E) | \
116 #define CONFIG_SYS_NOR_FTIM3 0x0
118 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
120 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS }
123 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
124 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
125 #define CONFIG_SYS_CSPR2_EXT (0xf)
126 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
130 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
131 #define CONFIG_SYS_CSOR2 0x0
133 /* CPLD Timing parameters for IFC CS2 */
134 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
135 FTIM0_GPCM_TEADC(0x0e) | \
136 FTIM0_GPCM_TEAHC(0x0e))
137 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
138 FTIM1_GPCM_TRAD(0x1f))
139 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
140 FTIM2_GPCM_TCH(0x8) | \
141 FTIM2_GPCM_TWP(0x1f))
142 #define CONFIG_SYS_CS2_FTIM3 0x0
144 /* NAND Flash on IFC */
145 #define CONFIG_SYS_NAND_BASE 0xff800000
146 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
148 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
149 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
150 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
151 | CSPR_MSEL_NAND /* MSEL = NAND */ \
153 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
155 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
156 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
157 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
158 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
159 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
160 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
161 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
163 /* ONFI NAND Flash mode0 Timing Params */
164 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
165 FTIM0_NAND_TWP(0x18) | \
166 FTIM0_NAND_TWCHT(0x07) | \
167 FTIM0_NAND_TWH(0x0a))
168 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
169 FTIM1_NAND_TWBE(0x39) | \
170 FTIM1_NAND_TRR(0x0e) | \
171 FTIM1_NAND_TRP(0x18))
172 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
173 FTIM2_NAND_TREH(0x0a) | \
174 FTIM2_NAND_TWHRE(0x1e))
175 #define CONFIG_SYS_NAND_FTIM3 0x0
177 #define CONFIG_SYS_NAND_DDR_LAW 11
178 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
180 #if defined(CONFIG_MTD_RAW_NAND)
181 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
182 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
183 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
184 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
185 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
186 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
187 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
188 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
189 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
190 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
191 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
192 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
193 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
194 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
195 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
196 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
198 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
199 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
200 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
201 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
202 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
203 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
204 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
205 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
206 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
207 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
208 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
209 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
210 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
211 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
212 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
213 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
216 #define CONFIG_HWCONFIG
218 /* define to use L1 as initial stack */
219 #define CONFIG_L1_INIT_RAM
220 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
221 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
222 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
223 /* The assembler doesn't like typecast */
224 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
225 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
226 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
227 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
228 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
233 #define CONFIG_SYS_NS16550_SERIAL
234 #define CONFIG_SYS_NS16550_REG_SIZE 1
235 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
236 #define CONFIG_SYS_BAUDRATE_TABLE \
237 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
238 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
239 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
240 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
241 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
247 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
248 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
249 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
250 #define I2C_MUX_CH_DEFAULT 0x8
252 #define I2C_MUX_CH_VOL_MONITOR 0xa
254 /* The lowest and highest voltage allowed for T208xRDB */
255 #define VDD_MV_MIN 819
256 #define VDD_MV_MAX 1212
261 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
262 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
263 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
264 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
265 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
266 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
268 * for slave u-boot IMAGE instored in master memory space,
269 * PHYS must be aligned based on the SIZE
271 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
272 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
273 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
274 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
276 * for slave UCODE and ENV instored in master memory space,
277 * PHYS must be aligned based on the SIZE
279 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
280 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
281 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
283 /* slave core release by master*/
284 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
285 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
288 * SRIO_PCIE_BOOT - SLAVE
290 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
291 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
292 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
293 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
297 * eSPI - Enhanced SPI
302 * Memory space is mapped 1-1, but I/O space must start from 0.
304 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
305 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
306 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
307 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
308 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
310 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
311 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
312 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
313 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
314 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
316 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
317 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
318 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
319 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
320 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
322 /* controller 4, Base address 203000 */
323 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
324 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
325 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
328 #ifndef CONFIG_NOBQFMAN
329 #define CONFIG_SYS_BMAN_NUM_PORTALS 18
330 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
331 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
332 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
333 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
334 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
335 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
336 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
337 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
338 CONFIG_SYS_BMAN_CENA_SIZE)
339 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
340 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
341 #define CONFIG_SYS_QMAN_NUM_PORTALS 18
342 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
343 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
344 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
345 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
346 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
347 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
348 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
349 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
350 CONFIG_SYS_QMAN_CENA_SIZE)
351 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
352 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
354 #define CONFIG_SYS_DPAA_FMAN
355 #define CONFIG_SYS_DPAA_PME
356 #define CONFIG_SYS_PMAN
357 #define CONFIG_SYS_DPAA_DCE
358 #define CONFIG_SYS_DPAA_RMAN /* RMan */
359 #endif /* CONFIG_NOBQFMAN */
361 #ifdef CONFIG_SYS_DPAA_FMAN
362 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
363 #define RGMII_PHY2_ADDR 0x02
364 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */
365 #define CORTINA_PHY_ADDR2 0x0d
366 /* Aquantia AQ1202 10G Base-T used by board revisions up to C */
367 #define FM1_10GEC3_PHY_ADDR 0x00
368 #define FM1_10GEC4_PHY_ADDR 0x01
369 /* Aquantia AQR113C 10G Base-T used by board revisions D and up */
370 #define AQR113C_PHY_ADDR1 0x00
371 #define AQR113C_PHY_ADDR2 0x08
382 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
386 * Dynamic MTD Partition support with mtdparts
394 * Miscellaneous configurable options
398 * For booting Linux, the board info and command line data
399 * have to be in the first 64 MB of memory, since this is
400 * the maximum mapped by the Linux kernel during initialization.
402 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
405 * Environment Configuration
407 #define CONFIG_ROOTPATH "/opt/nfsroot"
408 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
410 #define __USB_PHY_TYPE utmi
412 #define CONFIG_EXTRA_ENV_SETTINGS \
413 "hwconfig=fsl_ddr:" \
414 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
416 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
418 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
419 "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
420 "tftpflash=tftpboot $loadaddr $uboot && " \
421 "protect off $ubootaddr +$filesize && " \
422 "erase $ubootaddr +$filesize && " \
423 "cp.b $loadaddr $ubootaddr $filesize && " \
424 "protect on $ubootaddr +$filesize && " \
425 "cmp.b $loadaddr $ubootaddr $filesize\0" \
426 "consoledev=ttyS0\0" \
427 "ramdiskaddr=2000000\0" \
428 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \
429 "fdtaddr=1e00000\0" \
430 "fdtfile=t2080rdb/t2080rdb.dtb\0" \
434 * For emulation this causes u-boot to jump to the start of the
435 * proof point app code automatically
437 #define PROOF_POINTS \
438 "setenv bootargs root=/dev/$bdev rw " \
439 "console=$consoledev,$baudrate $othbootargs;" \
440 "cpu 1 release 0x29000000 - - -;" \
441 "cpu 2 release 0x29000000 - - -;" \
442 "cpu 3 release 0x29000000 - - -;" \
443 "cpu 4 release 0x29000000 - - -;" \
444 "cpu 5 release 0x29000000 - - -;" \
445 "cpu 6 release 0x29000000 - - -;" \
446 "cpu 7 release 0x29000000 - - -;" \
450 "setenv bootargs config-addr=0x60000000; " \
451 "bootm 0x01000000 - 0x00f00000"
454 "setenv bootargs root=/dev/$bdev rw " \
455 "console=$consoledev,$baudrate $othbootargs;" \
456 "cpu 1 release 0x01000000 - - -;" \
457 "cpu 2 release 0x01000000 - - -;" \
458 "cpu 3 release 0x01000000 - - -;" \
459 "cpu 4 release 0x01000000 - - -;" \
460 "cpu 5 release 0x01000000 - - -;" \
461 "cpu 6 release 0x01000000 - - -;" \
462 "cpu 7 release 0x01000000 - - -;" \
465 #include <asm/fsl_secure_boot.h>
467 #endif /* __T2080RDB_H */