1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
8 * T2080 RDB/PCIe board configuration file
14 #include <linux/stringify.h>
16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
17 #define CONFIG_FSL_SATA_V2
19 /* High Level Configuration Options */
20 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
21 #define CONFIG_ENABLE_36BIT_PHYS
23 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
24 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
25 #define CONFIG_ENV_OVERWRITE
27 #ifdef CONFIG_RAMBOOT_PBL
28 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
30 #define CONFIG_SPL_FLUSH_IMAGE
31 #define CONFIG_SPL_PAD_TO 0x40000
32 #define CONFIG_SPL_MAX_SIZE 0x28000
33 #define RESET_VECTOR_OFFSET 0x27FFC
34 #define BOOT_PAGE_OFFSET 0x27000
35 #ifdef CONFIG_SPL_BUILD
36 #define CONFIG_SPL_SKIP_RELOCATE
37 #define CONFIG_SPL_COMMON_INIT_DDR
38 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
41 #ifdef CONFIG_MTD_RAW_NAND
42 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
43 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
44 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
45 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
46 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg
49 #ifdef CONFIG_SPIFLASH
50 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
51 #define CONFIG_SPL_SPI_FLASH_MINIMAL
52 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
53 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
54 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
55 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
56 #ifndef CONFIG_SPL_BUILD
57 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
59 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg
63 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
64 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
65 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
66 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
67 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
68 #ifndef CONFIG_SPL_BUILD
69 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
71 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg
74 #endif /* CONFIG_RAMBOOT_PBL */
76 #define CONFIG_SRIO_PCIE_BOOT_MASTER
77 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
78 /* Set 1M boot space */
79 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
80 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
81 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
82 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
85 #ifndef CONFIG_RESET_VECTOR_ADDRESS
86 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
90 * These can be toggled for performance analysis, otherwise use default.
92 #define CONFIG_SYS_CACHE_STASHING
93 #define CONFIG_BTB /* toggle branch predition */
94 #define CONFIG_DDR_ECC
96 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
97 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
100 #if defined(CONFIG_SPIFLASH)
101 #elif defined(CONFIG_SDCARD)
102 #define CONFIG_SYS_MMC_ENV_DEV 0
106 unsigned long get_board_sys_clk(void);
107 unsigned long get_board_ddr_clk(void);
110 #define CONFIG_SYS_CLK_FREQ 66660000
111 #define CONFIG_DDR_CLK_FREQ 133330000
114 * Config the L3 Cache as L3 SRAM
116 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
117 #define CONFIG_SYS_L3_SIZE (512 << 10)
118 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
119 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
120 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
121 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
122 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
124 #define CONFIG_SYS_DCSRBAR 0xf0000000
125 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
128 #define CONFIG_ID_EEPROM
129 #define CONFIG_SYS_I2C_EEPROM_NXID
130 #define CONFIG_SYS_EEPROM_BUS_NUM 0
131 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
132 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
137 #define CONFIG_VERY_BIG_RAM
138 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
139 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
140 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
141 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
142 #define CONFIG_DDR_SPD
143 #define CONFIG_SYS_SPD_BUS_NUM 0
144 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
145 #define SPD_EEPROM_ADDRESS1 0x51
146 #define SPD_EEPROM_ADDRESS2 0x52
147 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
148 #define CTRL_INTLV_PREFERED cacheline
153 #define CONFIG_SYS_FLASH_BASE 0xe8000000
154 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
155 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
156 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
157 CSPR_PORT_SIZE_16 | \
160 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
162 /* NOR Flash Timing Params */
163 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
165 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
166 FTIM0_NOR_TEADC(0x5) | \
167 FTIM0_NOR_TEAHC(0x5))
168 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
169 FTIM1_NOR_TRAD_NOR(0x1A) |\
170 FTIM1_NOR_TSEQRAD_NOR(0x13))
171 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
172 FTIM2_NOR_TCH(0x4) | \
173 FTIM2_NOR_TWPH(0x0E) | \
175 #define CONFIG_SYS_NOR_FTIM3 0x0
177 #define CONFIG_SYS_FLASH_QUIET_TEST
178 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
180 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
181 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
182 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
183 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
184 #define CONFIG_SYS_FLASH_EMPTY_INFO
185 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS }
188 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
189 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
190 #define CONFIG_SYS_CSPR2_EXT (0xf)
191 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
195 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
196 #define CONFIG_SYS_CSOR2 0x0
198 /* CPLD Timing parameters for IFC CS2 */
199 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
200 FTIM0_GPCM_TEADC(0x0e) | \
201 FTIM0_GPCM_TEAHC(0x0e))
202 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
203 FTIM1_GPCM_TRAD(0x1f))
204 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
205 FTIM2_GPCM_TCH(0x8) | \
206 FTIM2_GPCM_TWP(0x1f))
207 #define CONFIG_SYS_CS2_FTIM3 0x0
209 /* NAND Flash on IFC */
210 #define CONFIG_NAND_FSL_IFC
211 #define CONFIG_SYS_NAND_BASE 0xff800000
212 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
214 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
215 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
216 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
217 | CSPR_MSEL_NAND /* MSEL = NAND */ \
219 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
221 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
222 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
223 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
224 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
225 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
226 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
227 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
229 #define CONFIG_SYS_NAND_ONFI_DETECTION
231 /* ONFI NAND Flash mode0 Timing Params */
232 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
233 FTIM0_NAND_TWP(0x18) | \
234 FTIM0_NAND_TWCHT(0x07) | \
235 FTIM0_NAND_TWH(0x0a))
236 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
237 FTIM1_NAND_TWBE(0x39) | \
238 FTIM1_NAND_TRR(0x0e) | \
239 FTIM1_NAND_TRP(0x18))
240 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
241 FTIM2_NAND_TREH(0x0a) | \
242 FTIM2_NAND_TWHRE(0x1e))
243 #define CONFIG_SYS_NAND_FTIM3 0x0
245 #define CONFIG_SYS_NAND_DDR_LAW 11
246 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
247 #define CONFIG_SYS_MAX_NAND_DEVICE 1
248 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
250 #if defined(CONFIG_MTD_RAW_NAND)
251 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
252 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
253 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
254 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
255 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
256 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
257 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
258 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
259 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
260 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
261 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
262 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
263 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
264 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
265 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
266 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
268 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
269 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
270 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
271 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
272 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
273 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
274 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
275 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
276 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
277 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
278 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
279 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
280 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
281 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
282 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
283 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
286 #if defined(CONFIG_RAMBOOT_PBL)
287 #define CONFIG_SYS_RAMBOOT
290 #ifdef CONFIG_SPL_BUILD
291 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
293 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
296 #define CONFIG_HWCONFIG
298 /* define to use L1 as initial stack */
299 #define CONFIG_L1_INIT_RAM
300 #define CONFIG_SYS_INIT_RAM_LOCK
301 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
302 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
303 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
304 /* The assembler doesn't like typecast */
305 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
306 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
307 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
308 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
309 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
310 GENERATED_GBL_DATA_SIZE)
311 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
312 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
313 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
318 #define CONFIG_SYS_NS16550_SERIAL
319 #define CONFIG_SYS_NS16550_REG_SIZE 1
320 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
321 #define CONFIG_SYS_BAUDRATE_TABLE \
322 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
323 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
324 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
325 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
326 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
331 #ifndef CONFIG_DM_I2C
332 #define CONFIG_SYS_I2C
333 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
334 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
335 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
336 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
337 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
338 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
339 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
340 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
341 #define CONFIG_SYS_FSL_I2C_SPEED 100000
342 #define CONFIG_SYS_FSL_I2C2_SPEED 100000
343 #define CONFIG_SYS_FSL_I2C3_SPEED 100000
344 #define CONFIG_SYS_FSL_I2C4_SPEED 100000
346 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
347 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
350 #define CONFIG_SYS_I2C_FSL
352 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
353 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
354 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
355 #define I2C_MUX_CH_DEFAULT 0x8
357 #define I2C_MUX_CH_VOL_MONITOR 0xa
359 #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv"
360 #ifndef CONFIG_SPL_BUILD
363 #define CONFIG_VOL_MONITOR_IR36021_SET
364 #define CONFIG_VOL_MONITOR_IR36021_READ
365 /* The lowest and highest voltage allowed for T208xRDB */
366 #define VDD_MV_MIN 819
367 #define VDD_MV_MAX 1212
372 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
373 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
374 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
375 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
376 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
377 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
379 * for slave u-boot IMAGE instored in master memory space,
380 * PHYS must be aligned based on the SIZE
382 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
383 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
384 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
385 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
387 * for slave UCODE and ENV instored in master memory space,
388 * PHYS must be aligned based on the SIZE
390 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
391 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
392 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
394 /* slave core release by master*/
395 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
396 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
399 * SRIO_PCIE_BOOT - SLAVE
401 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
402 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
403 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
404 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
408 * eSPI - Enhanced SPI
413 * Memory space is mapped 1-1, but I/O space must start from 0.
415 #define CONFIG_PCIE1 /* PCIE controller 1 */
416 #define CONFIG_PCIE2 /* PCIE controller 2 */
417 #define CONFIG_PCIE3 /* PCIE controller 3 */
418 #define CONFIG_PCIE4 /* PCIE controller 4 */
419 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
420 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
421 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
422 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
423 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
424 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
426 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
427 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
428 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
429 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
430 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
432 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
433 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
434 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
435 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
436 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
438 /* controller 4, Base address 203000 */
439 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
440 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
441 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
444 #if !defined(CONFIG_DM_PCI)
445 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
446 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
447 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
448 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
449 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
450 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
451 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
452 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
453 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
454 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
455 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
456 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
457 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
458 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
459 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
460 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
461 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
462 #define CONFIG_PCI_INDIRECT_BRIDGE
464 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
468 #ifndef CONFIG_NOBQFMAN
469 #define CONFIG_SYS_BMAN_NUM_PORTALS 18
470 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
471 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
472 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
473 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
474 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
475 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
476 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
477 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
478 CONFIG_SYS_BMAN_CENA_SIZE)
479 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
480 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
481 #define CONFIG_SYS_QMAN_NUM_PORTALS 18
482 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
483 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
484 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
485 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
486 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
487 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
488 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
489 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
490 CONFIG_SYS_QMAN_CENA_SIZE)
491 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
492 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
494 #define CONFIG_SYS_DPAA_FMAN
495 #define CONFIG_SYS_DPAA_PME
496 #define CONFIG_SYS_PMAN
497 #define CONFIG_SYS_DPAA_DCE
498 #define CONFIG_SYS_DPAA_RMAN /* RMan */
499 #define CONFIG_SYS_INTERLAKEN
501 /* Default address of microcode for the Linux Fman driver */
502 #if defined(CONFIG_SPIFLASH)
504 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
505 * env, so we got 0x110000.
507 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
508 #define CONFIG_CORTINA_FW_ADDR 0x120000
510 #elif defined(CONFIG_SDCARD)
512 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
513 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
514 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
516 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
517 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0)
519 #elif defined(CONFIG_MTD_RAW_NAND)
520 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
521 #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
522 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
524 * Slave has no ucode locally, it can fetch this from remote. When implementing
525 * in two corenet boards, slave's ucode could be stored in master's memory
526 * space, the address can be mapped from slave TLB->slave LAW->
527 * slave SRIO or PCIE outbound window->master inbound window->
528 * master LAW->the ucode address in master's memory space.
530 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
531 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000
533 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
534 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000
536 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
537 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
538 #endif /* CONFIG_NOBQFMAN */
540 #ifdef CONFIG_SYS_DPAA_FMAN
541 #define CONFIG_CORTINA_FW_LENGTH 0x40000
542 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
543 #define RGMII_PHY2_ADDR 0x02
544 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */
545 #define CORTINA_PHY_ADDR2 0x0d
546 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */
547 #define FM1_10GEC4_PHY_ADDR 0x01
550 #ifdef CONFIG_FMAN_ENET
551 #define CONFIG_ETHPRIME "FM1@DTSEC3"
557 #ifdef CONFIG_FSL_SATA_V2
558 #define CONFIG_SYS_SATA_MAX_DEVICE 2
560 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
561 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
563 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
564 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
571 #ifdef CONFIG_USB_EHCI_HCD
572 #define CONFIG_USB_EHCI_FSL
573 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
574 #define CONFIG_HAS_FSL_DR_USB
581 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
582 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
583 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
587 * Dynamic MTD Partition support with mtdparts
595 * Miscellaneous configurable options
597 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
600 * For booting Linux, the board info and command line data
601 * have to be in the first 64 MB of memory, since this is
602 * the maximum mapped by the Linux kernel during initialization.
604 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
605 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
607 #ifdef CONFIG_CMD_KGDB
608 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
609 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
613 * Environment Configuration
615 #define CONFIG_ROOTPATH "/opt/nfsroot"
616 #define CONFIG_BOOTFILE "uImage"
617 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
619 /* default location for tftp and bootm */
620 #define CONFIG_LOADADDR 1000000
621 #define __USB_PHY_TYPE utmi
623 #define CONFIG_EXTRA_ENV_SETTINGS \
624 "hwconfig=fsl_ddr:" \
625 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
627 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
629 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
630 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
631 "tftpflash=tftpboot $loadaddr $uboot && " \
632 "protect off $ubootaddr +$filesize && " \
633 "erase $ubootaddr +$filesize && " \
634 "cp.b $loadaddr $ubootaddr $filesize && " \
635 "protect on $ubootaddr +$filesize && " \
636 "cmp.b $loadaddr $ubootaddr $filesize\0" \
637 "consoledev=ttyS0\0" \
638 "ramdiskaddr=2000000\0" \
639 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \
640 "fdtaddr=1e00000\0" \
641 "fdtfile=t2080rdb/t2080rdb.dtb\0" \
645 * For emulation this causes u-boot to jump to the start of the
646 * proof point app code automatically
648 #define CONFIG_PROOF_POINTS \
649 "setenv bootargs root=/dev/$bdev rw " \
650 "console=$consoledev,$baudrate $othbootargs;" \
651 "cpu 1 release 0x29000000 - - -;" \
652 "cpu 2 release 0x29000000 - - -;" \
653 "cpu 3 release 0x29000000 - - -;" \
654 "cpu 4 release 0x29000000 - - -;" \
655 "cpu 5 release 0x29000000 - - -;" \
656 "cpu 6 release 0x29000000 - - -;" \
657 "cpu 7 release 0x29000000 - - -;" \
660 #define CONFIG_HVBOOT \
661 "setenv bootargs config-addr=0x60000000; " \
662 "bootm 0x01000000 - 0x00f00000"
665 "setenv bootargs root=/dev/$bdev rw " \
666 "console=$consoledev,$baudrate $othbootargs;" \
667 "cpu 1 release 0x01000000 - - -;" \
668 "cpu 2 release 0x01000000 - - -;" \
669 "cpu 3 release 0x01000000 - - -;" \
670 "cpu 4 release 0x01000000 - - -;" \
671 "cpu 5 release 0x01000000 - - -;" \
672 "cpu 6 release 0x01000000 - - -;" \
673 "cpu 7 release 0x01000000 - - -;" \
676 #define CONFIG_LINUX \
677 "setenv bootargs root=/dev/ram rw " \
678 "console=$consoledev,$baudrate $othbootargs;" \
679 "setenv ramdiskaddr 0x02000000;" \
680 "setenv fdtaddr 0x00c00000;" \
681 "setenv loadaddr 0x1000000;" \
682 "bootm $loadaddr $ramdiskaddr $fdtaddr"
684 #define CONFIG_HDBOOT \
685 "setenv bootargs root=/dev/$bdev rw " \
686 "console=$consoledev,$baudrate $othbootargs;" \
687 "tftp $loadaddr $bootfile;" \
688 "tftp $fdtaddr $fdtfile;" \
689 "bootm $loadaddr - $fdtaddr"
691 #define CONFIG_NFSBOOTCOMMAND \
692 "setenv bootargs root=/dev/nfs rw " \
693 "nfsroot=$serverip:$rootpath " \
694 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
695 "console=$consoledev,$baudrate $othbootargs;" \
696 "tftp $loadaddr $bootfile;" \
697 "tftp $fdtaddr $fdtfile;" \
698 "bootm $loadaddr - $fdtaddr"
700 #define CONFIG_RAMBOOTCOMMAND \
701 "setenv bootargs root=/dev/ram rw " \
702 "console=$consoledev,$baudrate $othbootargs;" \
703 "tftp $ramdiskaddr $ramdiskfile;" \
704 "tftp $loadaddr $bootfile;" \
705 "tftp $fdtaddr $fdtfile;" \
706 "bootm $loadaddr $ramdiskaddr $fdtaddr"
708 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
710 #include <asm/fsl_secure_boot.h>
712 #endif /* __T2080RDB_H */