2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * T2080 RDB/PCIe board configuration file
14 #define CONFIG_T2080RDB
15 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
17 #define CONFIG_USB_EHCI
18 #define CONFIG_FSL_SATA_V2
20 /* High Level Configuration Options */
22 #define CONFIG_E500 /* BOOKE e500 family */
23 #define CONFIG_E500MC /* BOOKE e500mc family */
24 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
25 #define CONFIG_MP /* support multiple processors */
26 #define CONFIG_ENABLE_36BIT_PHYS
28 #ifdef CONFIG_PHYS_64BIT
29 #define CONFIG_ADDR_MAP 1
30 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
33 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
34 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
35 #define CONFIG_FSL_IFC /* Enable IFC Support */
36 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
37 #define CONFIG_ENV_OVERWRITE
39 #ifdef CONFIG_RAMBOOT_PBL
40 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
42 #define CONFIG_SPL_FLUSH_IMAGE
43 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
44 #define CONFIG_SYS_TEXT_BASE 0x00201000
45 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
46 #define CONFIG_SPL_PAD_TO 0x40000
47 #define CONFIG_SPL_MAX_SIZE 0x28000
48 #define RESET_VECTOR_OFFSET 0x27FFC
49 #define BOOT_PAGE_OFFSET 0x27000
50 #ifdef CONFIG_SPL_BUILD
51 #define CONFIG_SPL_SKIP_RELOCATE
52 #define CONFIG_SPL_COMMON_INIT_DDR
53 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
54 #define CONFIG_SYS_NO_FLASH
58 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
59 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
60 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
61 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
62 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
63 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg
64 #define CONFIG_SPL_NAND_BOOT
67 #ifdef CONFIG_SPIFLASH
68 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
69 #define CONFIG_SPL_SPI_FLASH_MINIMAL
70 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
71 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
72 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
73 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
74 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
75 #ifndef CONFIG_SPL_BUILD
76 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
78 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg
79 #define CONFIG_SPL_SPI_BOOT
83 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
84 #define CONFIG_SPL_MMC_MINIMAL
85 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
86 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
87 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
88 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
89 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
90 #ifndef CONFIG_SPL_BUILD
91 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
93 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg
94 #define CONFIG_SPL_MMC_BOOT
97 #endif /* CONFIG_RAMBOOT_PBL */
99 #define CONFIG_SRIO_PCIE_BOOT_MASTER
100 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
101 /* Set 1M boot space */
102 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
103 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
104 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
105 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
106 #define CONFIG_SYS_NO_FLASH
109 #ifndef CONFIG_SYS_TEXT_BASE
110 #define CONFIG_SYS_TEXT_BASE 0xeff40000
113 #ifndef CONFIG_RESET_VECTOR_ADDRESS
114 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
118 * These can be toggled for performance analysis, otherwise use default.
120 #define CONFIG_SYS_CACHE_STASHING
121 #define CONFIG_BTB /* toggle branch predition */
122 #define CONFIG_DDR_ECC
123 #ifdef CONFIG_DDR_ECC
124 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
125 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
128 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
129 #define CONFIG_SYS_MEMTEST_END 0x00400000
130 #define CONFIG_SYS_ALT_MEMTEST
132 #ifndef CONFIG_SYS_NO_FLASH
133 #define CONFIG_FLASH_CFI_DRIVER
134 #define CONFIG_SYS_FLASH_CFI
135 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
138 #if defined(CONFIG_SPIFLASH)
139 #define CONFIG_SYS_EXTRA_ENV_RELOC
140 #define CONFIG_ENV_IS_IN_SPI_FLASH
141 #define CONFIG_ENV_SPI_BUS 0
142 #define CONFIG_ENV_SPI_CS 0
143 #define CONFIG_ENV_SPI_MAX_HZ 10000000
144 #define CONFIG_ENV_SPI_MODE 0
145 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
146 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
147 #define CONFIG_ENV_SECT_SIZE 0x10000
148 #elif defined(CONFIG_SDCARD)
149 #define CONFIG_SYS_EXTRA_ENV_RELOC
150 #define CONFIG_ENV_IS_IN_MMC
151 #define CONFIG_SYS_MMC_ENV_DEV 0
152 #define CONFIG_ENV_SIZE 0x2000
153 #define CONFIG_ENV_OFFSET (512 * 0x800)
154 #elif defined(CONFIG_NAND)
155 #define CONFIG_SYS_EXTRA_ENV_RELOC
156 #define CONFIG_ENV_IS_IN_NAND
157 #define CONFIG_ENV_SIZE 0x2000
158 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
159 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
160 #define CONFIG_ENV_IS_IN_REMOTE
161 #define CONFIG_ENV_ADDR 0xffe20000
162 #define CONFIG_ENV_SIZE 0x2000
163 #elif defined(CONFIG_ENV_IS_NOWHERE)
164 #define CONFIG_ENV_SIZE 0x2000
166 #define CONFIG_ENV_IS_IN_FLASH
167 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
168 #define CONFIG_ENV_SIZE 0x2000
169 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
173 unsigned long get_board_sys_clk(void);
174 unsigned long get_board_ddr_clk(void);
177 #define CONFIG_SYS_CLK_FREQ 66660000
178 #define CONFIG_DDR_CLK_FREQ 133330000
181 * Config the L3 Cache as L3 SRAM
183 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
184 #define CONFIG_SYS_L3_SIZE (512 << 10)
185 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
186 #ifdef CONFIG_RAMBOOT_PBL
187 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
189 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
190 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
191 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
192 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
194 #define CONFIG_SYS_DCSRBAR 0xf0000000
195 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
198 #define CONFIG_ID_EEPROM
199 #define CONFIG_SYS_I2C_EEPROM_NXID
200 #define CONFIG_SYS_EEPROM_BUS_NUM 0
201 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
202 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
207 #define CONFIG_VERY_BIG_RAM
208 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
209 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
210 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
211 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
212 #define CONFIG_DDR_SPD
213 #define CONFIG_SYS_FSL_DDR3
214 #undef CONFIG_FSL_DDR_INTERACTIVE
215 #define CONFIG_SYS_SPD_BUS_NUM 0
216 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
217 #define SPD_EEPROM_ADDRESS1 0x51
218 #define SPD_EEPROM_ADDRESS2 0x52
219 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
220 #define CTRL_INTLV_PREFERED cacheline
225 #define CONFIG_SYS_FLASH_BASE 0xe8000000
226 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
227 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
228 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
229 CSPR_PORT_SIZE_16 | \
232 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
234 /* NOR Flash Timing Params */
235 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
237 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
238 FTIM0_NOR_TEADC(0x5) | \
239 FTIM0_NOR_TEAHC(0x5))
240 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
241 FTIM1_NOR_TRAD_NOR(0x1A) |\
242 FTIM1_NOR_TSEQRAD_NOR(0x13))
243 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
244 FTIM2_NOR_TCH(0x4) | \
245 FTIM2_NOR_TWPH(0x0E) | \
247 #define CONFIG_SYS_NOR_FTIM3 0x0
249 #define CONFIG_SYS_FLASH_QUIET_TEST
250 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
252 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
253 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
254 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
255 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
256 #define CONFIG_SYS_FLASH_EMPTY_INFO
257 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS }
260 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
261 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
262 #define CONFIG_SYS_CSPR2_EXT (0xf)
263 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
267 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
268 #define CONFIG_SYS_CSOR2 0x0
270 /* CPLD Timing parameters for IFC CS2 */
271 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
272 FTIM0_GPCM_TEADC(0x0e) | \
273 FTIM0_GPCM_TEAHC(0x0e))
274 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
275 FTIM1_GPCM_TRAD(0x1f))
276 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
277 FTIM2_GPCM_TCH(0x8) | \
278 FTIM2_GPCM_TWP(0x1f))
279 #define CONFIG_SYS_CS2_FTIM3 0x0
281 /* NAND Flash on IFC */
282 #define CONFIG_NAND_FSL_IFC
283 #define CONFIG_SYS_NAND_BASE 0xff800000
284 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
286 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
287 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
288 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
289 | CSPR_MSEL_NAND /* MSEL = NAND */ \
291 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
293 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
294 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
295 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
296 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
297 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
298 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
299 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
301 #define CONFIG_SYS_NAND_ONFI_DETECTION
303 /* ONFI NAND Flash mode0 Timing Params */
304 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
305 FTIM0_NAND_TWP(0x18) | \
306 FTIM0_NAND_TWCHT(0x07) | \
307 FTIM0_NAND_TWH(0x0a))
308 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
309 FTIM1_NAND_TWBE(0x39) | \
310 FTIM1_NAND_TRR(0x0e) | \
311 FTIM1_NAND_TRP(0x18))
312 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
313 FTIM2_NAND_TREH(0x0a) | \
314 FTIM2_NAND_TWHRE(0x1e))
315 #define CONFIG_SYS_NAND_FTIM3 0x0
317 #define CONFIG_SYS_NAND_DDR_LAW 11
318 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
319 #define CONFIG_SYS_MAX_NAND_DEVICE 1
320 #define CONFIG_CMD_NAND
321 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
323 #if defined(CONFIG_NAND)
324 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
325 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
326 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
327 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
328 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
329 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
330 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
331 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
332 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
333 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
334 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
335 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
336 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
337 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
338 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
339 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
341 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
342 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
343 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
344 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
345 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
346 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
347 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
348 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
349 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
350 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
351 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
352 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
353 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
354 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
355 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
356 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
359 #if defined(CONFIG_RAMBOOT_PBL)
360 #define CONFIG_SYS_RAMBOOT
363 #ifdef CONFIG_SPL_BUILD
364 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
366 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
369 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
370 #define CONFIG_MISC_INIT_R
371 #define CONFIG_HWCONFIG
373 /* define to use L1 as initial stack */
374 #define CONFIG_L1_INIT_RAM
375 #define CONFIG_SYS_INIT_RAM_LOCK
376 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
377 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
378 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
379 /* The assembler doesn't like typecast */
380 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
381 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
382 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
383 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
384 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
385 GENERATED_GBL_DATA_SIZE)
386 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
387 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
388 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
393 #define CONFIG_CONS_INDEX 1
394 #define CONFIG_SYS_NS16550_SERIAL
395 #define CONFIG_SYS_NS16550_REG_SIZE 1
396 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
397 #define CONFIG_SYS_BAUDRATE_TABLE \
398 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
399 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
400 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
401 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
402 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
407 #define CONFIG_SYS_I2C
408 #define CONFIG_SYS_I2C_FSL
409 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
410 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
411 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
412 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
413 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
414 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
415 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
416 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
417 #define CONFIG_SYS_FSL_I2C_SPEED 100000
418 #define CONFIG_SYS_FSL_I2C2_SPEED 100000
419 #define CONFIG_SYS_FSL_I2C3_SPEED 100000
420 #define CONFIG_SYS_FSL_I2C4_SPEED 100000
421 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
422 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
423 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
424 #define I2C_MUX_CH_DEFAULT 0x8
426 #define I2C_MUX_CH_VOL_MONITOR 0xa
428 #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv"
429 #ifndef CONFIG_SPL_BUILD
432 #define CONFIG_VOL_MONITOR_IR36021_SET
433 #define CONFIG_VOL_MONITOR_IR36021_READ
434 /* The lowest and highest voltage allowed for T208xRDB */
435 #define VDD_MV_MIN 819
436 #define VDD_MV_MAX 1212
441 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
442 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
443 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
444 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
445 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
446 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
448 * for slave u-boot IMAGE instored in master memory space,
449 * PHYS must be aligned based on the SIZE
451 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
452 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
453 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
454 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
456 * for slave UCODE and ENV instored in master memory space,
457 * PHYS must be aligned based on the SIZE
459 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
460 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
461 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
463 /* slave core release by master*/
464 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
465 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
468 * SRIO_PCIE_BOOT - SLAVE
470 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
471 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
472 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
473 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
477 * eSPI - Enhanced SPI
479 #ifdef CONFIG_SPI_FLASH
480 #define CONFIG_SPI_FLASH_BAR
481 #define CONFIG_SF_DEFAULT_SPEED 10000000
482 #define CONFIG_SF_DEFAULT_MODE 0
487 * Memory space is mapped 1-1, but I/O space must start from 0.
489 #define CONFIG_PCIE1 /* PCIE controller 1 */
490 #define CONFIG_PCIE2 /* PCIE controller 2 */
491 #define CONFIG_PCIE3 /* PCIE controller 3 */
492 #define CONFIG_PCIE4 /* PCIE controller 4 */
493 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
494 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
495 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
496 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
497 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
498 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
499 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
500 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
501 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
502 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
503 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
505 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
506 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
507 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
508 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
509 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
510 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
511 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
512 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
513 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
515 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
516 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
517 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
518 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
519 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
520 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
521 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
522 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
523 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
525 /* controller 4, Base address 203000 */
526 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
527 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
528 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
529 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
530 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
531 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
532 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
535 #define CONFIG_PCI_INDIRECT_BRIDGE
536 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */
537 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
538 #define CONFIG_DOS_PARTITION
542 #ifndef CONFIG_NOBQFMAN
543 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
544 #define CONFIG_SYS_BMAN_NUM_PORTALS 18
545 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
546 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
547 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
548 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
549 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
550 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
551 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
552 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
553 CONFIG_SYS_BMAN_CENA_SIZE)
554 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
555 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
556 #define CONFIG_SYS_QMAN_NUM_PORTALS 18
557 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
558 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
559 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
560 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
561 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
562 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
563 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
564 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
565 CONFIG_SYS_QMAN_CENA_SIZE)
566 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
567 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
569 #define CONFIG_SYS_DPAA_FMAN
570 #define CONFIG_SYS_DPAA_PME
571 #define CONFIG_SYS_PMAN
572 #define CONFIG_SYS_DPAA_DCE
573 #define CONFIG_SYS_DPAA_RMAN /* RMan */
574 #define CONFIG_SYS_INTERLAKEN
576 /* Default address of microcode for the Linux Fman driver */
577 #if defined(CONFIG_SPIFLASH)
579 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
580 * env, so we got 0x110000.
582 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
583 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
584 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
585 #define CONFIG_CORTINA_FW_ADDR 0x120000
587 #elif defined(CONFIG_SDCARD)
589 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
590 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
591 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
593 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
594 #define CONFIG_SYS_CORTINA_FW_IN_MMC
595 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
596 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0)
598 #elif defined(CONFIG_NAND)
599 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
600 #define CONFIG_SYS_CORTINA_FW_IN_NAND
601 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
602 #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
603 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
605 * Slave has no ucode locally, it can fetch this from remote. When implementing
606 * in two corenet boards, slave's ucode could be stored in master's memory
607 * space, the address can be mapped from slave TLB->slave LAW->
608 * slave SRIO or PCIE outbound window->master inbound window->
609 * master LAW->the ucode address in master's memory space.
611 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
612 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE
613 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
614 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000
616 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
617 #define CONFIG_SYS_CORTINA_FW_IN_NOR
618 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
619 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000
621 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
622 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
623 #endif /* CONFIG_NOBQFMAN */
625 #ifdef CONFIG_SYS_DPAA_FMAN
626 #define CONFIG_FMAN_ENET
627 #define CONFIG_PHYLIB_10G
628 #define CONFIG_PHY_AQUANTIA
629 #define CONFIG_PHY_CORTINA
630 #define CONFIG_PHY_REALTEK
631 #define CONFIG_CORTINA_FW_LENGTH 0x40000
632 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
633 #define RGMII_PHY2_ADDR 0x02
634 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */
635 #define CORTINA_PHY_ADDR2 0x0d
636 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */
637 #define FM1_10GEC4_PHY_ADDR 0x01
640 #ifdef CONFIG_FMAN_ENET
641 #define CONFIG_MII /* MII PHY management */
642 #define CONFIG_ETHPRIME "FM1@DTSEC3"
643 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
649 #ifdef CONFIG_FSL_SATA_V2
650 #define CONFIG_LIBATA
651 #define CONFIG_FSL_SATA
652 #define CONFIG_SYS_SATA_MAX_DEVICE 2
654 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
655 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
657 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
658 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
660 #define CONFIG_CMD_SATA
661 #define CONFIG_DOS_PARTITION
667 #ifdef CONFIG_USB_EHCI
668 #define CONFIG_USB_EHCI_FSL
669 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
670 #define CONFIG_HAS_FSL_DR_USB
677 #define CONFIG_FSL_ESDHC
678 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
679 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
680 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
681 #define CONFIG_GENERIC_MMC
682 #define CONFIG_DOS_PARTITION
686 * Dynamic MTD Partition support with mtdparts
688 #ifndef CONFIG_SYS_NO_FLASH
689 #define CONFIG_MTD_DEVICE
690 #define CONFIG_MTD_PARTITIONS
691 #define CONFIG_CMD_MTDPARTS
692 #define CONFIG_FLASH_CFI_MTD
693 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
695 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
696 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
697 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \
698 "1m(uboot),5m(kernel),128k(dtb),-(user)"
706 * Command line configuration.
708 #define CONFIG_CMD_ERRATA
709 #define CONFIG_CMD_REGINFO
712 #define CONFIG_CMD_PCI
715 /* Hash command with SHA acceleration supported in hardware */
716 #ifdef CONFIG_FSL_CAAM
717 #define CONFIG_CMD_HASH
718 #define CONFIG_SHA_HW_ACCEL
722 * Miscellaneous configurable options
724 #define CONFIG_SYS_LONGHELP /* undef to save memory */
725 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
726 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
727 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
728 #ifdef CONFIG_CMD_KGDB
729 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
731 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
733 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
734 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
735 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
738 * For booting Linux, the board info and command line data
739 * have to be in the first 64 MB of memory, since this is
740 * the maximum mapped by the Linux kernel during initialization.
742 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
743 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
745 #ifdef CONFIG_CMD_KGDB
746 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
747 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
751 * Environment Configuration
753 #define CONFIG_ROOTPATH "/opt/nfsroot"
754 #define CONFIG_BOOTFILE "uImage"
755 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
757 /* default location for tftp and bootm */
758 #define CONFIG_LOADADDR 1000000
759 #define CONFIG_BAUDRATE 115200
760 #define __USB_PHY_TYPE utmi
762 #define CONFIG_EXTRA_ENV_SETTINGS \
763 "hwconfig=fsl_ddr:" \
764 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
766 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
768 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
769 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
770 "tftpflash=tftpboot $loadaddr $uboot && " \
771 "protect off $ubootaddr +$filesize && " \
772 "erase $ubootaddr +$filesize && " \
773 "cp.b $loadaddr $ubootaddr $filesize && " \
774 "protect on $ubootaddr +$filesize && " \
775 "cmp.b $loadaddr $ubootaddr $filesize\0" \
776 "consoledev=ttyS0\0" \
777 "ramdiskaddr=2000000\0" \
778 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \
779 "fdtaddr=1e00000\0" \
780 "fdtfile=t2080rdb/t2080rdb.dtb\0" \
784 * For emulation this causes u-boot to jump to the start of the
785 * proof point app code automatically
787 #define CONFIG_PROOF_POINTS \
788 "setenv bootargs root=/dev/$bdev rw " \
789 "console=$consoledev,$baudrate $othbootargs;" \
790 "cpu 1 release 0x29000000 - - -;" \
791 "cpu 2 release 0x29000000 - - -;" \
792 "cpu 3 release 0x29000000 - - -;" \
793 "cpu 4 release 0x29000000 - - -;" \
794 "cpu 5 release 0x29000000 - - -;" \
795 "cpu 6 release 0x29000000 - - -;" \
796 "cpu 7 release 0x29000000 - - -;" \
799 #define CONFIG_HVBOOT \
800 "setenv bootargs config-addr=0x60000000; " \
801 "bootm 0x01000000 - 0x00f00000"
804 "setenv bootargs root=/dev/$bdev rw " \
805 "console=$consoledev,$baudrate $othbootargs;" \
806 "cpu 1 release 0x01000000 - - -;" \
807 "cpu 2 release 0x01000000 - - -;" \
808 "cpu 3 release 0x01000000 - - -;" \
809 "cpu 4 release 0x01000000 - - -;" \
810 "cpu 5 release 0x01000000 - - -;" \
811 "cpu 6 release 0x01000000 - - -;" \
812 "cpu 7 release 0x01000000 - - -;" \
815 #define CONFIG_LINUX \
816 "setenv bootargs root=/dev/ram rw " \
817 "console=$consoledev,$baudrate $othbootargs;" \
818 "setenv ramdiskaddr 0x02000000;" \
819 "setenv fdtaddr 0x00c00000;" \
820 "setenv loadaddr 0x1000000;" \
821 "bootm $loadaddr $ramdiskaddr $fdtaddr"
823 #define CONFIG_HDBOOT \
824 "setenv bootargs root=/dev/$bdev rw " \
825 "console=$consoledev,$baudrate $othbootargs;" \
826 "tftp $loadaddr $bootfile;" \
827 "tftp $fdtaddr $fdtfile;" \
828 "bootm $loadaddr - $fdtaddr"
830 #define CONFIG_NFSBOOTCOMMAND \
831 "setenv bootargs root=/dev/nfs rw " \
832 "nfsroot=$serverip:$rootpath " \
833 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
834 "console=$consoledev,$baudrate $othbootargs;" \
835 "tftp $loadaddr $bootfile;" \
836 "tftp $fdtaddr $fdtfile;" \
837 "bootm $loadaddr - $fdtaddr"
839 #define CONFIG_RAMBOOTCOMMAND \
840 "setenv bootargs root=/dev/ram rw " \
841 "console=$consoledev,$baudrate $othbootargs;" \
842 "tftp $ramdiskaddr $ramdiskfile;" \
843 "tftp $loadaddr $bootfile;" \
844 "tftp $fdtaddr $fdtfile;" \
845 "bootm $loadaddr $ramdiskaddr $fdtaddr"
847 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
849 #include <asm/fsl_secure_boot.h>
851 #endif /* __T2080RDB_H */