common/board_f.c: modify the macro to use get_clocks() more common
[platform/kernel/u-boot.git] / include / configs / T208xRDB.h
1 /*
2  * Copyright 2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 /*
8  * T2080 RDB/PCIe board configuration file
9  */
10
11 #ifndef __T2080RDB_H
12 #define __T2080RDB_H
13
14 #define CONFIG_DISPLAY_BOARDINFO
15 #define CONFIG_T2080RDB
16 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
17 #define CONFIG_FSL_CLK
18 #define CONFIG_MMC
19 #define CONFIG_USB_EHCI
20 #define CONFIG_FSL_SATA_V2
21
22 /* High Level Configuration Options */
23 #define CONFIG_PHYS_64BIT
24 #define CONFIG_BOOKE
25 #define CONFIG_E500             /* BOOKE e500 family */
26 #define CONFIG_E500MC           /* BOOKE e500mc family */
27 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
28 #define CONFIG_MP               /* support multiple processors */
29 #define CONFIG_ENABLE_36BIT_PHYS
30
31 #ifdef CONFIG_PHYS_64BIT
32 #define CONFIG_ADDR_MAP 1
33 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
34 #endif
35
36 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
37 #define CONFIG_SYS_NUM_CPC      CONFIG_NUM_DDR_CONTROLLERS
38 #define CONFIG_FSL_IFC          /* Enable IFC Support */
39 #define CONFIG_FSL_CAAM         /* Enable SEC/CAAM */
40 #define CONFIG_FSL_LAW          /* Use common FSL init code */
41 #define CONFIG_ENV_OVERWRITE
42
43 #ifdef CONFIG_RAMBOOT_PBL
44 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
45 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_rcw.cfg
46
47 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
48 #define CONFIG_SPL_ENV_SUPPORT
49 #define CONFIG_SPL_SERIAL_SUPPORT
50 #define CONFIG_SPL_FLUSH_IMAGE
51 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
52 #define CONFIG_SPL_LIBGENERIC_SUPPORT
53 #define CONFIG_SPL_LIBCOMMON_SUPPORT
54 #define CONFIG_SPL_I2C_SUPPORT
55 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
56 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
57 #define CONFIG_SYS_TEXT_BASE            0x00201000
58 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
59 #define CONFIG_SPL_PAD_TO               0x40000
60 #define CONFIG_SPL_MAX_SIZE             0x28000
61 #define RESET_VECTOR_OFFSET             0x27FFC
62 #define BOOT_PAGE_OFFSET                0x27000
63 #ifdef CONFIG_SPL_BUILD
64 #define CONFIG_SPL_SKIP_RELOCATE
65 #define CONFIG_SPL_COMMON_INIT_DDR
66 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
67 #define CONFIG_SYS_NO_FLASH
68 #endif
69
70 #ifdef CONFIG_NAND
71 #define CONFIG_SPL_NAND_SUPPORT
72 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
73 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
74 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
75 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
76 #define CONFIG_SYS_LDSCRIPT  "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
77 #define CONFIG_SPL_NAND_BOOT
78 #endif
79
80 #ifdef CONFIG_SPIFLASH
81 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
82 #define CONFIG_SPL_SPI_SUPPORT
83 #define CONFIG_SPL_SPI_FLASH_SUPPORT
84 #define CONFIG_SPL_SPI_FLASH_MINIMAL
85 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
86 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
87 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
88 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
89 #define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot.lds"
90 #ifndef CONFIG_SPL_BUILD
91 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
92 #endif
93 #define CONFIG_SPL_SPI_BOOT
94 #endif
95
96 #ifdef CONFIG_SDCARD
97 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
98 #define CONFIG_SPL_MMC_SUPPORT
99 #define CONFIG_SPL_MMC_MINIMAL
100 #define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
101 #define CONFIG_SYS_MMC_U_BOOT_DST      (0x00200000)
102 #define CONFIG_SYS_MMC_U_BOOT_START    (0x00200000)
103 #define CONFIG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
104 #define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot.lds"
105 #ifndef CONFIG_SPL_BUILD
106 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
107 #endif
108 #define CONFIG_SPL_MMC_BOOT
109 #endif
110
111 #endif /* CONFIG_RAMBOOT_PBL */
112
113 #define CONFIG_SRIO_PCIE_BOOT_MASTER
114 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
115 /* Set 1M boot space */
116 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
117 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
118                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
119 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
120 #define CONFIG_SYS_NO_FLASH
121 #endif
122
123 #ifndef CONFIG_SYS_TEXT_BASE
124 #define CONFIG_SYS_TEXT_BASE    0xeff40000
125 #endif
126
127 #ifndef CONFIG_RESET_VECTOR_ADDRESS
128 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
129 #endif
130
131 /*
132  * These can be toggled for performance analysis, otherwise use default.
133  */
134 #define CONFIG_SYS_CACHE_STASHING
135 #define CONFIG_BTB              /* toggle branch predition */
136 #define CONFIG_DDR_ECC
137 #ifdef CONFIG_DDR_ECC
138 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
139 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
140 #endif
141
142 #define CONFIG_CMD_MEMTEST
143 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
144 #define CONFIG_SYS_MEMTEST_END          0x00400000
145 #define CONFIG_SYS_ALT_MEMTEST
146
147 #ifndef CONFIG_SYS_NO_FLASH
148 #define CONFIG_FLASH_CFI_DRIVER
149 #define CONFIG_SYS_FLASH_CFI
150 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
151 #endif
152
153 #if defined(CONFIG_SPIFLASH)
154 #define CONFIG_SYS_EXTRA_ENV_RELOC
155 #define CONFIG_ENV_IS_IN_SPI_FLASH
156 #define CONFIG_ENV_SPI_BUS      0
157 #define CONFIG_ENV_SPI_CS       0
158 #define CONFIG_ENV_SPI_MAX_HZ   10000000
159 #define CONFIG_ENV_SPI_MODE     0
160 #define CONFIG_ENV_SIZE         0x2000     /* 8KB */
161 #define CONFIG_ENV_OFFSET       0x100000   /* 1MB */
162 #define CONFIG_ENV_SECT_SIZE    0x10000
163 #elif defined(CONFIG_SDCARD)
164 #define CONFIG_SYS_EXTRA_ENV_RELOC
165 #define CONFIG_ENV_IS_IN_MMC
166 #define CONFIG_SYS_MMC_ENV_DEV  0
167 #define CONFIG_ENV_SIZE         0x2000
168 #define CONFIG_ENV_OFFSET       (512 * 0x800)
169 #elif defined(CONFIG_NAND)
170 #define CONFIG_SYS_EXTRA_ENV_RELOC
171 #define CONFIG_ENV_IS_IN_NAND
172 #define CONFIG_ENV_SIZE         0x2000
173 #define CONFIG_ENV_OFFSET       (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
174 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
175 #define CONFIG_ENV_IS_IN_REMOTE
176 #define CONFIG_ENV_ADDR         0xffe20000
177 #define CONFIG_ENV_SIZE         0x2000
178 #elif defined(CONFIG_ENV_IS_NOWHERE)
179 #define CONFIG_ENV_SIZE         0x2000
180 #else
181 #define CONFIG_ENV_IS_IN_FLASH
182 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
183 #define CONFIG_ENV_SIZE         0x2000
184 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
185 #endif
186
187 #ifndef __ASSEMBLY__
188 unsigned long get_board_sys_clk(void);
189 unsigned long get_board_ddr_clk(void);
190 #endif
191
192 #define CONFIG_SYS_CLK_FREQ     66660000
193 #define CONFIG_DDR_CLK_FREQ     133330000
194
195 /*
196  * Config the L3 Cache as L3 SRAM
197  */
198 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
199 #define CONFIG_SYS_L3_SIZE              (512 << 10)
200 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
201 #ifdef CONFIG_RAMBOOT_PBL
202 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
203 #endif
204 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
205 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
206 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
207 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
208
209 #define CONFIG_SYS_DCSRBAR      0xf0000000
210 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
211
212 /* EEPROM */
213 #define CONFIG_ID_EEPROM
214 #define CONFIG_SYS_I2C_EEPROM_NXID
215 #define CONFIG_SYS_EEPROM_BUS_NUM       0
216 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
217 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
218
219 /*
220  * DDR Setup
221  */
222 #define CONFIG_VERY_BIG_RAM
223 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
224 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
225 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
226 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
227 #define CONFIG_DDR_SPD
228 #define CONFIG_SYS_FSL_DDR3
229 #undef CONFIG_FSL_DDR_INTERACTIVE
230 #define CONFIG_SYS_SPD_BUS_NUM  0
231 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
232 #define SPD_EEPROM_ADDRESS1     0x51
233 #define SPD_EEPROM_ADDRESS2     0x52
234 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
235 #define CTRL_INTLV_PREFERED     cacheline
236
237 /*
238  * IFC Definitions
239  */
240 #define CONFIG_SYS_FLASH_BASE           0xe8000000
241 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
242 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
243 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
244                                 CSPR_PORT_SIZE_16 | \
245                                 CSPR_MSEL_NOR | \
246                                 CSPR_V)
247 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
248
249 /* NOR Flash Timing Params */
250 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
251
252 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
253                                 FTIM0_NOR_TEADC(0x5) | \
254                                 FTIM0_NOR_TEAHC(0x5))
255 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
256                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
257                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
258 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
259                                 FTIM2_NOR_TCH(0x4) | \
260                                 FTIM2_NOR_TWPH(0x0E) | \
261                                 FTIM2_NOR_TWP(0x1c))
262 #define CONFIG_SYS_NOR_FTIM3    0x0
263
264 #define CONFIG_SYS_FLASH_QUIET_TEST
265 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
266
267 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
268 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
269 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
270 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
271 #define CONFIG_SYS_FLASH_EMPTY_INFO
272 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS }
273
274 /* CPLD on IFC */
275 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
276 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
277 #define CONFIG_SYS_CSPR2_EXT    (0xf)
278 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
279                                 | CSPR_PORT_SIZE_8 \
280                                 | CSPR_MSEL_GPCM \
281                                 | CSPR_V)
282 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
283 #define CONFIG_SYS_CSOR2        0x0
284
285 /* CPLD Timing parameters for IFC CS2 */
286 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
287                                         FTIM0_GPCM_TEADC(0x0e) | \
288                                         FTIM0_GPCM_TEAHC(0x0e))
289 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
290                                         FTIM1_GPCM_TRAD(0x1f))
291 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
292                                         FTIM2_GPCM_TCH(0x8) | \
293                                         FTIM2_GPCM_TWP(0x1f))
294 #define CONFIG_SYS_CS2_FTIM3            0x0
295
296 /* NAND Flash on IFC */
297 #define CONFIG_NAND_FSL_IFC
298 #define CONFIG_SYS_NAND_BASE            0xff800000
299 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
300
301 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
302 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
303                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
304                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
305                                 | CSPR_V)
306 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
307
308 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
309                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
310                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
311                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
312                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
313                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
314                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
315
316 #define CONFIG_SYS_NAND_ONFI_DETECTION
317
318 /* ONFI NAND Flash mode0 Timing Params */
319 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
320                                         FTIM0_NAND_TWP(0x18)    | \
321                                         FTIM0_NAND_TWCHT(0x07)  | \
322                                         FTIM0_NAND_TWH(0x0a))
323 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
324                                         FTIM1_NAND_TWBE(0x39)   | \
325                                         FTIM1_NAND_TRR(0x0e)    | \
326                                         FTIM1_NAND_TRP(0x18))
327 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
328                                         FTIM2_NAND_TREH(0x0a)   | \
329                                         FTIM2_NAND_TWHRE(0x1e))
330 #define CONFIG_SYS_NAND_FTIM3           0x0
331
332 #define CONFIG_SYS_NAND_DDR_LAW         11
333 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
334 #define CONFIG_SYS_MAX_NAND_DEVICE      1
335 #define CONFIG_CMD_NAND
336 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
337
338 #if defined(CONFIG_NAND)
339 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
340 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
341 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
342 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
343 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
344 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
345 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
346 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
347 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
348 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
349 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
350 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
351 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
352 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
353 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
354 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
355 #else
356 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
357 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
358 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
359 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
360 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
361 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
362 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
363 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
364 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
365 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
366 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
367 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
368 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
369 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
370 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
371 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
372 #endif
373
374 #if defined(CONFIG_RAMBOOT_PBL)
375 #define CONFIG_SYS_RAMBOOT
376 #endif
377
378 #ifdef CONFIG_SPL_BUILD
379 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SPL_TEXT_BASE
380 #else
381 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SYS_TEXT_BASE /* start of monitor */
382 #endif
383
384 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
385 #define CONFIG_MISC_INIT_R
386 #define CONFIG_HWCONFIG
387
388 /* define to use L1 as initial stack */
389 #define CONFIG_L1_INIT_RAM
390 #define CONFIG_SYS_INIT_RAM_LOCK
391 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
392 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
393 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
394 /* The assembler doesn't like typecast */
395 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
396                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
397                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
398 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
399 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
400                                                 GENERATED_GBL_DATA_SIZE)
401 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
402 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
403 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
404
405 /*
406  * Serial Port
407  */
408 #define CONFIG_CONS_INDEX               1
409 #define CONFIG_SYS_NS16550
410 #define CONFIG_SYS_NS16550_SERIAL
411 #define CONFIG_SYS_NS16550_REG_SIZE     1
412 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
413 #define CONFIG_SYS_BAUDRATE_TABLE       \
414         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
415 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
416 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
417 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
418 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
419
420 /* Use the HUSH parser */
421 #define CONFIG_SYS_HUSH_PARSER
422 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
423
424 /* pass open firmware flat tree */
425 #define CONFIG_OF_LIBFDT
426 #define CONFIG_OF_BOARD_SETUP
427 #define CONFIG_OF_STDOUT_VIA_ALIAS
428
429 /* new uImage format support */
430 #define CONFIG_FIT
431 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
432
433 /*
434  * I2C
435  */
436 #define CONFIG_SYS_I2C
437 #define CONFIG_SYS_I2C_FSL
438 #define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
439 #define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
440 #define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
441 #define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
442 #define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
443 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
444 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
445 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
446 #define CONFIG_SYS_FSL_I2C_SPEED   100000
447 #define CONFIG_SYS_FSL_I2C2_SPEED  100000
448 #define CONFIG_SYS_FSL_I2C3_SPEED  100000
449 #define CONFIG_SYS_FSL_I2C4_SPEED  100000
450 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
451 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
452 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
453 #define I2C_MUX_CH_DEFAULT      0x8
454
455 #define I2C_MUX_CH_VOL_MONITOR  0xa
456
457 #define CONFIG_VID_FLS_ENV              "t208xrdb_vdd_mv"
458 #ifndef CONFIG_SPL_BUILD
459 #define CONFIG_VID
460 #endif
461 #define CONFIG_VOL_MONITOR_IR36021_SET
462 #define CONFIG_VOL_MONITOR_IR36021_READ
463 /* The lowest and highest voltage allowed for T208xRDB */
464 #define VDD_MV_MIN                      819
465 #define VDD_MV_MAX                      1212
466
467 /*
468  * RapidIO
469  */
470 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
471 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
472 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
473 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
474 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
475 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
476 /*
477  * for slave u-boot IMAGE instored in master memory space,
478  * PHYS must be aligned based on the SIZE
479  */
480 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
481 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
482 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
483 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
484 /*
485  * for slave UCODE and ENV instored in master memory space,
486  * PHYS must be aligned based on the SIZE
487  */
488 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
489 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
490 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
491
492 /* slave core release by master*/
493 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
494 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
495
496 /*
497  * SRIO_PCIE_BOOT - SLAVE
498  */
499 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
500 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
501 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
502                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
503 #endif
504
505 /*
506  * eSPI - Enhanced SPI
507  */
508 #ifdef CONFIG_SPI_FLASH
509 #define CONFIG_FSL_ESPI
510 #define CONFIG_SPI_FLASH_STMICRO
511 #define CONFIG_SPI_FLASH_BAR
512 #define CONFIG_CMD_SF
513 #define CONFIG_SF_DEFAULT_SPEED  10000000
514 #define CONFIG_SF_DEFAULT_MODE    0
515 #endif
516
517 /*
518  * General PCI
519  * Memory space is mapped 1-1, but I/O space must start from 0.
520  */
521 #define CONFIG_PCI              /* Enable PCI/PCIE */
522 #define CONFIG_PCIE1            /* PCIE controler 1 */
523 #define CONFIG_PCIE2            /* PCIE controler 2 */
524 #define CONFIG_PCIE3            /* PCIE controler 3 */
525 #define CONFIG_PCIE4            /* PCIE controler 4 */
526 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
527 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
528 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
529 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
530 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
531 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
532 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
533 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
534 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
535 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
536 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
537
538 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
539 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
540 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
541 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
542 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000 /* 256M */
543 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
544 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
545 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
546 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
547
548 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
549 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
550 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
551 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
552 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
553 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
554 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
555 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
556 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
557
558 /* controller 4, Base address 203000 */
559 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
560 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
561 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
562 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
563 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
564 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
565 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
566
567 #ifdef CONFIG_PCI
568 #define CONFIG_PCI_INDIRECT_BRIDGE
569 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata LSZ ADD */
570 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
571 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
572 #define CONFIG_DOS_PARTITION
573 #endif
574
575 /* Qman/Bman */
576 #ifndef CONFIG_NOBQFMAN
577 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
578 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
579 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
580 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
581 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
582 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
583 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
584 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
585 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
586 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
587                                         CONFIG_SYS_BMAN_CENA_SIZE)
588 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
589 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
590 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
591 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
592 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
593 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
594 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
595 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
596 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
597 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
598 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
599                                         CONFIG_SYS_QMAN_CENA_SIZE)
600 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
601 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
602
603 #define CONFIG_SYS_DPAA_FMAN
604 #define CONFIG_SYS_DPAA_PME
605 #define CONFIG_SYS_PMAN
606 #define CONFIG_SYS_DPAA_DCE
607 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
608 #define CONFIG_SYS_INTERLAKEN
609
610 /* Default address of microcode for the Linux Fman driver */
611 #if defined(CONFIG_SPIFLASH)
612 /*
613  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
614  * env, so we got 0x110000.
615  */
616 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
617 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
618 #define CONFIG_SYS_FMAN_FW_ADDR         0x110000
619 #define CONFIG_CORTINA_FW_ADDR          0x120000
620
621 #elif defined(CONFIG_SDCARD)
622 /*
623  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
624  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
625  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
626  */
627 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
628 #define CONFIG_SYS_CORTINA_FW_IN_MMC
629 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
630 #define CONFIG_CORTINA_FW_ADDR          (512 * 0x8a0)
631
632 #elif defined(CONFIG_NAND)
633 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
634 #define CONFIG_SYS_CORTINA_FW_IN_NAND
635 #define CONFIG_SYS_FMAN_FW_ADDR         (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
636 #define CONFIG_CORTINA_FW_ADDR          (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
637 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
638 /*
639  * Slave has no ucode locally, it can fetch this from remote. When implementing
640  * in two corenet boards, slave's ucode could be stored in master's memory
641  * space, the address can be mapped from slave TLB->slave LAW->
642  * slave SRIO or PCIE outbound window->master inbound window->
643  * master LAW->the ucode address in master's memory space.
644  */
645 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
646 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE
647 #define CONFIG_SYS_FMAN_FW_ADDR         0xFFE00000
648 #define CONFIG_CORTINA_FW_ADDR          0xFFE10000
649 #else
650 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
651 #define CONFIG_SYS_CORTINA_FW_IN_NOR
652 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
653 #define CONFIG_CORTINA_FW_ADDR          0xEFE00000
654 #endif
655 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
656 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
657 #endif /* CONFIG_NOBQFMAN */
658
659 #ifdef CONFIG_SYS_DPAA_FMAN
660 #define CONFIG_FMAN_ENET
661 #define CONFIG_PHYLIB_10G
662 #define CONFIG_PHY_AQUANTIA
663 #define CONFIG_PHY_CORTINA
664 #define CONFIG_PHY_REALTEK
665 #define CONFIG_CORTINA_FW_LENGTH        0x40000
666 #define RGMII_PHY1_ADDR         0x01  /* RealTek RTL8211E */
667 #define RGMII_PHY2_ADDR         0x02
668 #define CORTINA_PHY_ADDR1       0x0c  /* Cortina CS4315 */
669 #define CORTINA_PHY_ADDR2       0x0d
670 #define FM1_10GEC3_PHY_ADDR     0x00  /* Aquantia AQ1202 10G Base-T */
671 #define FM1_10GEC4_PHY_ADDR     0x01
672 #endif
673
674
675 #ifdef CONFIG_FMAN_ENET
676 #define CONFIG_MII              /* MII PHY management */
677 #define CONFIG_ETHPRIME         "FM1@DTSEC3"
678 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
679 #endif
680
681 /*
682  * SATA
683  */
684 #ifdef CONFIG_FSL_SATA_V2
685 #define CONFIG_LIBATA
686 #define CONFIG_FSL_SATA
687 #define CONFIG_SYS_SATA_MAX_DEVICE      2
688 #define CONFIG_SATA1
689 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
690 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
691 #define CONFIG_SATA2
692 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
693 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
694 #define CONFIG_LBA48
695 #define CONFIG_CMD_SATA
696 #define CONFIG_DOS_PARTITION
697 #define CONFIG_CMD_EXT2
698 #endif
699
700 /*
701  * USB
702  */
703 #ifdef CONFIG_USB_EHCI
704 #define CONFIG_CMD_USB
705 #define CONFIG_USB_STORAGE
706 #define CONFIG_USB_EHCI_FSL
707 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
708 #define CONFIG_CMD_EXT2
709 #define CONFIG_HAS_FSL_DR_USB
710 #endif
711
712 /*
713  * SDHC
714  */
715 #ifdef CONFIG_MMC
716 #define CONFIG_CMD_MMC
717 #define CONFIG_FSL_ESDHC
718 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
719 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
720 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
721 #define CONFIG_GENERIC_MMC
722 #define CONFIG_CMD_EXT2
723 #define CONFIG_CMD_FAT
724 #define CONFIG_DOS_PARTITION
725 #endif
726
727 /*
728  * Dynamic MTD Partition support with mtdparts
729  */
730 #ifndef CONFIG_SYS_NO_FLASH
731 #define CONFIG_MTD_DEVICE
732 #define CONFIG_MTD_PARTITIONS
733 #define CONFIG_CMD_MTDPARTS
734 #define CONFIG_FLASH_CFI_MTD
735 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
736                         "spi0=spife110000.1"
737 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
738                         "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
739                         "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \
740                         "1m(uboot),5m(kernel),128k(dtb),-(user)"
741 #endif
742
743 /*
744  * Environment
745  */
746
747 /*
748  * Command line configuration.
749  */
750 #define CONFIG_CMD_DHCP
751 #define CONFIG_CMD_ERRATA
752 #define CONFIG_CMD_MII
753 #define CONFIG_CMD_I2C
754 #define CONFIG_CMD_PING
755 #define CONFIG_CMD_REGINFO
756
757 #ifdef CONFIG_PCI
758 #define CONFIG_CMD_PCI
759 #endif
760
761 /* Hash command with SHA acceleration supported in hardware */
762 #ifdef CONFIG_FSL_CAAM
763 #define CONFIG_CMD_HASH
764 #define CONFIG_SHA_HW_ACCEL
765 #endif
766
767 /*
768  * Miscellaneous configurable options
769  */
770 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
771 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
772 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support */
773 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
774 #ifdef CONFIG_CMD_KGDB
775 #define CONFIG_SYS_CBSIZE       1024      /* Console I/O Buffer Size */
776 #else
777 #define CONFIG_SYS_CBSIZE       256       /* Console I/O Buffer Size */
778 #endif
779 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
780 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
781 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
782
783 /*
784  * For booting Linux, the board info and command line data
785  * have to be in the first 64 MB of memory, since this is
786  * the maximum mapped by the Linux kernel during initialization.
787  */
788 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
789 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
790
791 #ifdef CONFIG_CMD_KGDB
792 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
793 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
794 #endif
795
796 /*
797  * Environment Configuration
798  */
799 #define CONFIG_ROOTPATH  "/opt/nfsroot"
800 #define CONFIG_BOOTFILE  "uImage"
801 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
802
803 /* default location for tftp and bootm */
804 #define CONFIG_LOADADDR         1000000
805 #define CONFIG_BAUDRATE         115200
806 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
807 #define __USB_PHY_TYPE          utmi
808
809 #define CONFIG_EXTRA_ENV_SETTINGS                               \
810         "hwconfig=fsl_ddr:"                                     \
811         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
812         "bank_intlv=auto;"                                      \
813         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
814         "netdev=eth0\0"                                         \
815         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
816         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
817         "tftpflash=tftpboot $loadaddr $uboot && "               \
818         "protect off $ubootaddr +$filesize && "                 \
819         "erase $ubootaddr +$filesize && "                       \
820         "cp.b $loadaddr $ubootaddr $filesize && "               \
821         "protect on $ubootaddr +$filesize && "                  \
822         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
823         "consoledev=ttyS0\0"                                    \
824         "ramdiskaddr=2000000\0"                                 \
825         "ramdiskfile=t2080rdb/ramdisk.uboot\0"                  \
826         "fdtaddr=c00000\0"                                      \
827         "fdtfile=t2080rdb/t2080rdb.dtb\0"                       \
828         "bdev=sda3\0"
829
830 /*
831  * For emulation this causes u-boot to jump to the start of the
832  * proof point app code automatically
833  */
834 #define CONFIG_PROOF_POINTS                             \
835         "setenv bootargs root=/dev/$bdev rw "           \
836         "console=$consoledev,$baudrate $othbootargs;"   \
837         "cpu 1 release 0x29000000 - - -;"               \
838         "cpu 2 release 0x29000000 - - -;"               \
839         "cpu 3 release 0x29000000 - - -;"               \
840         "cpu 4 release 0x29000000 - - -;"               \
841         "cpu 5 release 0x29000000 - - -;"               \
842         "cpu 6 release 0x29000000 - - -;"               \
843         "cpu 7 release 0x29000000 - - -;"               \
844         "go 0x29000000"
845
846 #define CONFIG_HVBOOT                           \
847         "setenv bootargs config-addr=0x60000000; "      \
848         "bootm 0x01000000 - 0x00f00000"
849
850 #define CONFIG_ALU                              \
851         "setenv bootargs root=/dev/$bdev rw "           \
852         "console=$consoledev,$baudrate $othbootargs;"   \
853         "cpu 1 release 0x01000000 - - -;"               \
854         "cpu 2 release 0x01000000 - - -;"               \
855         "cpu 3 release 0x01000000 - - -;"               \
856         "cpu 4 release 0x01000000 - - -;"               \
857         "cpu 5 release 0x01000000 - - -;"               \
858         "cpu 6 release 0x01000000 - - -;"               \
859         "cpu 7 release 0x01000000 - - -;"               \
860         "go 0x01000000"
861
862 #define CONFIG_LINUX                            \
863         "setenv bootargs root=/dev/ram rw "             \
864         "console=$consoledev,$baudrate $othbootargs;"   \
865         "setenv ramdiskaddr 0x02000000;"                \
866         "setenv fdtaddr 0x00c00000;"                    \
867         "setenv loadaddr 0x1000000;"                    \
868         "bootm $loadaddr $ramdiskaddr $fdtaddr"
869
870 #define CONFIG_HDBOOT                                   \
871         "setenv bootargs root=/dev/$bdev rw "           \
872         "console=$consoledev,$baudrate $othbootargs;"   \
873         "tftp $loadaddr $bootfile;"                     \
874         "tftp $fdtaddr $fdtfile;"                       \
875         "bootm $loadaddr - $fdtaddr"
876
877 #define CONFIG_NFSBOOTCOMMAND                   \
878         "setenv bootargs root=/dev/nfs rw "     \
879         "nfsroot=$serverip:$rootpath "          \
880         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
881         "console=$consoledev,$baudrate $othbootargs;"   \
882         "tftp $loadaddr $bootfile;"             \
883         "tftp $fdtaddr $fdtfile;"               \
884         "bootm $loadaddr - $fdtaddr"
885
886 #define CONFIG_RAMBOOTCOMMAND                           \
887         "setenv bootargs root=/dev/ram rw "             \
888         "console=$consoledev,$baudrate $othbootargs;"   \
889         "tftp $ramdiskaddr $ramdiskfile;"               \
890         "tftp $loadaddr $bootfile;"                     \
891         "tftp $fdtaddr $fdtfile;"                       \
892         "bootm $loadaddr $ramdiskaddr $fdtaddr"
893
894 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
895
896 #ifdef CONFIG_SECURE_BOOT
897 #include <asm/fsl_secure_boot.h>
898 #define CONFIG_CMD_BLOB
899 #undef CONFIG_CMD_USB
900 #endif
901
902 #endif  /* __T2080RDB_H */