include/configs/T208xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T2080 RDB/PCIe board configuration file
   9  */
  10
  11 #ifndef __T2080RDB_H
  12 #define __T2080RDB_H
  13
  14 #include <linux/stringify.h>
  15
  16 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  17
  18 /* High Level Configuration Options */
  19 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
  20
  21 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  22 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  23
  24 #ifdef CONFIG_RAMBOOT_PBL
  25 #define RESET_VECTOR_OFFSET             0x27FFC
  26 #define BOOT_PAGE_OFFSET                0x27000
  27
  28 #ifdef CONFIG_MTD_RAW_NAND
  29 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  30 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  31 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  32 #endif
  33
  34 #ifdef CONFIG_SPIFLASH
  35 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  36 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
  37 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
  38 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
  39 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
  40 #endif
  41
  42 #ifdef CONFIG_SDCARD
  43 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  44 #define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
  45 #define CONFIG_SYS_MMC_U_BOOT_DST      (0x00200000)
  46 #define CONFIG_SYS_MMC_U_BOOT_START    (0x00200000)
  47 #define CONFIG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
  48 #endif
  49
  50 #endif /* CONFIG_RAMBOOT_PBL */
  51
  52 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  53 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  54 /* Set 1M boot space */
  55 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  56 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  57                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  58 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  59 #endif
  60
  61 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  62 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  63 #endif
  64
  65 /*
  66  * These can be toggled for performance analysis, otherwise use default.
  67  */
  68 #define CONFIG_SYS_CACHE_STASHING
  69 #ifdef CONFIG_DDR_ECC
  70 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  71 #endif
  72
  73 /*
  74  * Config the L3 Cache as L3 SRAM
  75  */
  76 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
  77 #define CONFIG_SYS_L3_SIZE              (512 << 10)
  78 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
  79
  80 #define CONFIG_SYS_DCSRBAR      0xf0000000
  81 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  82
  83 /* EEPROM */
  84 #define CONFIG_SYS_I2C_EEPROM_NXID
  85 #define CONFIG_SYS_EEPROM_BUS_NUM       0
  86
  87 /*
  88  * DDR Setup
  89  */
  90 #define CONFIG_VERY_BIG_RAM
  91 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  92 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  93 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
  94 #define SPD_EEPROM_ADDRESS1     0x51
  95 #define SPD_EEPROM_ADDRESS2     0x52
  96 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  97 #define CTRL_INTLV_PREFERED     cacheline
  98
  99 /*
 100  * IFC Definitions
 101  */
 102 #define CONFIG_SYS_FLASH_BASE           0xe8000000
 103 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 104 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 105 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 106                                 CSPR_PORT_SIZE_16 | \
 107                                 CSPR_MSEL_NOR | \
 108                                 CSPR_V)
 109 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 110
 111 /* NOR Flash Timing Params */
 112 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 113
 114 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 115                                 FTIM0_NOR_TEADC(0x5) | \
 116                                 FTIM0_NOR_TEAHC(0x5))
 117 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 118                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 119                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 120 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 121                                 FTIM2_NOR_TCH(0x4) | \
 122                                 FTIM2_NOR_TWPH(0x0E) | \
 123                                 FTIM2_NOR_TWP(0x1c))
 124 #define CONFIG_SYS_NOR_FTIM3    0x0
 125
 126 #define CONFIG_SYS_FLASH_QUIET_TEST
 127 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 128
 129 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 130 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 131 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 132 #define CONFIG_SYS_FLASH_EMPTY_INFO
 133 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS }
 134
 135 /* CPLD on IFC */
 136 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 137 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 138 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 139 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 140                                 | CSPR_PORT_SIZE_8 \
 141                                 | CSPR_MSEL_GPCM \
 142                                 | CSPR_V)
 143 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 144 #define CONFIG_SYS_CSOR2        0x0
 145
 146 /* CPLD Timing parameters for IFC CS2 */
 147 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 148                                         FTIM0_GPCM_TEADC(0x0e) | \
 149                                         FTIM0_GPCM_TEAHC(0x0e))
 150 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 151                                         FTIM1_GPCM_TRAD(0x1f))
 152 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 153                                         FTIM2_GPCM_TCH(0x8) | \
 154                                         FTIM2_GPCM_TWP(0x1f))
 155 #define CONFIG_SYS_CS2_FTIM3            0x0
 156
 157 /* NAND Flash on IFC */
 158 #define CONFIG_SYS_NAND_BASE            0xff800000
 159 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 160
 161 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 162 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 163                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 164                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 165                                 | CSPR_V)
 166 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 167
 168 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 169                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 170                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 171                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 172                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 173                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 174                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 175
 176 /* ONFI NAND Flash mode0 Timing Params */
 177 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 178                                         FTIM0_NAND_TWP(0x18)    | \
 179                                         FTIM0_NAND_TWCHT(0x07)  | \
 180                                         FTIM0_NAND_TWH(0x0a))
 181 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 182                                         FTIM1_NAND_TWBE(0x39)   | \
 183                                         FTIM1_NAND_TRR(0x0e)    | \
 184                                         FTIM1_NAND_TRP(0x18))
 185 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 186                                         FTIM2_NAND_TREH(0x0a)   | \
 187                                         FTIM2_NAND_TWHRE(0x1e))
 188 #define CONFIG_SYS_NAND_FTIM3           0x0
 189
 190 #define CONFIG_SYS_NAND_DDR_LAW         11
 191 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 192 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 193
 194 #if defined(CONFIG_MTD_RAW_NAND)
 195 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 196 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 197 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 198 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 199 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 200 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 201 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 202 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 203 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 204 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 205 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 206 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 207 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 208 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 209 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 210 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 211 #else
 212 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 213 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 214 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 215 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 216 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 217 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 218 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 219 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 220 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 221 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 222 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 223 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 224 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 225 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 226 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 227 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 228 #endif
 229
 230 #if defined(CONFIG_RAMBOOT_PBL)
 231 #define CONFIG_SYS_RAMBOOT
 232 #endif
 233
 234 #define CONFIG_HWCONFIG
 235
 236 /* define to use L1 as initial stack */
 237 #define CONFIG_L1_INIT_RAM
 238 #define CONFIG_SYS_INIT_RAM_LOCK
 239 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 240 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 241 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 242 /* The assembler doesn't like typecast */
 243 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 244                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 245                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 246 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 247 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 248 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 249
 250 /*
 251  * Serial Port
 252  */
 253 #define CONFIG_SYS_NS16550_SERIAL
 254 #define CONFIG_SYS_NS16550_REG_SIZE     1
 255 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 256 #define CONFIG_SYS_BAUDRATE_TABLE       \
 257         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 258 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 259 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 260 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 261 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 262
 263 /*
 264  * I2C
 265  */
 266
 267 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 268 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 269 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 270 #define I2C_MUX_CH_DEFAULT      0x8
 271
 272 #define I2C_MUX_CH_VOL_MONITOR  0xa
 273
 274 /* The lowest and highest voltage allowed for T208xRDB */
 275 #define VDD_MV_MIN                      819
 276 #define VDD_MV_MAX                      1212
 277
 278 /*
 279  * RapidIO
 280  */
 281 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 282 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 283 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 284 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 285 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 286 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 287 /*
 288  * for slave u-boot IMAGE instored in master memory space,
 289  * PHYS must be aligned based on the SIZE
 290  */
 291 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 292 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 293 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 294 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 295 /*
 296  * for slave UCODE and ENV instored in master memory space,
 297  * PHYS must be aligned based on the SIZE
 298  */
 299 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 300 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 301 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 302
 303 /* slave core release by master*/
 304 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 305 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 306
 307 /*
 308  * SRIO_PCIE_BOOT - SLAVE
 309  */
 310 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 311 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 312 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 313                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 314 #endif
 315
 316 /*
 317  * eSPI - Enhanced SPI
 318  */
 319
 320 /*
 321  * General PCI
 322  * Memory space is mapped 1-1, but I/O space must start from 0.
 323  */
 324 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 325 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 326 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 327 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 328 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 329
 330 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 331 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 332 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 333 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 334 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 335
 336 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 337 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 338 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 339 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 340 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 341
 342 /* controller 4, Base address 203000 */
 343 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 344 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 345 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 346
 347 /* Qman/Bman */
 348 #ifndef CONFIG_NOBQFMAN
 349 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 350 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 351 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 352 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 353 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 354 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 355 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 356 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 357 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 358                                         CONFIG_SYS_BMAN_CENA_SIZE)
 359 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 360 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 361 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 362 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 363 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 364 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 365 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 366 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 367 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 368 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 369 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 370                                         CONFIG_SYS_QMAN_CENA_SIZE)
 371 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 372 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 373
 374 #define CONFIG_SYS_DPAA_FMAN
 375 #define CONFIG_SYS_DPAA_PME
 376 #define CONFIG_SYS_PMAN
 377 #define CONFIG_SYS_DPAA_DCE
 378 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 379 #define CONFIG_SYS_INTERLAKEN
 380
 381 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 382 #endif /* CONFIG_NOBQFMAN */
 383
 384 #ifdef CONFIG_SYS_DPAA_FMAN
 385 #define RGMII_PHY1_ADDR         0x01  /* RealTek RTL8211E */
 386 #define RGMII_PHY2_ADDR         0x02
 387 #define CORTINA_PHY_ADDR1       0x0c  /* Cortina CS4315 */
 388 #define CORTINA_PHY_ADDR2       0x0d
 389 /* Aquantia AQ1202 10G Base-T used by board revisions up to C */
 390 #define FM1_10GEC3_PHY_ADDR     0x00
 391 #define FM1_10GEC4_PHY_ADDR     0x01
 392 /* Aquantia AQR113C 10G Base-T used by board revisions D and up */
 393 #define AQR113C_PHY_ADDR1       0x00
 394 #define AQR113C_PHY_ADDR2       0x08
 395 #endif
 396
 397 /*
 398  * USB
 399  */
 400
 401 /*
 402  * SDHC
 403  */
 404 #ifdef CONFIG_MMC
 405 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 406 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 407 #endif
 408
 409 /*
 410  * Dynamic MTD Partition support with mtdparts
 411  */
 412
 413 /*
 414  * Environment
 415  */
 416
 417 /*
 418  * Miscellaneous configurable options
 419  */
 420
 421 /*
 422  * For booting Linux, the board info and command line data
 423  * have to be in the first 64 MB of memory, since this is
 424  * the maximum mapped by the Linux kernel during initialization.
 425  */
 426 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 427 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 428
 429 /*
 430  * Environment Configuration
 431  */
 432 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 433 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 434
 435 #define __USB_PHY_TYPE          utmi
 436
 437 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 438         "hwconfig=fsl_ddr:"                                     \
 439         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 440         "bank_intlv=auto;"                                      \
 441         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 442         "netdev=eth0\0"                                         \
 443         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 444         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 445         "tftpflash=tftpboot $loadaddr $uboot && "               \
 446         "protect off $ubootaddr +$filesize && "                 \
 447         "erase $ubootaddr +$filesize && "                       \
 448         "cp.b $loadaddr $ubootaddr $filesize && "               \
 449         "protect on $ubootaddr +$filesize && "                  \
 450         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 451         "consoledev=ttyS0\0"                                    \
 452         "ramdiskaddr=2000000\0"                                 \
 453         "ramdiskfile=t2080rdb/ramdisk.uboot\0"                  \
 454         "fdtaddr=1e00000\0"                                     \
 455         "fdtfile=t2080rdb/t2080rdb.dtb\0"                       \
 456         "bdev=sda3\0"
 457
 458 /*
 459  * For emulation this causes u-boot to jump to the start of the
 460  * proof point app code automatically
 461  */
 462 #define PROOF_POINTS                            \
 463         "setenv bootargs root=/dev/$bdev rw "           \
 464         "console=$consoledev,$baudrate $othbootargs;"   \
 465         "cpu 1 release 0x29000000 - - -;"               \
 466         "cpu 2 release 0x29000000 - - -;"               \
 467         "cpu 3 release 0x29000000 - - -;"               \
 468         "cpu 4 release 0x29000000 - - -;"               \
 469         "cpu 5 release 0x29000000 - - -;"               \
 470         "cpu 6 release 0x29000000 - - -;"               \
 471         "cpu 7 release 0x29000000 - - -;"               \
 472         "go 0x29000000"
 473
 474 #define HVBOOT                          \
 475         "setenv bootargs config-addr=0x60000000; "      \
 476         "bootm 0x01000000 - 0x00f00000"
 477
 478 #define ALU                             \
 479         "setenv bootargs root=/dev/$bdev rw "           \
 480         "console=$consoledev,$baudrate $othbootargs;"   \
 481         "cpu 1 release 0x01000000 - - -;"               \
 482         "cpu 2 release 0x01000000 - - -;"               \
 483         "cpu 3 release 0x01000000 - - -;"               \
 484         "cpu 4 release 0x01000000 - - -;"               \
 485         "cpu 5 release 0x01000000 - - -;"               \
 486         "cpu 6 release 0x01000000 - - -;"               \
 487         "cpu 7 release 0x01000000 - - -;"               \
 488         "go 0x01000000"
 489
 490 #include <asm/fsl_secure_boot.h>
 491
 492 #endif  /* __T2080RDB_H */