1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
7 * T2080 RDB/PCIe board configuration file
13 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
14 #define CONFIG_FSL_SATA_V2
16 /* High Level Configuration Options */
17 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
18 #define CONFIG_MP /* support multiple processors */
19 #define CONFIG_ENABLE_36BIT_PHYS
21 #ifdef CONFIG_PHYS_64BIT
22 #define CONFIG_ADDR_MAP 1
23 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
26 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
27 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
28 #define CONFIG_ENV_OVERWRITE
30 #ifdef CONFIG_RAMBOOT_PBL
31 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
33 #define CONFIG_SPL_FLUSH_IMAGE
34 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
35 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
36 #define CONFIG_SPL_PAD_TO 0x40000
37 #define CONFIG_SPL_MAX_SIZE 0x28000
38 #define RESET_VECTOR_OFFSET 0x27FFC
39 #define BOOT_PAGE_OFFSET 0x27000
40 #ifdef CONFIG_SPL_BUILD
41 #define CONFIG_SPL_SKIP_RELOCATE
42 #define CONFIG_SPL_COMMON_INIT_DDR
43 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
47 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
48 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
49 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
50 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
51 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
52 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg
53 #define CONFIG_SPL_NAND_BOOT
56 #ifdef CONFIG_SPIFLASH
57 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
58 #define CONFIG_SPL_SPI_FLASH_MINIMAL
59 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
60 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
62 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
63 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
64 #ifndef CONFIG_SPL_BUILD
65 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
67 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg
68 #define CONFIG_SPL_SPI_BOOT
72 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
73 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
74 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
75 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
76 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
77 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
78 #ifndef CONFIG_SPL_BUILD
79 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
81 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg
82 #define CONFIG_SPL_MMC_BOOT
85 #endif /* CONFIG_RAMBOOT_PBL */
87 #define CONFIG_SRIO_PCIE_BOOT_MASTER
88 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
89 /* Set 1M boot space */
90 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
91 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
92 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
93 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
96 #ifndef CONFIG_RESET_VECTOR_ADDRESS
97 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
101 * These can be toggled for performance analysis, otherwise use default.
103 #define CONFIG_SYS_CACHE_STASHING
104 #define CONFIG_BTB /* toggle branch predition */
105 #define CONFIG_DDR_ECC
106 #ifdef CONFIG_DDR_ECC
107 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
108 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
111 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
112 #define CONFIG_SYS_MEMTEST_END 0x00400000
114 #ifdef CONFIG_MTD_NOR_FLASH
115 #define CONFIG_FLASH_CFI_DRIVER
116 #define CONFIG_SYS_FLASH_CFI
117 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
120 #if defined(CONFIG_SPIFLASH)
121 #define CONFIG_SYS_EXTRA_ENV_RELOC
122 #define CONFIG_ENV_SPI_BUS 0
123 #define CONFIG_ENV_SPI_CS 0
124 #define CONFIG_ENV_SPI_MAX_HZ 10000000
125 #define CONFIG_ENV_SPI_MODE 0
126 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
127 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
128 #define CONFIG_ENV_SECT_SIZE 0x10000
129 #elif defined(CONFIG_SDCARD)
130 #define CONFIG_SYS_EXTRA_ENV_RELOC
131 #define CONFIG_SYS_MMC_ENV_DEV 0
132 #define CONFIG_ENV_SIZE 0x2000
133 #define CONFIG_ENV_OFFSET (512 * 0x800)
134 #elif defined(CONFIG_NAND)
135 #define CONFIG_SYS_EXTRA_ENV_RELOC
136 #define CONFIG_ENV_SIZE 0x2000
137 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
138 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
139 #define CONFIG_ENV_ADDR 0xffe20000
140 #define CONFIG_ENV_SIZE 0x2000
141 #elif defined(CONFIG_ENV_IS_NOWHERE)
142 #define CONFIG_ENV_SIZE 0x2000
144 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
145 #define CONFIG_ENV_SIZE 0x2000
146 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
150 unsigned long get_board_sys_clk(void);
151 unsigned long get_board_ddr_clk(void);
154 #define CONFIG_SYS_CLK_FREQ 66660000
155 #define CONFIG_DDR_CLK_FREQ 133330000
158 * Config the L3 Cache as L3 SRAM
160 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
161 #define CONFIG_SYS_L3_SIZE (512 << 10)
162 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
163 #ifdef CONFIG_RAMBOOT_PBL
164 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
166 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
167 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
168 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
169 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
171 #define CONFIG_SYS_DCSRBAR 0xf0000000
172 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
175 #define CONFIG_ID_EEPROM
176 #define CONFIG_SYS_I2C_EEPROM_NXID
177 #define CONFIG_SYS_EEPROM_BUS_NUM 0
178 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
179 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
184 #define CONFIG_VERY_BIG_RAM
185 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
186 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
187 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
188 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
189 #define CONFIG_DDR_SPD
190 #undef CONFIG_FSL_DDR_INTERACTIVE
191 #define CONFIG_SYS_SPD_BUS_NUM 0
192 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
193 #define SPD_EEPROM_ADDRESS1 0x51
194 #define SPD_EEPROM_ADDRESS2 0x52
195 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
196 #define CTRL_INTLV_PREFERED cacheline
201 #define CONFIG_SYS_FLASH_BASE 0xe8000000
202 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
203 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
204 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
205 CSPR_PORT_SIZE_16 | \
208 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
210 /* NOR Flash Timing Params */
211 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
213 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
214 FTIM0_NOR_TEADC(0x5) | \
215 FTIM0_NOR_TEAHC(0x5))
216 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
217 FTIM1_NOR_TRAD_NOR(0x1A) |\
218 FTIM1_NOR_TSEQRAD_NOR(0x13))
219 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
220 FTIM2_NOR_TCH(0x4) | \
221 FTIM2_NOR_TWPH(0x0E) | \
223 #define CONFIG_SYS_NOR_FTIM3 0x0
225 #define CONFIG_SYS_FLASH_QUIET_TEST
226 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
228 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
229 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
230 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
231 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
232 #define CONFIG_SYS_FLASH_EMPTY_INFO
233 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS }
236 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
237 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
238 #define CONFIG_SYS_CSPR2_EXT (0xf)
239 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
243 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
244 #define CONFIG_SYS_CSOR2 0x0
246 /* CPLD Timing parameters for IFC CS2 */
247 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
248 FTIM0_GPCM_TEADC(0x0e) | \
249 FTIM0_GPCM_TEAHC(0x0e))
250 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
251 FTIM1_GPCM_TRAD(0x1f))
252 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
253 FTIM2_GPCM_TCH(0x8) | \
254 FTIM2_GPCM_TWP(0x1f))
255 #define CONFIG_SYS_CS2_FTIM3 0x0
257 /* NAND Flash on IFC */
258 #define CONFIG_NAND_FSL_IFC
259 #define CONFIG_SYS_NAND_BASE 0xff800000
260 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
262 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
263 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
264 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
265 | CSPR_MSEL_NAND /* MSEL = NAND */ \
267 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
269 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
270 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
271 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
272 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
273 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
274 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
275 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
277 #define CONFIG_SYS_NAND_ONFI_DETECTION
279 /* ONFI NAND Flash mode0 Timing Params */
280 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
281 FTIM0_NAND_TWP(0x18) | \
282 FTIM0_NAND_TWCHT(0x07) | \
283 FTIM0_NAND_TWH(0x0a))
284 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
285 FTIM1_NAND_TWBE(0x39) | \
286 FTIM1_NAND_TRR(0x0e) | \
287 FTIM1_NAND_TRP(0x18))
288 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
289 FTIM2_NAND_TREH(0x0a) | \
290 FTIM2_NAND_TWHRE(0x1e))
291 #define CONFIG_SYS_NAND_FTIM3 0x0
293 #define CONFIG_SYS_NAND_DDR_LAW 11
294 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
295 #define CONFIG_SYS_MAX_NAND_DEVICE 1
296 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
298 #if defined(CONFIG_NAND)
299 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
300 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
301 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
302 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
303 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
304 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
305 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
306 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
307 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
308 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
309 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
310 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
311 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
312 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
313 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
314 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
316 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
317 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
318 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
319 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
320 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
321 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
322 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
323 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
324 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
325 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
326 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
327 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
328 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
329 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
330 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
331 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
334 #if defined(CONFIG_RAMBOOT_PBL)
335 #define CONFIG_SYS_RAMBOOT
338 #ifdef CONFIG_SPL_BUILD
339 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
341 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
344 #define CONFIG_MISC_INIT_R
345 #define CONFIG_HWCONFIG
347 /* define to use L1 as initial stack */
348 #define CONFIG_L1_INIT_RAM
349 #define CONFIG_SYS_INIT_RAM_LOCK
350 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
351 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
352 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
353 /* The assembler doesn't like typecast */
354 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
355 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
356 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
357 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
358 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
359 GENERATED_GBL_DATA_SIZE)
360 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
361 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
362 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
367 #define CONFIG_SYS_NS16550_SERIAL
368 #define CONFIG_SYS_NS16550_REG_SIZE 1
369 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
370 #define CONFIG_SYS_BAUDRATE_TABLE \
371 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
372 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
373 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
374 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
375 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
380 #define CONFIG_SYS_I2C
381 #define CONFIG_SYS_I2C_FSL
382 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
383 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
384 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
385 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
386 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
387 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
388 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
389 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
390 #define CONFIG_SYS_FSL_I2C_SPEED 100000
391 #define CONFIG_SYS_FSL_I2C2_SPEED 100000
392 #define CONFIG_SYS_FSL_I2C3_SPEED 100000
393 #define CONFIG_SYS_FSL_I2C4_SPEED 100000
394 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
395 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
396 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
397 #define I2C_MUX_CH_DEFAULT 0x8
399 #define I2C_MUX_CH_VOL_MONITOR 0xa
401 #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv"
402 #ifndef CONFIG_SPL_BUILD
405 #define CONFIG_VOL_MONITOR_IR36021_SET
406 #define CONFIG_VOL_MONITOR_IR36021_READ
407 /* The lowest and highest voltage allowed for T208xRDB */
408 #define VDD_MV_MIN 819
409 #define VDD_MV_MAX 1212
414 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
415 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
416 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
417 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
418 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
419 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
421 * for slave u-boot IMAGE instored in master memory space,
422 * PHYS must be aligned based on the SIZE
424 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
425 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
426 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
427 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
429 * for slave UCODE and ENV instored in master memory space,
430 * PHYS must be aligned based on the SIZE
432 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
433 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
434 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
436 /* slave core release by master*/
437 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
438 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
441 * SRIO_PCIE_BOOT - SLAVE
443 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
444 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
445 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
446 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
450 * eSPI - Enhanced SPI
452 #ifdef CONFIG_SPI_FLASH
453 #define CONFIG_SPI_FLASH_BAR
454 #define CONFIG_SF_DEFAULT_SPEED 10000000
455 #define CONFIG_SF_DEFAULT_MODE 0
460 * Memory space is mapped 1-1, but I/O space must start from 0.
462 #define CONFIG_PCIE1 /* PCIE controller 1 */
463 #define CONFIG_PCIE2 /* PCIE controller 2 */
464 #define CONFIG_PCIE3 /* PCIE controller 3 */
465 #define CONFIG_PCIE4 /* PCIE controller 4 */
466 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
467 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
468 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
469 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
470 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
471 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
472 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
473 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
474 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
475 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
476 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
478 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
479 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
480 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
481 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
482 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
483 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
484 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
485 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
486 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
488 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
489 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
490 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
491 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
492 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
493 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
494 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
495 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
496 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
498 /* controller 4, Base address 203000 */
499 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
500 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
501 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
502 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
503 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
504 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
505 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
508 #define CONFIG_PCI_INDIRECT_BRIDGE
509 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */
510 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
514 #ifndef CONFIG_NOBQFMAN
515 #define CONFIG_SYS_BMAN_NUM_PORTALS 18
516 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
517 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
518 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
519 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
520 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
521 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
522 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
523 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
524 CONFIG_SYS_BMAN_CENA_SIZE)
525 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
526 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
527 #define CONFIG_SYS_QMAN_NUM_PORTALS 18
528 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
529 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
530 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
531 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
532 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
533 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
534 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
535 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
536 CONFIG_SYS_QMAN_CENA_SIZE)
537 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
538 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
540 #define CONFIG_SYS_DPAA_FMAN
541 #define CONFIG_SYS_DPAA_PME
542 #define CONFIG_SYS_PMAN
543 #define CONFIG_SYS_DPAA_DCE
544 #define CONFIG_SYS_DPAA_RMAN /* RMan */
545 #define CONFIG_SYS_INTERLAKEN
547 /* Default address of microcode for the Linux Fman driver */
548 #if defined(CONFIG_SPIFLASH)
550 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
551 * env, so we got 0x110000.
553 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
554 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
555 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
556 #define CONFIG_CORTINA_FW_ADDR 0x120000
558 #elif defined(CONFIG_SDCARD)
560 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
561 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
562 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
564 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
565 #define CONFIG_SYS_CORTINA_FW_IN_MMC
566 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
567 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0)
569 #elif defined(CONFIG_NAND)
570 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
571 #define CONFIG_SYS_CORTINA_FW_IN_NAND
572 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
573 #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
574 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
576 * Slave has no ucode locally, it can fetch this from remote. When implementing
577 * in two corenet boards, slave's ucode could be stored in master's memory
578 * space, the address can be mapped from slave TLB->slave LAW->
579 * slave SRIO or PCIE outbound window->master inbound window->
580 * master LAW->the ucode address in master's memory space.
582 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
583 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE
584 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
585 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000
587 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
588 #define CONFIG_SYS_CORTINA_FW_IN_NOR
589 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
590 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000
592 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
593 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
594 #endif /* CONFIG_NOBQFMAN */
596 #ifdef CONFIG_SYS_DPAA_FMAN
597 #define CONFIG_FMAN_ENET
598 #define CONFIG_PHYLIB_10G
599 #define CONFIG_PHY_AQUANTIA
600 #define CONFIG_PHY_CORTINA
601 #define CONFIG_PHY_REALTEK
602 #define CONFIG_CORTINA_FW_LENGTH 0x40000
603 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
604 #define RGMII_PHY2_ADDR 0x02
605 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */
606 #define CORTINA_PHY_ADDR2 0x0d
607 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */
608 #define FM1_10GEC4_PHY_ADDR 0x01
611 #ifdef CONFIG_FMAN_ENET
612 #define CONFIG_MII /* MII PHY management */
613 #define CONFIG_ETHPRIME "FM1@DTSEC3"
619 #ifdef CONFIG_FSL_SATA_V2
620 #define CONFIG_SYS_SATA_MAX_DEVICE 2
622 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
623 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
625 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
626 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
633 #ifdef CONFIG_USB_EHCI_HCD
634 #define CONFIG_USB_EHCI_FSL
635 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
636 #define CONFIG_HAS_FSL_DR_USB
643 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
644 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
645 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
649 * Dynamic MTD Partition support with mtdparts
651 #ifdef CONFIG_MTD_NOR_FLASH
652 #define CONFIG_MTD_DEVICE
653 #define CONFIG_MTD_PARTITIONS
654 #define CONFIG_FLASH_CFI_MTD
662 * Miscellaneous configurable options
664 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
667 * For booting Linux, the board info and command line data
668 * have to be in the first 64 MB of memory, since this is
669 * the maximum mapped by the Linux kernel during initialization.
671 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
672 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
674 #ifdef CONFIG_CMD_KGDB
675 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
676 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
680 * Environment Configuration
682 #define CONFIG_ROOTPATH "/opt/nfsroot"
683 #define CONFIG_BOOTFILE "uImage"
684 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
686 /* default location for tftp and bootm */
687 #define CONFIG_LOADADDR 1000000
688 #define __USB_PHY_TYPE utmi
690 #define CONFIG_EXTRA_ENV_SETTINGS \
691 "hwconfig=fsl_ddr:" \
692 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
694 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
696 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
697 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
698 "tftpflash=tftpboot $loadaddr $uboot && " \
699 "protect off $ubootaddr +$filesize && " \
700 "erase $ubootaddr +$filesize && " \
701 "cp.b $loadaddr $ubootaddr $filesize && " \
702 "protect on $ubootaddr +$filesize && " \
703 "cmp.b $loadaddr $ubootaddr $filesize\0" \
704 "consoledev=ttyS0\0" \
705 "ramdiskaddr=2000000\0" \
706 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \
707 "fdtaddr=1e00000\0" \
708 "fdtfile=t2080rdb/t2080rdb.dtb\0" \
712 * For emulation this causes u-boot to jump to the start of the
713 * proof point app code automatically
715 #define CONFIG_PROOF_POINTS \
716 "setenv bootargs root=/dev/$bdev rw " \
717 "console=$consoledev,$baudrate $othbootargs;" \
718 "cpu 1 release 0x29000000 - - -;" \
719 "cpu 2 release 0x29000000 - - -;" \
720 "cpu 3 release 0x29000000 - - -;" \
721 "cpu 4 release 0x29000000 - - -;" \
722 "cpu 5 release 0x29000000 - - -;" \
723 "cpu 6 release 0x29000000 - - -;" \
724 "cpu 7 release 0x29000000 - - -;" \
727 #define CONFIG_HVBOOT \
728 "setenv bootargs config-addr=0x60000000; " \
729 "bootm 0x01000000 - 0x00f00000"
732 "setenv bootargs root=/dev/$bdev rw " \
733 "console=$consoledev,$baudrate $othbootargs;" \
734 "cpu 1 release 0x01000000 - - -;" \
735 "cpu 2 release 0x01000000 - - -;" \
736 "cpu 3 release 0x01000000 - - -;" \
737 "cpu 4 release 0x01000000 - - -;" \
738 "cpu 5 release 0x01000000 - - -;" \
739 "cpu 6 release 0x01000000 - - -;" \
740 "cpu 7 release 0x01000000 - - -;" \
743 #define CONFIG_LINUX \
744 "setenv bootargs root=/dev/ram rw " \
745 "console=$consoledev,$baudrate $othbootargs;" \
746 "setenv ramdiskaddr 0x02000000;" \
747 "setenv fdtaddr 0x00c00000;" \
748 "setenv loadaddr 0x1000000;" \
749 "bootm $loadaddr $ramdiskaddr $fdtaddr"
751 #define CONFIG_HDBOOT \
752 "setenv bootargs root=/dev/$bdev rw " \
753 "console=$consoledev,$baudrate $othbootargs;" \
754 "tftp $loadaddr $bootfile;" \
755 "tftp $fdtaddr $fdtfile;" \
756 "bootm $loadaddr - $fdtaddr"
758 #define CONFIG_NFSBOOTCOMMAND \
759 "setenv bootargs root=/dev/nfs rw " \
760 "nfsroot=$serverip:$rootpath " \
761 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
762 "console=$consoledev,$baudrate $othbootargs;" \
763 "tftp $loadaddr $bootfile;" \
764 "tftp $fdtaddr $fdtfile;" \
765 "bootm $loadaddr - $fdtaddr"
767 #define CONFIG_RAMBOOTCOMMAND \
768 "setenv bootargs root=/dev/ram rw " \
769 "console=$consoledev,$baudrate $othbootargs;" \
770 "tftp $ramdiskaddr $ramdiskfile;" \
771 "tftp $loadaddr $bootfile;" \
772 "tftp $fdtaddr $fdtfile;" \
773 "bootm $loadaddr $ramdiskaddr $fdtaddr"
775 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
777 #include <asm/fsl_secure_boot.h>
779 #endif /* __T2080RDB_H */