1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
8 * T2080 RDB/PCIe board configuration file
14 #include <linux/stringify.h>
16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
17 #define CONFIG_FSL_SATA_V2
19 /* High Level Configuration Options */
20 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
21 #define CONFIG_ENABLE_36BIT_PHYS
23 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
24 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
26 #ifdef CONFIG_RAMBOOT_PBL
27 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
29 #define CONFIG_SPL_FLUSH_IMAGE
30 #define CONFIG_SPL_PAD_TO 0x40000
31 #define CONFIG_SPL_MAX_SIZE 0x28000
32 #define RESET_VECTOR_OFFSET 0x27FFC
33 #define BOOT_PAGE_OFFSET 0x27000
34 #ifdef CONFIG_SPL_BUILD
35 #define CONFIG_SPL_SKIP_RELOCATE
36 #define CONFIG_SPL_COMMON_INIT_DDR
37 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
40 #ifdef CONFIG_MTD_RAW_NAND
41 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
42 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
43 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
44 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
45 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg
48 #ifdef CONFIG_SPIFLASH
49 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
50 #define CONFIG_SPL_SPI_FLASH_MINIMAL
51 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
52 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
53 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
54 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
55 #ifndef CONFIG_SPL_BUILD
56 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
58 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg
62 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
63 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
64 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
65 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
66 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
67 #ifndef CONFIG_SPL_BUILD
68 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
70 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg
73 #endif /* CONFIG_RAMBOOT_PBL */
75 #define CONFIG_SRIO_PCIE_BOOT_MASTER
76 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
77 /* Set 1M boot space */
78 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
79 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
80 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
81 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
84 #ifndef CONFIG_RESET_VECTOR_ADDRESS
85 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
89 * These can be toggled for performance analysis, otherwise use default.
91 #define CONFIG_SYS_CACHE_STASHING
92 #define CONFIG_BTB /* toggle branch predition */
93 #define CONFIG_DDR_ECC
95 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
96 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
100 unsigned long get_board_sys_clk(void);
103 #define CONFIG_SYS_CLK_FREQ 66660000
106 * Config the L3 Cache as L3 SRAM
108 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
109 #define CONFIG_SYS_L3_SIZE (512 << 10)
110 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
111 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
112 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
113 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
114 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
116 #define CONFIG_SYS_DCSRBAR 0xf0000000
117 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
120 #define CONFIG_SYS_I2C_EEPROM_NXID
121 #define CONFIG_SYS_EEPROM_BUS_NUM 0
126 #define CONFIG_VERY_BIG_RAM
127 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
128 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
129 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
130 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
131 #define CONFIG_DDR_SPD
132 #define CONFIG_SYS_SPD_BUS_NUM 0
133 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
134 #define SPD_EEPROM_ADDRESS1 0x51
135 #define SPD_EEPROM_ADDRESS2 0x52
136 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
137 #define CTRL_INTLV_PREFERED cacheline
142 #define CONFIG_SYS_FLASH_BASE 0xe8000000
143 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
144 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
145 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
146 CSPR_PORT_SIZE_16 | \
149 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
151 /* NOR Flash Timing Params */
152 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
154 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
155 FTIM0_NOR_TEADC(0x5) | \
156 FTIM0_NOR_TEAHC(0x5))
157 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
158 FTIM1_NOR_TRAD_NOR(0x1A) |\
159 FTIM1_NOR_TSEQRAD_NOR(0x13))
160 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
161 FTIM2_NOR_TCH(0x4) | \
162 FTIM2_NOR_TWPH(0x0E) | \
164 #define CONFIG_SYS_NOR_FTIM3 0x0
166 #define CONFIG_SYS_FLASH_QUIET_TEST
167 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
169 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
170 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
171 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
172 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
173 #define CONFIG_SYS_FLASH_EMPTY_INFO
174 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS }
177 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
178 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
179 #define CONFIG_SYS_CSPR2_EXT (0xf)
180 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
184 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
185 #define CONFIG_SYS_CSOR2 0x0
187 /* CPLD Timing parameters for IFC CS2 */
188 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
189 FTIM0_GPCM_TEADC(0x0e) | \
190 FTIM0_GPCM_TEAHC(0x0e))
191 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
192 FTIM1_GPCM_TRAD(0x1f))
193 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
194 FTIM2_GPCM_TCH(0x8) | \
195 FTIM2_GPCM_TWP(0x1f))
196 #define CONFIG_SYS_CS2_FTIM3 0x0
198 /* NAND Flash on IFC */
199 #define CONFIG_NAND_FSL_IFC
200 #define CONFIG_SYS_NAND_BASE 0xff800000
201 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
203 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
204 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
205 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
206 | CSPR_MSEL_NAND /* MSEL = NAND */ \
208 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
210 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
211 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
212 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
213 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
214 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
215 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
216 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
218 #define CONFIG_SYS_NAND_ONFI_DETECTION
220 /* ONFI NAND Flash mode0 Timing Params */
221 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
222 FTIM0_NAND_TWP(0x18) | \
223 FTIM0_NAND_TWCHT(0x07) | \
224 FTIM0_NAND_TWH(0x0a))
225 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
226 FTIM1_NAND_TWBE(0x39) | \
227 FTIM1_NAND_TRR(0x0e) | \
228 FTIM1_NAND_TRP(0x18))
229 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
230 FTIM2_NAND_TREH(0x0a) | \
231 FTIM2_NAND_TWHRE(0x1e))
232 #define CONFIG_SYS_NAND_FTIM3 0x0
234 #define CONFIG_SYS_NAND_DDR_LAW 11
235 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
236 #define CONFIG_SYS_MAX_NAND_DEVICE 1
237 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
239 #if defined(CONFIG_MTD_RAW_NAND)
240 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
241 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
242 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
243 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
244 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
245 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
246 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
247 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
248 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
249 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
250 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
251 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
252 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
253 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
254 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
255 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
257 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
258 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
259 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
260 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
261 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
262 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
263 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
264 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
265 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
266 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
267 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
268 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
269 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
270 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
271 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
272 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
275 #if defined(CONFIG_RAMBOOT_PBL)
276 #define CONFIG_SYS_RAMBOOT
279 #ifdef CONFIG_SPL_BUILD
280 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
282 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
285 #define CONFIG_HWCONFIG
287 /* define to use L1 as initial stack */
288 #define CONFIG_L1_INIT_RAM
289 #define CONFIG_SYS_INIT_RAM_LOCK
290 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
291 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
292 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
293 /* The assembler doesn't like typecast */
294 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
295 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
296 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
297 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
298 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
299 GENERATED_GBL_DATA_SIZE)
300 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
301 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
302 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
307 #define CONFIG_SYS_NS16550_SERIAL
308 #define CONFIG_SYS_NS16550_REG_SIZE 1
309 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
310 #define CONFIG_SYS_BAUDRATE_TABLE \
311 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
312 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
313 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
314 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
315 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
321 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
322 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
323 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
324 #define I2C_MUX_CH_DEFAULT 0x8
326 #define I2C_MUX_CH_VOL_MONITOR 0xa
328 #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv"
329 #ifndef CONFIG_SPL_BUILD
332 #define CONFIG_VOL_MONITOR_IR36021_SET
333 #define CONFIG_VOL_MONITOR_IR36021_READ
334 /* The lowest and highest voltage allowed for T208xRDB */
335 #define VDD_MV_MIN 819
336 #define VDD_MV_MAX 1212
341 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
342 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
343 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
344 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
345 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
346 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
348 * for slave u-boot IMAGE instored in master memory space,
349 * PHYS must be aligned based on the SIZE
351 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
352 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
353 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
354 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
356 * for slave UCODE and ENV instored in master memory space,
357 * PHYS must be aligned based on the SIZE
359 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
360 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
361 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
363 /* slave core release by master*/
364 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
365 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
368 * SRIO_PCIE_BOOT - SLAVE
370 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
371 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
372 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
373 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
377 * eSPI - Enhanced SPI
382 * Memory space is mapped 1-1, but I/O space must start from 0.
384 #define CONFIG_PCIE1 /* PCIE controller 1 */
385 #define CONFIG_PCIE2 /* PCIE controller 2 */
386 #define CONFIG_PCIE3 /* PCIE controller 3 */
387 #define CONFIG_PCIE4 /* PCIE controller 4 */
388 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
389 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
390 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
391 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
392 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
393 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
395 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
396 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
397 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
398 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
399 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
401 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
402 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
403 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
404 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
405 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
407 /* controller 4, Base address 203000 */
408 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
409 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
410 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
413 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
417 #ifndef CONFIG_NOBQFMAN
418 #define CONFIG_SYS_BMAN_NUM_PORTALS 18
419 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
420 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
421 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
422 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
423 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
424 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
425 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
426 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
427 CONFIG_SYS_BMAN_CENA_SIZE)
428 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
429 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
430 #define CONFIG_SYS_QMAN_NUM_PORTALS 18
431 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
432 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
433 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
434 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
435 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
436 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
437 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
438 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
439 CONFIG_SYS_QMAN_CENA_SIZE)
440 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
441 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
443 #define CONFIG_SYS_DPAA_FMAN
444 #define CONFIG_SYS_DPAA_PME
445 #define CONFIG_SYS_PMAN
446 #define CONFIG_SYS_DPAA_DCE
447 #define CONFIG_SYS_DPAA_RMAN /* RMan */
448 #define CONFIG_SYS_INTERLAKEN
450 /* Default address of microcode for the Linux Fman driver */
451 #if defined(CONFIG_SPIFLASH)
453 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
454 * env, so we got 0x110000.
456 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
458 #elif defined(CONFIG_SDCARD)
460 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
461 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
462 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
464 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
466 #elif defined(CONFIG_MTD_RAW_NAND)
467 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
468 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
470 * Slave has no ucode locally, it can fetch this from remote. When implementing
471 * in two corenet boards, slave's ucode could be stored in master's memory
472 * space, the address can be mapped from slave TLB->slave LAW->
473 * slave SRIO or PCIE outbound window->master inbound window->
474 * master LAW->the ucode address in master's memory space.
476 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
478 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
480 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
481 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
482 #endif /* CONFIG_NOBQFMAN */
484 #ifdef CONFIG_SYS_DPAA_FMAN
485 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
486 #define RGMII_PHY2_ADDR 0x02
487 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */
488 #define CORTINA_PHY_ADDR2 0x0d
489 /* Aquantia AQ1202 10G Base-T used by board revisions up to C */
490 #define FM1_10GEC3_PHY_ADDR 0x00
491 #define FM1_10GEC4_PHY_ADDR 0x01
492 /* Aquantia AQR113C 10G Base-T used by board revisions D and up */
493 #define AQR113C_PHY_ADDR1 0x00
494 #define AQR113C_PHY_ADDR2 0x08
497 #ifdef CONFIG_FMAN_ENET
498 #define CONFIG_ETHPRIME "FM1@DTSEC3"
504 #ifdef CONFIG_FSL_SATA_V2
505 #define CONFIG_SYS_SATA_MAX_DEVICE 2
507 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
508 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
510 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
511 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
518 #ifdef CONFIG_USB_EHCI_HCD
519 #define CONFIG_USB_EHCI_FSL
520 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
521 #define CONFIG_HAS_FSL_DR_USB
528 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
529 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
533 * Dynamic MTD Partition support with mtdparts
541 * Miscellaneous configurable options
543 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
546 * For booting Linux, the board info and command line data
547 * have to be in the first 64 MB of memory, since this is
548 * the maximum mapped by the Linux kernel during initialization.
550 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
551 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
553 #ifdef CONFIG_CMD_KGDB
554 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
555 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
559 * Environment Configuration
561 #define CONFIG_ROOTPATH "/opt/nfsroot"
562 #define CONFIG_BOOTFILE "uImage"
563 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
565 /* default location for tftp and bootm */
566 #define CONFIG_LOADADDR 1000000
567 #define __USB_PHY_TYPE utmi
569 #define CONFIG_EXTRA_ENV_SETTINGS \
570 "hwconfig=fsl_ddr:" \
571 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
573 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
575 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
576 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
577 "tftpflash=tftpboot $loadaddr $uboot && " \
578 "protect off $ubootaddr +$filesize && " \
579 "erase $ubootaddr +$filesize && " \
580 "cp.b $loadaddr $ubootaddr $filesize && " \
581 "protect on $ubootaddr +$filesize && " \
582 "cmp.b $loadaddr $ubootaddr $filesize\0" \
583 "consoledev=ttyS0\0" \
584 "ramdiskaddr=2000000\0" \
585 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \
586 "fdtaddr=1e00000\0" \
587 "fdtfile=t2080rdb/t2080rdb.dtb\0" \
591 * For emulation this causes u-boot to jump to the start of the
592 * proof point app code automatically
594 #define PROOF_POINTS \
595 "setenv bootargs root=/dev/$bdev rw " \
596 "console=$consoledev,$baudrate $othbootargs;" \
597 "cpu 1 release 0x29000000 - - -;" \
598 "cpu 2 release 0x29000000 - - -;" \
599 "cpu 3 release 0x29000000 - - -;" \
600 "cpu 4 release 0x29000000 - - -;" \
601 "cpu 5 release 0x29000000 - - -;" \
602 "cpu 6 release 0x29000000 - - -;" \
603 "cpu 7 release 0x29000000 - - -;" \
607 "setenv bootargs config-addr=0x60000000; " \
608 "bootm 0x01000000 - 0x00f00000"
611 "setenv bootargs root=/dev/$bdev rw " \
612 "console=$consoledev,$baudrate $othbootargs;" \
613 "cpu 1 release 0x01000000 - - -;" \
614 "cpu 2 release 0x01000000 - - -;" \
615 "cpu 3 release 0x01000000 - - -;" \
616 "cpu 4 release 0x01000000 - - -;" \
617 "cpu 5 release 0x01000000 - - -;" \
618 "cpu 6 release 0x01000000 - - -;" \
619 "cpu 7 release 0x01000000 - - -;" \
622 #define LINUXBOOTCOMMAND \
623 "setenv bootargs root=/dev/ram rw " \
624 "console=$consoledev,$baudrate $othbootargs;" \
625 "setenv ramdiskaddr 0x02000000;" \
626 "setenv fdtaddr 0x00c00000;" \
627 "setenv loadaddr 0x1000000;" \
628 "bootm $loadaddr $ramdiskaddr $fdtaddr"
631 "setenv bootargs root=/dev/$bdev rw " \
632 "console=$consoledev,$baudrate $othbootargs;" \
633 "tftp $loadaddr $bootfile;" \
634 "tftp $fdtaddr $fdtfile;" \
635 "bootm $loadaddr - $fdtaddr"
637 #define NFSBOOTCOMMAND \
638 "setenv bootargs root=/dev/nfs rw " \
639 "nfsroot=$serverip:$rootpath " \
640 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
641 "console=$consoledev,$baudrate $othbootargs;" \
642 "tftp $loadaddr $bootfile;" \
643 "tftp $fdtaddr $fdtfile;" \
644 "bootm $loadaddr - $fdtaddr"
646 #define RAMBOOTCOMMAND \
647 "setenv bootargs root=/dev/ram rw " \
648 "console=$consoledev,$baudrate $othbootargs;" \
649 "tftp $ramdiskaddr $ramdiskfile;" \
650 "tftp $loadaddr $bootfile;" \
651 "tftp $fdtaddr $fdtfile;" \
652 "bootm $loadaddr $ramdiskaddr $fdtaddr"
654 #define CONFIG_BOOTCOMMAND LINUXBOOTCOMMAND
656 #include <asm/fsl_secure_boot.h>
658 #endif /* __T2080RDB_H */