1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
8 * T2080 RDB/PCIe board configuration file
14 #include <linux/stringify.h>
16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
17 #define CONFIG_FSL_SATA_V2
19 /* High Level Configuration Options */
20 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
21 #define CONFIG_ENABLE_36BIT_PHYS
23 #ifdef CONFIG_PHYS_64BIT
24 #define CONFIG_ADDR_MAP 1
25 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
28 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
29 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
30 #define CONFIG_ENV_OVERWRITE
32 #ifdef CONFIG_RAMBOOT_PBL
33 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
35 #define CONFIG_SPL_FLUSH_IMAGE
36 #define CONFIG_SPL_PAD_TO 0x40000
37 #define CONFIG_SPL_MAX_SIZE 0x28000
38 #define RESET_VECTOR_OFFSET 0x27FFC
39 #define BOOT_PAGE_OFFSET 0x27000
40 #ifdef CONFIG_SPL_BUILD
41 #define CONFIG_SPL_SKIP_RELOCATE
42 #define CONFIG_SPL_COMMON_INIT_DDR
43 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
46 #ifdef CONFIG_MTD_RAW_NAND
47 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
48 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
49 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
50 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
51 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg
54 #ifdef CONFIG_SPIFLASH
55 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
56 #define CONFIG_SPL_SPI_FLASH_MINIMAL
57 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
58 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
59 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
60 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
61 #ifndef CONFIG_SPL_BUILD
62 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
64 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg
68 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
69 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
70 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
71 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
72 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
73 #ifndef CONFIG_SPL_BUILD
74 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
76 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg
79 #endif /* CONFIG_RAMBOOT_PBL */
81 #define CONFIG_SRIO_PCIE_BOOT_MASTER
82 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
83 /* Set 1M boot space */
84 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
85 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
86 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
87 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
90 #ifndef CONFIG_RESET_VECTOR_ADDRESS
91 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
95 * These can be toggled for performance analysis, otherwise use default.
97 #define CONFIG_SYS_CACHE_STASHING
98 #define CONFIG_BTB /* toggle branch predition */
99 #define CONFIG_DDR_ECC
100 #ifdef CONFIG_DDR_ECC
101 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
102 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
105 #if defined(CONFIG_SPIFLASH)
106 #elif defined(CONFIG_SDCARD)
107 #define CONFIG_SYS_MMC_ENV_DEV 0
111 unsigned long get_board_sys_clk(void);
112 unsigned long get_board_ddr_clk(void);
115 #define CONFIG_SYS_CLK_FREQ 66660000
116 #define CONFIG_DDR_CLK_FREQ 133330000
119 * Config the L3 Cache as L3 SRAM
121 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
122 #define CONFIG_SYS_L3_SIZE (512 << 10)
123 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
124 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
125 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
126 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
127 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
129 #define CONFIG_SYS_DCSRBAR 0xf0000000
130 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
133 #define CONFIG_ID_EEPROM
134 #define CONFIG_SYS_I2C_EEPROM_NXID
135 #define CONFIG_SYS_EEPROM_BUS_NUM 0
136 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
137 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
142 #define CONFIG_VERY_BIG_RAM
143 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
144 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
145 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
146 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
147 #define CONFIG_DDR_SPD
148 #define CONFIG_SYS_SPD_BUS_NUM 0
149 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
150 #define SPD_EEPROM_ADDRESS1 0x51
151 #define SPD_EEPROM_ADDRESS2 0x52
152 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
153 #define CTRL_INTLV_PREFERED cacheline
158 #define CONFIG_SYS_FLASH_BASE 0xe8000000
159 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
160 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
161 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
162 CSPR_PORT_SIZE_16 | \
165 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
167 /* NOR Flash Timing Params */
168 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
170 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
171 FTIM0_NOR_TEADC(0x5) | \
172 FTIM0_NOR_TEAHC(0x5))
173 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
174 FTIM1_NOR_TRAD_NOR(0x1A) |\
175 FTIM1_NOR_TSEQRAD_NOR(0x13))
176 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
177 FTIM2_NOR_TCH(0x4) | \
178 FTIM2_NOR_TWPH(0x0E) | \
180 #define CONFIG_SYS_NOR_FTIM3 0x0
182 #define CONFIG_SYS_FLASH_QUIET_TEST
183 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
185 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
186 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
187 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
188 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
189 #define CONFIG_SYS_FLASH_EMPTY_INFO
190 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS }
193 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
194 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
195 #define CONFIG_SYS_CSPR2_EXT (0xf)
196 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
200 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
201 #define CONFIG_SYS_CSOR2 0x0
203 /* CPLD Timing parameters for IFC CS2 */
204 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
205 FTIM0_GPCM_TEADC(0x0e) | \
206 FTIM0_GPCM_TEAHC(0x0e))
207 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
208 FTIM1_GPCM_TRAD(0x1f))
209 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
210 FTIM2_GPCM_TCH(0x8) | \
211 FTIM2_GPCM_TWP(0x1f))
212 #define CONFIG_SYS_CS2_FTIM3 0x0
214 /* NAND Flash on IFC */
215 #define CONFIG_NAND_FSL_IFC
216 #define CONFIG_SYS_NAND_BASE 0xff800000
217 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
219 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
220 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
221 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
222 | CSPR_MSEL_NAND /* MSEL = NAND */ \
224 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
226 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
227 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
228 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
229 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
230 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
231 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
232 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
234 #define CONFIG_SYS_NAND_ONFI_DETECTION
236 /* ONFI NAND Flash mode0 Timing Params */
237 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
238 FTIM0_NAND_TWP(0x18) | \
239 FTIM0_NAND_TWCHT(0x07) | \
240 FTIM0_NAND_TWH(0x0a))
241 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
242 FTIM1_NAND_TWBE(0x39) | \
243 FTIM1_NAND_TRR(0x0e) | \
244 FTIM1_NAND_TRP(0x18))
245 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
246 FTIM2_NAND_TREH(0x0a) | \
247 FTIM2_NAND_TWHRE(0x1e))
248 #define CONFIG_SYS_NAND_FTIM3 0x0
250 #define CONFIG_SYS_NAND_DDR_LAW 11
251 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
252 #define CONFIG_SYS_MAX_NAND_DEVICE 1
253 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
255 #if defined(CONFIG_MTD_RAW_NAND)
256 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
257 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
258 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
259 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
260 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
261 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
262 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
263 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
264 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
265 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
266 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
267 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
268 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
269 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
270 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
271 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
273 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
274 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
275 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
276 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
277 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
278 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
279 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
280 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
281 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
282 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
283 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
284 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
285 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
286 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
287 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
288 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
291 #if defined(CONFIG_RAMBOOT_PBL)
292 #define CONFIG_SYS_RAMBOOT
295 #ifdef CONFIG_SPL_BUILD
296 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
298 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
301 #define CONFIG_HWCONFIG
303 /* define to use L1 as initial stack */
304 #define CONFIG_L1_INIT_RAM
305 #define CONFIG_SYS_INIT_RAM_LOCK
306 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
307 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
308 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
309 /* The assembler doesn't like typecast */
310 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
311 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
312 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
313 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
314 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
315 GENERATED_GBL_DATA_SIZE)
316 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
317 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
318 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
323 #define CONFIG_SYS_NS16550_SERIAL
324 #define CONFIG_SYS_NS16550_REG_SIZE 1
325 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
326 #define CONFIG_SYS_BAUDRATE_TABLE \
327 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
328 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
329 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
330 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
331 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
336 #ifndef CONFIG_DM_I2C
337 #define CONFIG_SYS_I2C
338 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
339 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
340 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
341 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
342 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
343 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
344 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
345 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
346 #define CONFIG_SYS_FSL_I2C_SPEED 100000
347 #define CONFIG_SYS_FSL_I2C2_SPEED 100000
348 #define CONFIG_SYS_FSL_I2C3_SPEED 100000
349 #define CONFIG_SYS_FSL_I2C4_SPEED 100000
351 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
352 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
355 #define CONFIG_SYS_I2C_FSL
357 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
358 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
359 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
360 #define I2C_MUX_CH_DEFAULT 0x8
362 #define I2C_MUX_CH_VOL_MONITOR 0xa
364 #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv"
365 #ifndef CONFIG_SPL_BUILD
368 #define CONFIG_VOL_MONITOR_IR36021_SET
369 #define CONFIG_VOL_MONITOR_IR36021_READ
370 /* The lowest and highest voltage allowed for T208xRDB */
371 #define VDD_MV_MIN 819
372 #define VDD_MV_MAX 1212
377 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
378 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
379 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
380 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
381 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
382 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
384 * for slave u-boot IMAGE instored in master memory space,
385 * PHYS must be aligned based on the SIZE
387 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
388 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
389 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
390 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
392 * for slave UCODE and ENV instored in master memory space,
393 * PHYS must be aligned based on the SIZE
395 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
396 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
397 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
399 /* slave core release by master*/
400 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
401 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
404 * SRIO_PCIE_BOOT - SLAVE
406 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
407 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
408 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
409 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
413 * eSPI - Enhanced SPI
418 * Memory space is mapped 1-1, but I/O space must start from 0.
420 #define CONFIG_PCIE1 /* PCIE controller 1 */
421 #define CONFIG_PCIE2 /* PCIE controller 2 */
422 #define CONFIG_PCIE3 /* PCIE controller 3 */
423 #define CONFIG_PCIE4 /* PCIE controller 4 */
424 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
425 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
426 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
427 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
428 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
429 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
431 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
432 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
433 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
434 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
435 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
437 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
438 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
439 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
440 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
441 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
443 /* controller 4, Base address 203000 */
444 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
445 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
446 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
449 #if !defined(CONFIG_DM_PCI)
450 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
451 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
452 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
453 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
454 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
455 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
456 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
457 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
458 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
459 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
460 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
461 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
462 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
463 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
464 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
465 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
466 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
467 #define CONFIG_PCI_INDIRECT_BRIDGE
469 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
473 #ifndef CONFIG_NOBQFMAN
474 #define CONFIG_SYS_BMAN_NUM_PORTALS 18
475 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
476 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
477 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
478 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
479 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
480 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
481 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
482 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
483 CONFIG_SYS_BMAN_CENA_SIZE)
484 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
485 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
486 #define CONFIG_SYS_QMAN_NUM_PORTALS 18
487 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
488 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
489 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
490 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
491 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
492 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
493 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
494 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
495 CONFIG_SYS_QMAN_CENA_SIZE)
496 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
497 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
499 #define CONFIG_SYS_DPAA_FMAN
500 #define CONFIG_SYS_DPAA_PME
501 #define CONFIG_SYS_PMAN
502 #define CONFIG_SYS_DPAA_DCE
503 #define CONFIG_SYS_DPAA_RMAN /* RMan */
504 #define CONFIG_SYS_INTERLAKEN
506 /* Default address of microcode for the Linux Fman driver */
507 #if defined(CONFIG_SPIFLASH)
509 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
510 * env, so we got 0x110000.
512 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
513 #define CONFIG_CORTINA_FW_ADDR 0x120000
515 #elif defined(CONFIG_SDCARD)
517 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
518 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
519 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
521 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
522 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0)
524 #elif defined(CONFIG_MTD_RAW_NAND)
525 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
526 #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
527 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
529 * Slave has no ucode locally, it can fetch this from remote. When implementing
530 * in two corenet boards, slave's ucode could be stored in master's memory
531 * space, the address can be mapped from slave TLB->slave LAW->
532 * slave SRIO or PCIE outbound window->master inbound window->
533 * master LAW->the ucode address in master's memory space.
535 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
536 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000
538 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
539 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000
541 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
542 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
543 #endif /* CONFIG_NOBQFMAN */
545 #ifdef CONFIG_SYS_DPAA_FMAN
546 #define CONFIG_CORTINA_FW_LENGTH 0x40000
547 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
548 #define RGMII_PHY2_ADDR 0x02
549 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */
550 #define CORTINA_PHY_ADDR2 0x0d
551 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */
552 #define FM1_10GEC4_PHY_ADDR 0x01
555 #ifdef CONFIG_FMAN_ENET
556 #define CONFIG_ETHPRIME "FM1@DTSEC3"
562 #ifdef CONFIG_FSL_SATA_V2
563 #define CONFIG_SYS_SATA_MAX_DEVICE 2
565 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
566 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
568 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
569 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
576 #ifdef CONFIG_USB_EHCI_HCD
577 #define CONFIG_USB_EHCI_FSL
578 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
579 #define CONFIG_HAS_FSL_DR_USB
586 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
587 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
588 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
592 * Dynamic MTD Partition support with mtdparts
600 * Miscellaneous configurable options
602 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
605 * For booting Linux, the board info and command line data
606 * have to be in the first 64 MB of memory, since this is
607 * the maximum mapped by the Linux kernel during initialization.
609 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
610 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
612 #ifdef CONFIG_CMD_KGDB
613 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
614 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
618 * Environment Configuration
620 #define CONFIG_ROOTPATH "/opt/nfsroot"
621 #define CONFIG_BOOTFILE "uImage"
622 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
624 /* default location for tftp and bootm */
625 #define CONFIG_LOADADDR 1000000
626 #define __USB_PHY_TYPE utmi
628 #define CONFIG_EXTRA_ENV_SETTINGS \
629 "hwconfig=fsl_ddr:" \
630 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
632 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
634 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
635 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
636 "tftpflash=tftpboot $loadaddr $uboot && " \
637 "protect off $ubootaddr +$filesize && " \
638 "erase $ubootaddr +$filesize && " \
639 "cp.b $loadaddr $ubootaddr $filesize && " \
640 "protect on $ubootaddr +$filesize && " \
641 "cmp.b $loadaddr $ubootaddr $filesize\0" \
642 "consoledev=ttyS0\0" \
643 "ramdiskaddr=2000000\0" \
644 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \
645 "fdtaddr=1e00000\0" \
646 "fdtfile=t2080rdb/t2080rdb.dtb\0" \
650 * For emulation this causes u-boot to jump to the start of the
651 * proof point app code automatically
653 #define CONFIG_PROOF_POINTS \
654 "setenv bootargs root=/dev/$bdev rw " \
655 "console=$consoledev,$baudrate $othbootargs;" \
656 "cpu 1 release 0x29000000 - - -;" \
657 "cpu 2 release 0x29000000 - - -;" \
658 "cpu 3 release 0x29000000 - - -;" \
659 "cpu 4 release 0x29000000 - - -;" \
660 "cpu 5 release 0x29000000 - - -;" \
661 "cpu 6 release 0x29000000 - - -;" \
662 "cpu 7 release 0x29000000 - - -;" \
665 #define CONFIG_HVBOOT \
666 "setenv bootargs config-addr=0x60000000; " \
667 "bootm 0x01000000 - 0x00f00000"
670 "setenv bootargs root=/dev/$bdev rw " \
671 "console=$consoledev,$baudrate $othbootargs;" \
672 "cpu 1 release 0x01000000 - - -;" \
673 "cpu 2 release 0x01000000 - - -;" \
674 "cpu 3 release 0x01000000 - - -;" \
675 "cpu 4 release 0x01000000 - - -;" \
676 "cpu 5 release 0x01000000 - - -;" \
677 "cpu 6 release 0x01000000 - - -;" \
678 "cpu 7 release 0x01000000 - - -;" \
681 #define CONFIG_LINUX \
682 "setenv bootargs root=/dev/ram rw " \
683 "console=$consoledev,$baudrate $othbootargs;" \
684 "setenv ramdiskaddr 0x02000000;" \
685 "setenv fdtaddr 0x00c00000;" \
686 "setenv loadaddr 0x1000000;" \
687 "bootm $loadaddr $ramdiskaddr $fdtaddr"
689 #define CONFIG_HDBOOT \
690 "setenv bootargs root=/dev/$bdev rw " \
691 "console=$consoledev,$baudrate $othbootargs;" \
692 "tftp $loadaddr $bootfile;" \
693 "tftp $fdtaddr $fdtfile;" \
694 "bootm $loadaddr - $fdtaddr"
696 #define CONFIG_NFSBOOTCOMMAND \
697 "setenv bootargs root=/dev/nfs rw " \
698 "nfsroot=$serverip:$rootpath " \
699 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
700 "console=$consoledev,$baudrate $othbootargs;" \
701 "tftp $loadaddr $bootfile;" \
702 "tftp $fdtaddr $fdtfile;" \
703 "bootm $loadaddr - $fdtaddr"
705 #define CONFIG_RAMBOOTCOMMAND \
706 "setenv bootargs root=/dev/ram rw " \
707 "console=$consoledev,$baudrate $othbootargs;" \
708 "tftp $ramdiskaddr $ramdiskfile;" \
709 "tftp $loadaddr $bootfile;" \
710 "tftp $fdtaddr $fdtfile;" \
711 "bootm $loadaddr $ramdiskaddr $fdtaddr"
713 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
715 #include <asm/fsl_secure_boot.h>
717 #endif /* __T2080RDB_H */