1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
8 * T2080 RDB/PCIe board configuration file
14 #include <linux/stringify.h>
16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
17 #define CONFIG_FSL_SATA_V2
19 /* High Level Configuration Options */
20 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
21 #define CONFIG_ENABLE_36BIT_PHYS
23 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
24 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
26 #ifdef CONFIG_RAMBOOT_PBL
27 #define CONFIG_SPL_FLUSH_IMAGE
28 #define CONFIG_SPL_PAD_TO 0x40000
29 #define CONFIG_SPL_MAX_SIZE 0x28000
30 #define RESET_VECTOR_OFFSET 0x27FFC
31 #define BOOT_PAGE_OFFSET 0x27000
32 #ifdef CONFIG_SPL_BUILD
33 #define CONFIG_SPL_SKIP_RELOCATE
34 #define CONFIG_SPL_COMMON_INIT_DDR
35 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
38 #ifdef CONFIG_MTD_RAW_NAND
39 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
40 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
41 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
44 #ifdef CONFIG_SPIFLASH
45 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
46 #define CONFIG_SPL_SPI_FLASH_MINIMAL
47 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
48 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
49 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
50 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
51 #ifndef CONFIG_SPL_BUILD
52 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
57 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
58 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
59 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
60 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
61 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
62 #ifndef CONFIG_SPL_BUILD
63 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
67 #endif /* CONFIG_RAMBOOT_PBL */
69 #define CONFIG_SRIO_PCIE_BOOT_MASTER
70 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
71 /* Set 1M boot space */
72 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
73 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
74 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
75 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
78 #ifndef CONFIG_RESET_VECTOR_ADDRESS
79 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
83 * These can be toggled for performance analysis, otherwise use default.
85 #define CONFIG_SYS_CACHE_STASHING
86 #define CONFIG_BTB /* toggle branch predition */
88 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
92 * Config the L3 Cache as L3 SRAM
94 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
95 #define CONFIG_SYS_L3_SIZE (512 << 10)
96 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
97 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
98 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
99 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
100 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
102 #define CONFIG_SYS_DCSRBAR 0xf0000000
103 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
106 #define CONFIG_SYS_I2C_EEPROM_NXID
107 #define CONFIG_SYS_EEPROM_BUS_NUM 0
112 #define CONFIG_VERY_BIG_RAM
113 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
114 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
115 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
116 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
117 #define CONFIG_SYS_SPD_BUS_NUM 0
118 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
119 #define SPD_EEPROM_ADDRESS1 0x51
120 #define SPD_EEPROM_ADDRESS2 0x52
121 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
122 #define CTRL_INTLV_PREFERED cacheline
127 #define CONFIG_SYS_FLASH_BASE 0xe8000000
128 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
129 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
130 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
131 CSPR_PORT_SIZE_16 | \
134 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
136 /* NOR Flash Timing Params */
137 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
139 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
140 FTIM0_NOR_TEADC(0x5) | \
141 FTIM0_NOR_TEAHC(0x5))
142 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
143 FTIM1_NOR_TRAD_NOR(0x1A) |\
144 FTIM1_NOR_TSEQRAD_NOR(0x13))
145 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
146 FTIM2_NOR_TCH(0x4) | \
147 FTIM2_NOR_TWPH(0x0E) | \
149 #define CONFIG_SYS_NOR_FTIM3 0x0
151 #define CONFIG_SYS_FLASH_QUIET_TEST
152 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
154 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
155 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
156 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
157 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
158 #define CONFIG_SYS_FLASH_EMPTY_INFO
159 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS }
162 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
163 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
164 #define CONFIG_SYS_CSPR2_EXT (0xf)
165 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
169 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
170 #define CONFIG_SYS_CSOR2 0x0
172 /* CPLD Timing parameters for IFC CS2 */
173 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
174 FTIM0_GPCM_TEADC(0x0e) | \
175 FTIM0_GPCM_TEAHC(0x0e))
176 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
177 FTIM1_GPCM_TRAD(0x1f))
178 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
179 FTIM2_GPCM_TCH(0x8) | \
180 FTIM2_GPCM_TWP(0x1f))
181 #define CONFIG_SYS_CS2_FTIM3 0x0
183 /* NAND Flash on IFC */
184 #define CONFIG_SYS_NAND_BASE 0xff800000
185 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
187 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
188 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
189 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
190 | CSPR_MSEL_NAND /* MSEL = NAND */ \
192 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
194 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
195 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
196 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
197 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
198 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
199 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
200 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
202 /* ONFI NAND Flash mode0 Timing Params */
203 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
204 FTIM0_NAND_TWP(0x18) | \
205 FTIM0_NAND_TWCHT(0x07) | \
206 FTIM0_NAND_TWH(0x0a))
207 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
208 FTIM1_NAND_TWBE(0x39) | \
209 FTIM1_NAND_TRR(0x0e) | \
210 FTIM1_NAND_TRP(0x18))
211 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
212 FTIM2_NAND_TREH(0x0a) | \
213 FTIM2_NAND_TWHRE(0x1e))
214 #define CONFIG_SYS_NAND_FTIM3 0x0
216 #define CONFIG_SYS_NAND_DDR_LAW 11
217 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
218 #define CONFIG_SYS_MAX_NAND_DEVICE 1
220 #if defined(CONFIG_MTD_RAW_NAND)
221 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
222 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
223 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
224 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
225 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
226 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
227 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
228 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
229 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
230 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
231 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
232 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
233 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
234 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
235 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
236 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
238 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
239 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
240 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
241 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
242 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
243 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
244 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
245 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
246 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
247 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
248 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
249 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
250 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
251 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
252 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
253 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
256 #if defined(CONFIG_RAMBOOT_PBL)
257 #define CONFIG_SYS_RAMBOOT
260 #ifdef CONFIG_SPL_BUILD
261 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
263 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
266 #define CONFIG_HWCONFIG
268 /* define to use L1 as initial stack */
269 #define CONFIG_L1_INIT_RAM
270 #define CONFIG_SYS_INIT_RAM_LOCK
271 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
272 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
273 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
274 /* The assembler doesn't like typecast */
275 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
276 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
277 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
278 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
279 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
280 GENERATED_GBL_DATA_SIZE)
281 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
282 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
287 #define CONFIG_SYS_NS16550_SERIAL
288 #define CONFIG_SYS_NS16550_REG_SIZE 1
289 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
290 #define CONFIG_SYS_BAUDRATE_TABLE \
291 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
292 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
293 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
294 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
295 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
301 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
302 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
303 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
304 #define I2C_MUX_CH_DEFAULT 0x8
306 #define I2C_MUX_CH_VOL_MONITOR 0xa
308 /* The lowest and highest voltage allowed for T208xRDB */
309 #define VDD_MV_MIN 819
310 #define VDD_MV_MAX 1212
315 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
316 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
317 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
318 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
319 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
320 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
322 * for slave u-boot IMAGE instored in master memory space,
323 * PHYS must be aligned based on the SIZE
325 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
326 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
327 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
328 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
330 * for slave UCODE and ENV instored in master memory space,
331 * PHYS must be aligned based on the SIZE
333 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
334 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
335 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
337 /* slave core release by master*/
338 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
339 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
342 * SRIO_PCIE_BOOT - SLAVE
344 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
345 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
346 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
347 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
351 * eSPI - Enhanced SPI
356 * Memory space is mapped 1-1, but I/O space must start from 0.
358 #define CONFIG_PCIE1 /* PCIE controller 1 */
359 #define CONFIG_PCIE2 /* PCIE controller 2 */
360 #define CONFIG_PCIE3 /* PCIE controller 3 */
361 #define CONFIG_PCIE4 /* PCIE controller 4 */
362 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
363 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
364 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
365 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
366 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
368 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
369 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
370 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
371 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
372 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
374 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
375 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
376 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
377 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
378 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
380 /* controller 4, Base address 203000 */
381 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
382 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
383 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
386 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
390 #ifndef CONFIG_NOBQFMAN
391 #define CONFIG_SYS_BMAN_NUM_PORTALS 18
392 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
393 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
394 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
395 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
396 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
397 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
398 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
399 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
400 CONFIG_SYS_BMAN_CENA_SIZE)
401 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
402 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
403 #define CONFIG_SYS_QMAN_NUM_PORTALS 18
404 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
405 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
406 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
407 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
408 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
409 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
410 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
411 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
412 CONFIG_SYS_QMAN_CENA_SIZE)
413 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
414 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
416 #define CONFIG_SYS_DPAA_FMAN
417 #define CONFIG_SYS_DPAA_PME
418 #define CONFIG_SYS_PMAN
419 #define CONFIG_SYS_DPAA_DCE
420 #define CONFIG_SYS_DPAA_RMAN /* RMan */
421 #define CONFIG_SYS_INTERLAKEN
423 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
424 #endif /* CONFIG_NOBQFMAN */
426 #ifdef CONFIG_SYS_DPAA_FMAN
427 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
428 #define RGMII_PHY2_ADDR 0x02
429 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */
430 #define CORTINA_PHY_ADDR2 0x0d
431 /* Aquantia AQ1202 10G Base-T used by board revisions up to C */
432 #define FM1_10GEC3_PHY_ADDR 0x00
433 #define FM1_10GEC4_PHY_ADDR 0x01
434 /* Aquantia AQR113C 10G Base-T used by board revisions D and up */
435 #define AQR113C_PHY_ADDR1 0x00
436 #define AQR113C_PHY_ADDR2 0x08
439 #ifdef CONFIG_FMAN_ENET
440 #define CONFIG_ETHPRIME "FM1@DTSEC3"
446 #ifdef CONFIG_FSL_SATA_V2
447 #define CONFIG_SYS_SATA_MAX_DEVICE 2
449 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
450 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
452 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
453 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
460 #ifdef CONFIG_USB_EHCI_HCD
461 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
462 #define CONFIG_HAS_FSL_DR_USB
469 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
470 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
474 * Dynamic MTD Partition support with mtdparts
482 * Miscellaneous configurable options
486 * For booting Linux, the board info and command line data
487 * have to be in the first 64 MB of memory, since this is
488 * the maximum mapped by the Linux kernel during initialization.
490 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
491 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
494 * Environment Configuration
496 #define CONFIG_ROOTPATH "/opt/nfsroot"
497 #define CONFIG_BOOTFILE "uImage"
498 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
500 #define __USB_PHY_TYPE utmi
502 #define CONFIG_EXTRA_ENV_SETTINGS \
503 "hwconfig=fsl_ddr:" \
504 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
506 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
508 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
509 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
510 "tftpflash=tftpboot $loadaddr $uboot && " \
511 "protect off $ubootaddr +$filesize && " \
512 "erase $ubootaddr +$filesize && " \
513 "cp.b $loadaddr $ubootaddr $filesize && " \
514 "protect on $ubootaddr +$filesize && " \
515 "cmp.b $loadaddr $ubootaddr $filesize\0" \
516 "consoledev=ttyS0\0" \
517 "ramdiskaddr=2000000\0" \
518 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \
519 "fdtaddr=1e00000\0" \
520 "fdtfile=t2080rdb/t2080rdb.dtb\0" \
524 * For emulation this causes u-boot to jump to the start of the
525 * proof point app code automatically
527 #define PROOF_POINTS \
528 "setenv bootargs root=/dev/$bdev rw " \
529 "console=$consoledev,$baudrate $othbootargs;" \
530 "cpu 1 release 0x29000000 - - -;" \
531 "cpu 2 release 0x29000000 - - -;" \
532 "cpu 3 release 0x29000000 - - -;" \
533 "cpu 4 release 0x29000000 - - -;" \
534 "cpu 5 release 0x29000000 - - -;" \
535 "cpu 6 release 0x29000000 - - -;" \
536 "cpu 7 release 0x29000000 - - -;" \
540 "setenv bootargs config-addr=0x60000000; " \
541 "bootm 0x01000000 - 0x00f00000"
544 "setenv bootargs root=/dev/$bdev rw " \
545 "console=$consoledev,$baudrate $othbootargs;" \
546 "cpu 1 release 0x01000000 - - -;" \
547 "cpu 2 release 0x01000000 - - -;" \
548 "cpu 3 release 0x01000000 - - -;" \
549 "cpu 4 release 0x01000000 - - -;" \
550 "cpu 5 release 0x01000000 - - -;" \
551 "cpu 6 release 0x01000000 - - -;" \
552 "cpu 7 release 0x01000000 - - -;" \
555 #include <asm/fsl_secure_boot.h>
557 #endif /* __T2080RDB_H */