1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2011-2013 Freescale Semiconductor, Inc.
8 * T2080/T2081 QDS board configuration file
14 #include <linux/stringify.h>
16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
17 #if defined(CONFIG_ARCH_T2080)
18 #define CONFIG_FSL_SATA_V2
19 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
20 #define CONFIG_SRIO1 /* SRIO port 1 */
21 #define CONFIG_SRIO2 /* SRIO port 2 */
22 #elif defined(CONFIG_ARCH_T2081)
25 /* High Level Configuration Options */
26 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
27 #define CONFIG_ENABLE_36BIT_PHYS
29 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
30 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
32 #ifdef CONFIG_RAMBOOT_PBL
33 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
35 #define CONFIG_SPL_FLUSH_IMAGE
36 #define CONFIG_SPL_PAD_TO 0x40000
37 #define CONFIG_SPL_MAX_SIZE 0x28000
38 #define RESET_VECTOR_OFFSET 0x27FFC
39 #define BOOT_PAGE_OFFSET 0x27000
40 #ifdef CONFIG_SPL_BUILD
41 #define CONFIG_SPL_SKIP_RELOCATE
42 #define CONFIG_SPL_COMMON_INIT_DDR
43 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
46 #ifdef CONFIG_MTD_RAW_NAND
47 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
48 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
49 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
50 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
51 #if defined(CONFIG_ARCH_T2080)
52 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg
53 #elif defined(CONFIG_ARCH_T2081)
54 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg
58 #ifdef CONFIG_SPIFLASH
59 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
60 #define CONFIG_SPL_SPI_FLASH_MINIMAL
61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
62 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
65 #ifndef CONFIG_SPL_BUILD
66 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
68 #if defined(CONFIG_ARCH_T2080)
69 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg
70 #elif defined(CONFIG_ARCH_T2081)
71 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg
76 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
77 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
78 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
79 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
80 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
81 #ifndef CONFIG_SPL_BUILD
82 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
84 #if defined(CONFIG_ARCH_T2080)
85 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg
86 #elif defined(CONFIG_ARCH_T2081)
87 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg
91 #endif /* CONFIG_RAMBOOT_PBL */
93 #define CONFIG_SRIO_PCIE_BOOT_MASTER
94 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
95 /* Set 1M boot space */
96 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
97 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
98 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
99 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
102 #ifndef CONFIG_RESET_VECTOR_ADDRESS
103 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
107 * These can be toggled for performance analysis, otherwise use default.
109 #define CONFIG_SYS_CACHE_STASHING
110 #define CONFIG_BTB /* toggle branch predition */
111 #define CONFIG_DDR_ECC
112 #ifdef CONFIG_DDR_ECC
113 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
114 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
117 #if defined(CONFIG_SPIFLASH)
118 #elif defined(CONFIG_SDCARD)
119 #define CONFIG_SYS_MMC_ENV_DEV 0
123 unsigned long get_board_sys_clk(void);
124 unsigned long get_board_ddr_clk(void);
127 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
128 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
131 * Config the L3 Cache as L3 SRAM
133 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
134 #define CONFIG_SYS_L3_SIZE (512 << 10)
135 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
136 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
137 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
138 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
139 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
141 #define CONFIG_SYS_DCSRBAR 0xf0000000
142 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
145 #define CONFIG_ID_EEPROM
146 #define CONFIG_SYS_I2C_EEPROM_NXID
147 #define CONFIG_SYS_EEPROM_BUS_NUM 0
148 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
149 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
154 #define CONFIG_VERY_BIG_RAM
155 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
156 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
157 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
158 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
159 #define CONFIG_DDR_SPD
160 #define CONFIG_SYS_SPD_BUS_NUM 0
161 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
162 #define SPD_EEPROM_ADDRESS1 0x51
163 #define SPD_EEPROM_ADDRESS2 0x52
164 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
165 #define CTRL_INTLV_PREFERED cacheline
170 #define CONFIG_SYS_FLASH_BASE 0xe0000000
171 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
172 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
173 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
175 CSPR_PORT_SIZE_16 | \
178 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
179 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
180 CSPR_PORT_SIZE_16 | \
183 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
184 /* NOR Flash Timing Params */
185 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
187 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
188 FTIM0_NOR_TEADC(0x5) | \
189 FTIM0_NOR_TEAHC(0x5))
190 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
191 FTIM1_NOR_TRAD_NOR(0x1A) |\
192 FTIM1_NOR_TSEQRAD_NOR(0x13))
193 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
194 FTIM2_NOR_TCH(0x4) | \
195 FTIM2_NOR_TWPH(0x0E) | \
197 #define CONFIG_SYS_NOR_FTIM3 0x0
199 #define CONFIG_SYS_FLASH_QUIET_TEST
200 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
202 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
203 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
204 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
205 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
207 #define CONFIG_SYS_FLASH_EMPTY_INFO
208 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
209 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
211 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
212 #define QIXIS_BASE 0xffdf0000
213 #define QIXIS_LBMAP_SWITCH 6
214 #define QIXIS_LBMAP_MASK 0x0f
215 #define QIXIS_LBMAP_SHIFT 0
216 #define QIXIS_LBMAP_DFLTBANK 0x00
217 #define QIXIS_LBMAP_ALTBANK 0x04
218 #define QIXIS_LBMAP_NAND 0x09
219 #define QIXIS_LBMAP_SD 0x00
220 #define QIXIS_RCW_SRC_NAND 0x104
221 #define QIXIS_RCW_SRC_SD 0x040
222 #define QIXIS_RST_CTL_RESET 0x83
223 #define QIXIS_RST_FORCE_MEM 0x1
224 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
225 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
226 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
227 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
229 #define CONFIG_SYS_CSPR3_EXT (0xf)
230 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
234 #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
235 #define CONFIG_SYS_CSOR3 0x0
236 /* QIXIS Timing parameters for IFC CS3 */
237 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
238 FTIM0_GPCM_TEADC(0x0e) | \
239 FTIM0_GPCM_TEAHC(0x0e))
240 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
241 FTIM1_GPCM_TRAD(0x3f))
242 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
243 FTIM2_GPCM_TCH(0x8) | \
244 FTIM2_GPCM_TWP(0x1f))
245 #define CONFIG_SYS_CS3_FTIM3 0x0
247 /* NAND Flash on IFC */
248 #define CONFIG_NAND_FSL_IFC
249 #define CONFIG_SYS_NAND_BASE 0xff800000
250 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
252 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
253 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
254 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
255 | CSPR_MSEL_NAND /* MSEL = NAND */ \
257 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
259 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
260 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
261 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
262 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
263 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
264 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
265 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
267 #define CONFIG_SYS_NAND_ONFI_DETECTION
269 /* ONFI NAND Flash mode0 Timing Params */
270 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
271 FTIM0_NAND_TWP(0x18) | \
272 FTIM0_NAND_TWCHT(0x07) | \
273 FTIM0_NAND_TWH(0x0a))
274 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
275 FTIM1_NAND_TWBE(0x39) | \
276 FTIM1_NAND_TRR(0x0e) | \
277 FTIM1_NAND_TRP(0x18))
278 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
279 FTIM2_NAND_TREH(0x0a) | \
280 FTIM2_NAND_TWHRE(0x1e))
281 #define CONFIG_SYS_NAND_FTIM3 0x0
283 #define CONFIG_SYS_NAND_DDR_LAW 11
284 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
285 #define CONFIG_SYS_MAX_NAND_DEVICE 1
286 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
288 #if defined(CONFIG_MTD_RAW_NAND)
289 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
290 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
291 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
292 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
293 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
294 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
295 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
296 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
297 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
298 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
299 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
300 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
301 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
302 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
303 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
304 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
305 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
306 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
307 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
308 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
309 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
310 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
311 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
312 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
314 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
315 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
316 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
317 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
318 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
319 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
320 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
321 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
322 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
323 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
324 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
325 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
326 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
327 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
328 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
329 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
330 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
331 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
332 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
333 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
334 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
335 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
336 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
337 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
340 #if defined(CONFIG_RAMBOOT_PBL)
341 #define CONFIG_SYS_RAMBOOT
344 #ifdef CONFIG_SPL_BUILD
345 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
347 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
350 #define CONFIG_HWCONFIG
352 /* define to use L1 as initial stack */
353 #define CONFIG_L1_INIT_RAM
354 #define CONFIG_SYS_INIT_RAM_LOCK
355 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
356 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
357 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
358 /* The assembler doesn't like typecast */
359 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
360 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
361 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
362 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
363 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
364 GENERATED_GBL_DATA_SIZE)
365 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
366 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
367 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
372 #define CONFIG_SYS_NS16550_SERIAL
373 #define CONFIG_SYS_NS16550_REG_SIZE 1
374 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
375 #define CONFIG_SYS_BAUDRATE_TABLE \
376 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
377 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
378 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
379 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
380 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
385 #ifndef CONFIG_DM_I2C
386 #define CONFIG_SYS_I2C
387 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
388 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
389 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
390 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
391 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
392 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
393 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
394 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
395 #define CONFIG_SYS_FSL_I2C_SPEED 100000
396 #define CONFIG_SYS_FSL_I2C2_SPEED 100000
397 #define CONFIG_SYS_FSL_I2C3_SPEED 100000
398 #define CONFIG_SYS_FSL_I2C4_SPEED 100000
401 #define CONFIG_SYS_I2C_FSL
403 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
404 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
405 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
406 #define I2C_MUX_CH_DEFAULT 0x8
408 #define I2C_MUX_CH_VOL_MONITOR 0xa
410 /* Voltage monitor on channel 2*/
411 #define I2C_VOL_MONITOR_ADDR 0x40
412 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
413 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
414 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
416 #define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv"
417 #ifndef CONFIG_SPL_BUILD
420 #define CONFIG_VOL_MONITOR_IR36021_SET
421 #define CONFIG_VOL_MONITOR_IR36021_READ
422 /* The lowest and highest voltage allowed for T208xQDS */
423 #define VDD_MV_MIN 819
424 #define VDD_MV_MAX 1212
429 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
430 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
431 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
432 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
433 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
434 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
436 * for slave u-boot IMAGE instored in master memory space,
437 * PHYS must be aligned based on the SIZE
439 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
440 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
441 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
442 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
444 * for slave UCODE and ENV instored in master memory space,
445 * PHYS must be aligned based on the SIZE
447 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
448 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
449 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
451 /* slave core release by master*/
452 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
453 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
456 * SRIO_PCIE_BOOT - SLAVE
458 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
459 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
460 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
461 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
465 * eSPI - Enhanced SPI
470 * Memory space is mapped 1-1, but I/O space must start from 0.
472 #define CONFIG_PCIE1 /* PCIE controller 1 */
473 #define CONFIG_PCIE2 /* PCIE controller 2 */
474 #define CONFIG_PCIE3 /* PCIE controller 3 */
475 #define CONFIG_PCIE4 /* PCIE controller 4 */
476 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
477 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
478 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
479 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
480 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
481 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
483 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
484 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
485 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
486 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
487 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
489 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
490 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
491 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
492 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
493 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
495 /* controller 4, Base address 203000 */
496 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
497 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
498 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
501 #if !defined(CONFIG_DM_PCI)
502 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
503 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
504 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
505 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
506 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
507 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
508 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
509 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
510 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
511 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
512 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
513 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
514 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
515 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
516 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
517 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
518 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
519 #define CONFIG_PCI_INDIRECT_BRIDGE
521 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
525 #ifndef CONFIG_NOBQFMAN
526 #define CONFIG_SYS_BMAN_NUM_PORTALS 18
527 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
528 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
529 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
530 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
531 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
532 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
533 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
534 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
535 CONFIG_SYS_BMAN_CENA_SIZE)
536 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
537 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
538 #define CONFIG_SYS_QMAN_NUM_PORTALS 18
539 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
540 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
541 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
542 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
543 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
544 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
545 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
546 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
547 CONFIG_SYS_QMAN_CENA_SIZE)
548 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
549 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
551 #define CONFIG_SYS_DPAA_FMAN
552 #define CONFIG_SYS_DPAA_PME
553 #define CONFIG_SYS_PMAN
554 #define CONFIG_SYS_DPAA_DCE
555 #define CONFIG_SYS_DPAA_RMAN /* RMan */
556 #define CONFIG_SYS_INTERLAKEN
558 /* Default address of microcode for the Linux Fman driver */
559 #if defined(CONFIG_SPIFLASH)
561 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
562 * env, so we got 0x110000.
564 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
565 #elif defined(CONFIG_SDCARD)
567 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
568 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
569 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
571 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
572 #elif defined(CONFIG_MTD_RAW_NAND)
573 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
574 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
576 * Slave has no ucode locally, it can fetch this from remote. When implementing
577 * in two corenet boards, slave's ucode could be stored in master's memory
578 * space, the address can be mapped from slave TLB->slave LAW->
579 * slave SRIO or PCIE outbound window->master inbound window->
580 * master LAW->the ucode address in master's memory space.
582 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
584 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
586 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
587 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
588 #endif /* CONFIG_NOBQFMAN */
590 #ifdef CONFIG_SYS_DPAA_FMAN
591 #define RGMII_PHY1_ADDR 0x1
592 #define RGMII_PHY2_ADDR 0x2
593 #define FM1_10GEC1_PHY_ADDR 0x3
594 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
595 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
596 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
597 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
600 #ifdef CONFIG_FMAN_ENET
601 #define CONFIG_ETHPRIME "FM1@DTSEC3"
607 #ifdef CONFIG_FSL_SATA_V2
608 #define CONFIG_SYS_SATA_MAX_DEVICE 2
610 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
611 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
613 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
614 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
621 #ifdef CONFIG_USB_EHCI_HCD
622 #define CONFIG_USB_EHCI_FSL
623 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
624 #define CONFIG_HAS_FSL_DR_USB
631 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
632 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
633 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
637 * Dynamic MTD Partition support with mtdparts
643 #define CONFIG_LOADS_ECHO /* echo on for serial download */
644 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
647 * Miscellaneous configurable options
649 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
652 * For booting Linux, the board info and command line data
653 * have to be in the first 64 MB of memory, since this is
654 * the maximum mapped by the Linux kernel during initialization.
656 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
657 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
659 #ifdef CONFIG_CMD_KGDB
660 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
661 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
665 * Environment Configuration
667 #define CONFIG_ROOTPATH "/opt/nfsroot"
668 #define CONFIG_BOOTFILE "uImage"
669 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
671 /* default location for tftp and bootm */
672 #define CONFIG_LOADADDR 1000000
673 #define __USB_PHY_TYPE utmi
675 #define CONFIG_EXTRA_ENV_SETTINGS \
676 "hwconfig=fsl_ddr:" \
677 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
679 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
681 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
682 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
683 "tftpflash=tftpboot $loadaddr $uboot && " \
684 "protect off $ubootaddr +$filesize && " \
685 "erase $ubootaddr +$filesize && " \
686 "cp.b $loadaddr $ubootaddr $filesize && " \
687 "protect on $ubootaddr +$filesize && " \
688 "cmp.b $loadaddr $ubootaddr $filesize\0" \
689 "consoledev=ttyS0\0" \
690 "ramdiskaddr=2000000\0" \
691 "ramdiskfile=t2080qds/ramdisk.uboot\0" \
692 "fdtaddr=1e00000\0" \
693 "fdtfile=t2080qds/t2080qds.dtb\0" \
697 * For emulation this causes u-boot to jump to the start of the
698 * proof point app code automatically
700 #define CONFIG_PROOF_POINTS \
701 "setenv bootargs root=/dev/$bdev rw " \
702 "console=$consoledev,$baudrate $othbootargs;" \
703 "cpu 1 release 0x29000000 - - -;" \
704 "cpu 2 release 0x29000000 - - -;" \
705 "cpu 3 release 0x29000000 - - -;" \
706 "cpu 4 release 0x29000000 - - -;" \
707 "cpu 5 release 0x29000000 - - -;" \
708 "cpu 6 release 0x29000000 - - -;" \
709 "cpu 7 release 0x29000000 - - -;" \
712 #define CONFIG_HVBOOT \
713 "setenv bootargs config-addr=0x60000000; " \
714 "bootm 0x01000000 - 0x00f00000"
717 "setenv bootargs root=/dev/$bdev rw " \
718 "console=$consoledev,$baudrate $othbootargs;" \
719 "cpu 1 release 0x01000000 - - -;" \
720 "cpu 2 release 0x01000000 - - -;" \
721 "cpu 3 release 0x01000000 - - -;" \
722 "cpu 4 release 0x01000000 - - -;" \
723 "cpu 5 release 0x01000000 - - -;" \
724 "cpu 6 release 0x01000000 - - -;" \
725 "cpu 7 release 0x01000000 - - -;" \
728 #define CONFIG_LINUX \
729 "setenv bootargs root=/dev/ram rw " \
730 "console=$consoledev,$baudrate $othbootargs;" \
731 "setenv ramdiskaddr 0x02000000;" \
732 "setenv fdtaddr 0x00c00000;" \
733 "setenv loadaddr 0x1000000;" \
734 "bootm $loadaddr $ramdiskaddr $fdtaddr"
736 #define CONFIG_HDBOOT \
737 "setenv bootargs root=/dev/$bdev rw " \
738 "console=$consoledev,$baudrate $othbootargs;" \
739 "tftp $loadaddr $bootfile;" \
740 "tftp $fdtaddr $fdtfile;" \
741 "bootm $loadaddr - $fdtaddr"
743 #define CONFIG_NFSBOOTCOMMAND \
744 "setenv bootargs root=/dev/nfs rw " \
745 "nfsroot=$serverip:$rootpath " \
746 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
747 "console=$consoledev,$baudrate $othbootargs;" \
748 "tftp $loadaddr $bootfile;" \
749 "tftp $fdtaddr $fdtfile;" \
750 "bootm $loadaddr - $fdtaddr"
752 #define CONFIG_RAMBOOTCOMMAND \
753 "setenv bootargs root=/dev/ram rw " \
754 "console=$consoledev,$baudrate $othbootargs;" \
755 "tftp $ramdiskaddr $ramdiskfile;" \
756 "tftp $loadaddr $bootfile;" \
757 "tftp $fdtaddr $fdtfile;" \
758 "bootm $loadaddr $ramdiskaddr $fdtaddr"
760 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
762 #include <asm/fsl_secure_boot.h>
764 #endif /* __T208xQDS_H */