2 * Copyright 2011-2013 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * T2080/T2081 QDS board configuration file
14 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
15 #define CONFIG_USB_EHCI
16 #if defined(CONFIG_ARCH_T2080)
17 #define CONFIG_FSL_SATA_V2
18 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
19 #define CONFIG_SRIO1 /* SRIO port 1 */
20 #define CONFIG_SRIO2 /* SRIO port 2 */
21 #elif defined(CONFIG_ARCH_T2081)
22 #define CONFIG_T2081QDS
25 /* High Level Configuration Options */
26 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
27 #define CONFIG_MP /* support multiple processors */
28 #define CONFIG_ENABLE_36BIT_PHYS
30 #ifdef CONFIG_PHYS_64BIT
31 #define CONFIG_ADDR_MAP 1
32 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
35 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
36 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
37 #define CONFIG_FSL_IFC /* Enable IFC Support */
38 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
39 #define CONFIG_ENV_OVERWRITE
41 #ifdef CONFIG_RAMBOOT_PBL
42 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
44 #define CONFIG_SPL_FLUSH_IMAGE
45 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
46 #define CONFIG_SYS_TEXT_BASE 0x00201000
47 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
48 #define CONFIG_SPL_PAD_TO 0x40000
49 #define CONFIG_SPL_MAX_SIZE 0x28000
50 #define RESET_VECTOR_OFFSET 0x27FFC
51 #define BOOT_PAGE_OFFSET 0x27000
52 #ifdef CONFIG_SPL_BUILD
53 #define CONFIG_SPL_SKIP_RELOCATE
54 #define CONFIG_SPL_COMMON_INIT_DDR
55 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
56 #define CONFIG_SYS_NO_FLASH
60 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
61 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
62 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
63 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
64 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
65 #if defined(CONFIG_ARCH_T2080)
66 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg
67 #elif defined(CONFIG_ARCH_T2081)
68 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg
70 #define CONFIG_SPL_NAND_BOOT
73 #ifdef CONFIG_SPIFLASH
74 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
75 #define CONFIG_SPL_SPI_FLASH_MINIMAL
76 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
77 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
78 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
79 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
80 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
81 #ifndef CONFIG_SPL_BUILD
82 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
84 #if defined(CONFIG_ARCH_T2080)
85 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg
86 #elif defined(CONFIG_ARCH_T2081)
87 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg
89 #define CONFIG_SPL_SPI_BOOT
93 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
94 #define CONFIG_SPL_MMC_MINIMAL
95 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
96 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
97 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
98 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
99 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
100 #ifndef CONFIG_SPL_BUILD
101 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
103 #if defined(CONFIG_ARCH_T2080)
104 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg
105 #elif defined(CONFIG_ARCH_T2081)
106 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg
108 #define CONFIG_SPL_MMC_BOOT
111 #endif /* CONFIG_RAMBOOT_PBL */
113 #define CONFIG_SRIO_PCIE_BOOT_MASTER
114 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
115 /* Set 1M boot space */
116 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
117 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
118 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
119 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
120 #define CONFIG_SYS_NO_FLASH
123 #ifndef CONFIG_SYS_TEXT_BASE
124 #define CONFIG_SYS_TEXT_BASE 0xeff40000
127 #ifndef CONFIG_RESET_VECTOR_ADDRESS
128 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
132 * These can be toggled for performance analysis, otherwise use default.
134 #define CONFIG_SYS_CACHE_STASHING
135 #define CONFIG_BTB /* toggle branch predition */
136 #define CONFIG_DDR_ECC
137 #ifdef CONFIG_DDR_ECC
138 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
139 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
142 #ifndef CONFIG_SYS_NO_FLASH
143 #define CONFIG_FLASH_CFI_DRIVER
144 #define CONFIG_SYS_FLASH_CFI
145 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
148 #if defined(CONFIG_SPIFLASH)
149 #define CONFIG_SYS_EXTRA_ENV_RELOC
150 #define CONFIG_ENV_IS_IN_SPI_FLASH
151 #define CONFIG_ENV_SPI_BUS 0
152 #define CONFIG_ENV_SPI_CS 0
153 #define CONFIG_ENV_SPI_MAX_HZ 10000000
154 #define CONFIG_ENV_SPI_MODE 0
155 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
156 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
157 #define CONFIG_ENV_SECT_SIZE 0x10000
158 #elif defined(CONFIG_SDCARD)
159 #define CONFIG_SYS_EXTRA_ENV_RELOC
160 #define CONFIG_ENV_IS_IN_MMC
161 #define CONFIG_SYS_MMC_ENV_DEV 0
162 #define CONFIG_ENV_SIZE 0x2000
163 #define CONFIG_ENV_OFFSET (512 * 0x800)
164 #elif defined(CONFIG_NAND)
165 #define CONFIG_SYS_EXTRA_ENV_RELOC
166 #define CONFIG_ENV_IS_IN_NAND
167 #define CONFIG_ENV_SIZE 0x2000
168 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
169 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
170 #define CONFIG_ENV_IS_IN_REMOTE
171 #define CONFIG_ENV_ADDR 0xffe20000
172 #define CONFIG_ENV_SIZE 0x2000
173 #elif defined(CONFIG_ENV_IS_NOWHERE)
174 #define CONFIG_ENV_SIZE 0x2000
176 #define CONFIG_ENV_IS_IN_FLASH
177 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
178 #define CONFIG_ENV_SIZE 0x2000
179 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
183 unsigned long get_board_sys_clk(void);
184 unsigned long get_board_ddr_clk(void);
187 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
188 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
191 * Config the L3 Cache as L3 SRAM
193 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
194 #define CONFIG_SYS_L3_SIZE (512 << 10)
195 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
196 #ifdef CONFIG_RAMBOOT_PBL
197 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
199 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
200 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
201 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
202 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
204 #define CONFIG_SYS_DCSRBAR 0xf0000000
205 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
208 #define CONFIG_ID_EEPROM
209 #define CONFIG_SYS_I2C_EEPROM_NXID
210 #define CONFIG_SYS_EEPROM_BUS_NUM 0
211 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
212 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
217 #define CONFIG_VERY_BIG_RAM
218 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
219 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
220 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
221 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
222 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
223 #define CONFIG_DDR_SPD
224 #define CONFIG_SYS_FSL_DDR3
225 #define CONFIG_FSL_DDR_INTERACTIVE
226 #define CONFIG_SYS_SPD_BUS_NUM 0
227 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
228 #define SPD_EEPROM_ADDRESS1 0x51
229 #define SPD_EEPROM_ADDRESS2 0x52
230 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
231 #define CTRL_INTLV_PREFERED cacheline
236 #define CONFIG_SYS_FLASH_BASE 0xe0000000
237 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
238 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
239 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
241 CSPR_PORT_SIZE_16 | \
244 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
245 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
246 CSPR_PORT_SIZE_16 | \
249 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
250 /* NOR Flash Timing Params */
251 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
253 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
254 FTIM0_NOR_TEADC(0x5) | \
255 FTIM0_NOR_TEAHC(0x5))
256 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
257 FTIM1_NOR_TRAD_NOR(0x1A) |\
258 FTIM1_NOR_TSEQRAD_NOR(0x13))
259 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
260 FTIM2_NOR_TCH(0x4) | \
261 FTIM2_NOR_TWPH(0x0E) | \
263 #define CONFIG_SYS_NOR_FTIM3 0x0
265 #define CONFIG_SYS_FLASH_QUIET_TEST
266 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
268 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
269 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
270 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
271 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
273 #define CONFIG_SYS_FLASH_EMPTY_INFO
274 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
275 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
277 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
278 #define QIXIS_BASE 0xffdf0000
279 #define QIXIS_LBMAP_SWITCH 6
280 #define QIXIS_LBMAP_MASK 0x0f
281 #define QIXIS_LBMAP_SHIFT 0
282 #define QIXIS_LBMAP_DFLTBANK 0x00
283 #define QIXIS_LBMAP_ALTBANK 0x04
284 #define QIXIS_LBMAP_NAND 0x09
285 #define QIXIS_LBMAP_SD 0x00
286 #define QIXIS_RCW_SRC_NAND 0x104
287 #define QIXIS_RCW_SRC_SD 0x040
288 #define QIXIS_RST_CTL_RESET 0x83
289 #define QIXIS_RST_FORCE_MEM 0x1
290 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
291 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
292 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
293 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
295 #define CONFIG_SYS_CSPR3_EXT (0xf)
296 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
300 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
301 #define CONFIG_SYS_CSOR3 0x0
302 /* QIXIS Timing parameters for IFC CS3 */
303 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
304 FTIM0_GPCM_TEADC(0x0e) | \
305 FTIM0_GPCM_TEAHC(0x0e))
306 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
307 FTIM1_GPCM_TRAD(0x3f))
308 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
309 FTIM2_GPCM_TCH(0x8) | \
310 FTIM2_GPCM_TWP(0x1f))
311 #define CONFIG_SYS_CS3_FTIM3 0x0
313 /* NAND Flash on IFC */
314 #define CONFIG_NAND_FSL_IFC
315 #define CONFIG_SYS_NAND_BASE 0xff800000
316 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
318 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
319 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
320 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
321 | CSPR_MSEL_NAND /* MSEL = NAND */ \
323 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
325 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
326 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
327 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
328 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
329 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
330 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
331 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
333 #define CONFIG_SYS_NAND_ONFI_DETECTION
335 /* ONFI NAND Flash mode0 Timing Params */
336 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
337 FTIM0_NAND_TWP(0x18) | \
338 FTIM0_NAND_TWCHT(0x07) | \
339 FTIM0_NAND_TWH(0x0a))
340 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
341 FTIM1_NAND_TWBE(0x39) | \
342 FTIM1_NAND_TRR(0x0e) | \
343 FTIM1_NAND_TRP(0x18))
344 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
345 FTIM2_NAND_TREH(0x0a) | \
346 FTIM2_NAND_TWHRE(0x1e))
347 #define CONFIG_SYS_NAND_FTIM3 0x0
349 #define CONFIG_SYS_NAND_DDR_LAW 11
350 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
351 #define CONFIG_SYS_MAX_NAND_DEVICE 1
352 #define CONFIG_CMD_NAND
353 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
355 #if defined(CONFIG_NAND)
356 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
357 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
358 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
359 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
360 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
361 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
362 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
363 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
364 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
365 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
366 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
367 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
368 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
369 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
370 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
371 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
372 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
373 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
374 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
375 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
376 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
377 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
378 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
379 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
381 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
382 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
383 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
384 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
385 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
386 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
387 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
388 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
389 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
390 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
391 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
392 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
393 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
394 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
395 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
396 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
397 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
398 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
399 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
400 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
401 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
402 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
403 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
404 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
407 #if defined(CONFIG_RAMBOOT_PBL)
408 #define CONFIG_SYS_RAMBOOT
411 #ifdef CONFIG_SPL_BUILD
412 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
414 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
417 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
418 #define CONFIG_MISC_INIT_R
419 #define CONFIG_HWCONFIG
421 /* define to use L1 as initial stack */
422 #define CONFIG_L1_INIT_RAM
423 #define CONFIG_SYS_INIT_RAM_LOCK
424 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
425 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
426 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
427 /* The assembler doesn't like typecast */
428 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
429 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
430 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
431 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
432 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
433 GENERATED_GBL_DATA_SIZE)
434 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
435 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
436 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
441 #define CONFIG_CONS_INDEX 1
442 #define CONFIG_SYS_NS16550_SERIAL
443 #define CONFIG_SYS_NS16550_REG_SIZE 1
444 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
445 #define CONFIG_SYS_BAUDRATE_TABLE \
446 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
447 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
448 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
449 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
450 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
455 #define CONFIG_SYS_I2C
456 #define CONFIG_SYS_I2C_FSL
457 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
458 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
459 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
460 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
461 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
462 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
463 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
464 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
465 #define CONFIG_SYS_FSL_I2C_SPEED 100000
466 #define CONFIG_SYS_FSL_I2C2_SPEED 100000
467 #define CONFIG_SYS_FSL_I2C3_SPEED 100000
468 #define CONFIG_SYS_FSL_I2C4_SPEED 100000
469 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
470 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
471 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
472 #define I2C_MUX_CH_DEFAULT 0x8
474 #define I2C_MUX_CH_VOL_MONITOR 0xa
476 /* Voltage monitor on channel 2*/
477 #define I2C_VOL_MONITOR_ADDR 0x40
478 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
479 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
480 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
482 #define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv"
483 #ifndef CONFIG_SPL_BUILD
486 #define CONFIG_VOL_MONITOR_IR36021_SET
487 #define CONFIG_VOL_MONITOR_IR36021_READ
488 /* The lowest and highest voltage allowed for T208xQDS */
489 #define VDD_MV_MIN 819
490 #define VDD_MV_MAX 1212
495 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
496 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
497 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
498 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
499 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
500 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
502 * for slave u-boot IMAGE instored in master memory space,
503 * PHYS must be aligned based on the SIZE
505 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
506 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
507 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
508 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
510 * for slave UCODE and ENV instored in master memory space,
511 * PHYS must be aligned based on the SIZE
513 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
514 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
515 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
517 /* slave core release by master*/
518 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
519 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
522 * SRIO_PCIE_BOOT - SLAVE
524 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
525 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
526 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
527 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
531 * eSPI - Enhanced SPI
533 #ifdef CONFIG_SPI_FLASH
534 #ifndef CONFIG_SPL_BUILD
537 #define CONFIG_SPI_FLASH_BAR
538 #define CONFIG_SF_DEFAULT_SPEED 10000000
539 #define CONFIG_SF_DEFAULT_MODE 0
544 * Memory space is mapped 1-1, but I/O space must start from 0.
546 #define CONFIG_PCIE1 /* PCIE controller 1 */
547 #define CONFIG_PCIE2 /* PCIE controller 2 */
548 #define CONFIG_PCIE3 /* PCIE controller 3 */
549 #define CONFIG_PCIE4 /* PCIE controller 4 */
550 #define CONFIG_FSL_PCIE_RESET
551 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
552 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
553 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
554 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
555 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
556 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
557 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
558 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
559 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
560 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
561 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
563 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
564 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
565 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
566 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
567 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
568 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
569 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
570 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
571 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
573 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
574 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
575 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
576 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
577 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
578 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
579 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
580 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
581 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
583 /* controller 4, Base address 203000 */
584 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
585 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
586 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
587 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
588 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
589 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
590 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
593 #define CONFIG_PCI_INDIRECT_BRIDGE
594 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
595 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
596 #define CONFIG_DOS_PARTITION
600 #ifndef CONFIG_NOBQFMAN
601 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
602 #define CONFIG_SYS_BMAN_NUM_PORTALS 18
603 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
604 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
605 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
606 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
607 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
608 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
609 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
610 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
611 CONFIG_SYS_BMAN_CENA_SIZE)
612 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
613 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
614 #define CONFIG_SYS_QMAN_NUM_PORTALS 18
615 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
616 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
617 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
618 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
619 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
620 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
621 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
622 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
623 CONFIG_SYS_QMAN_CENA_SIZE)
624 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
625 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
627 #define CONFIG_SYS_DPAA_FMAN
628 #define CONFIG_SYS_DPAA_PME
629 #define CONFIG_SYS_PMAN
630 #define CONFIG_SYS_DPAA_DCE
631 #define CONFIG_SYS_DPAA_RMAN /* RMan */
632 #define CONFIG_SYS_INTERLAKEN
634 /* Default address of microcode for the Linux Fman driver */
635 #if defined(CONFIG_SPIFLASH)
637 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
638 * env, so we got 0x110000.
640 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
641 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
642 #elif defined(CONFIG_SDCARD)
644 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
645 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
646 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
648 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
649 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
650 #elif defined(CONFIG_NAND)
651 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
652 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
653 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
655 * Slave has no ucode locally, it can fetch this from remote. When implementing
656 * in two corenet boards, slave's ucode could be stored in master's memory
657 * space, the address can be mapped from slave TLB->slave LAW->
658 * slave SRIO or PCIE outbound window->master inbound window->
659 * master LAW->the ucode address in master's memory space.
661 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
662 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
664 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
665 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
667 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
668 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
669 #endif /* CONFIG_NOBQFMAN */
671 #ifdef CONFIG_SYS_DPAA_FMAN
672 #define CONFIG_FMAN_ENET
673 #define CONFIG_PHYLIB_10G
674 #define CONFIG_PHY_VITESSE
675 #define CONFIG_PHY_REALTEK
676 #define CONFIG_PHY_TERANETICS
677 #define RGMII_PHY1_ADDR 0x1
678 #define RGMII_PHY2_ADDR 0x2
679 #define FM1_10GEC1_PHY_ADDR 0x3
680 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
681 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
682 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
683 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
686 #ifdef CONFIG_FMAN_ENET
687 #define CONFIG_MII /* MII PHY management */
688 #define CONFIG_ETHPRIME "FM1@DTSEC3"
689 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
695 #ifdef CONFIG_FSL_SATA_V2
696 #define CONFIG_LIBATA
697 #define CONFIG_FSL_SATA
698 #define CONFIG_SYS_SATA_MAX_DEVICE 2
700 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
701 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
703 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
704 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
706 #define CONFIG_CMD_SATA
707 #define CONFIG_DOS_PARTITION
713 #ifdef CONFIG_USB_EHCI
714 #define CONFIG_USB_EHCI_FSL
715 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
716 #define CONFIG_HAS_FSL_DR_USB
723 #define CONFIG_FSL_ESDHC
724 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
725 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
726 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
727 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
728 #define CONFIG_GENERIC_MMC
729 #define CONFIG_DOS_PARTITION
730 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT
734 * Dynamic MTD Partition support with mtdparts
736 #ifndef CONFIG_SYS_NO_FLASH
737 #define CONFIG_MTD_DEVICE
738 #define CONFIG_MTD_PARTITIONS
739 #define CONFIG_CMD_MTDPARTS
740 #define CONFIG_FLASH_CFI_MTD
741 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
743 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
744 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
745 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \
746 "1m(uboot),5m(kernel),128k(dtb),-(user)"
752 #define CONFIG_LOADS_ECHO /* echo on for serial download */
753 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
756 * Command line configuration.
758 #define CONFIG_CMD_ERRATA
759 #define CONFIG_CMD_IRQ
760 #define CONFIG_CMD_REGINFO
763 #define CONFIG_CMD_PCI
766 /* Hash command with SHA acceleration supported in hardware */
767 #ifdef CONFIG_FSL_CAAM
768 #define CONFIG_CMD_HASH
769 #define CONFIG_SHA_HW_ACCEL
773 * Miscellaneous configurable options
775 #define CONFIG_SYS_LONGHELP /* undef to save memory */
776 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
777 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
778 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
779 #ifdef CONFIG_CMD_KGDB
780 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
782 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
784 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
785 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
786 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
789 * For booting Linux, the board info and command line data
790 * have to be in the first 64 MB of memory, since this is
791 * the maximum mapped by the Linux kernel during initialization.
793 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
794 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
796 #ifdef CONFIG_CMD_KGDB
797 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
798 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
802 * Environment Configuration
804 #define CONFIG_ROOTPATH "/opt/nfsroot"
805 #define CONFIG_BOOTFILE "uImage"
806 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
808 /* default location for tftp and bootm */
809 #define CONFIG_LOADADDR 1000000
810 #define CONFIG_BAUDRATE 115200
811 #define __USB_PHY_TYPE utmi
813 #define CONFIG_EXTRA_ENV_SETTINGS \
814 "hwconfig=fsl_ddr:" \
815 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
817 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
819 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
820 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
821 "tftpflash=tftpboot $loadaddr $uboot && " \
822 "protect off $ubootaddr +$filesize && " \
823 "erase $ubootaddr +$filesize && " \
824 "cp.b $loadaddr $ubootaddr $filesize && " \
825 "protect on $ubootaddr +$filesize && " \
826 "cmp.b $loadaddr $ubootaddr $filesize\0" \
827 "consoledev=ttyS0\0" \
828 "ramdiskaddr=2000000\0" \
829 "ramdiskfile=t2080qds/ramdisk.uboot\0" \
830 "fdtaddr=1e00000\0" \
831 "fdtfile=t2080qds/t2080qds.dtb\0" \
835 * For emulation this causes u-boot to jump to the start of the
836 * proof point app code automatically
838 #define CONFIG_PROOF_POINTS \
839 "setenv bootargs root=/dev/$bdev rw " \
840 "console=$consoledev,$baudrate $othbootargs;" \
841 "cpu 1 release 0x29000000 - - -;" \
842 "cpu 2 release 0x29000000 - - -;" \
843 "cpu 3 release 0x29000000 - - -;" \
844 "cpu 4 release 0x29000000 - - -;" \
845 "cpu 5 release 0x29000000 - - -;" \
846 "cpu 6 release 0x29000000 - - -;" \
847 "cpu 7 release 0x29000000 - - -;" \
850 #define CONFIG_HVBOOT \
851 "setenv bootargs config-addr=0x60000000; " \
852 "bootm 0x01000000 - 0x00f00000"
855 "setenv bootargs root=/dev/$bdev rw " \
856 "console=$consoledev,$baudrate $othbootargs;" \
857 "cpu 1 release 0x01000000 - - -;" \
858 "cpu 2 release 0x01000000 - - -;" \
859 "cpu 3 release 0x01000000 - - -;" \
860 "cpu 4 release 0x01000000 - - -;" \
861 "cpu 5 release 0x01000000 - - -;" \
862 "cpu 6 release 0x01000000 - - -;" \
863 "cpu 7 release 0x01000000 - - -;" \
866 #define CONFIG_LINUX \
867 "setenv bootargs root=/dev/ram rw " \
868 "console=$consoledev,$baudrate $othbootargs;" \
869 "setenv ramdiskaddr 0x02000000;" \
870 "setenv fdtaddr 0x00c00000;" \
871 "setenv loadaddr 0x1000000;" \
872 "bootm $loadaddr $ramdiskaddr $fdtaddr"
874 #define CONFIG_HDBOOT \
875 "setenv bootargs root=/dev/$bdev rw " \
876 "console=$consoledev,$baudrate $othbootargs;" \
877 "tftp $loadaddr $bootfile;" \
878 "tftp $fdtaddr $fdtfile;" \
879 "bootm $loadaddr - $fdtaddr"
881 #define CONFIG_NFSBOOTCOMMAND \
882 "setenv bootargs root=/dev/nfs rw " \
883 "nfsroot=$serverip:$rootpath " \
884 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
885 "console=$consoledev,$baudrate $othbootargs;" \
886 "tftp $loadaddr $bootfile;" \
887 "tftp $fdtaddr $fdtfile;" \
888 "bootm $loadaddr - $fdtaddr"
890 #define CONFIG_RAMBOOTCOMMAND \
891 "setenv bootargs root=/dev/ram rw " \
892 "console=$consoledev,$baudrate $othbootargs;" \
893 "tftp $ramdiskaddr $ramdiskfile;" \
894 "tftp $loadaddr $bootfile;" \
895 "tftp $fdtaddr $fdtfile;" \
896 "bootm $loadaddr $ramdiskaddr $fdtaddr"
898 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
900 #include <asm/fsl_secure_boot.h>
902 #endif /* __T208xQDS_H */