1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2011-2013 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
8 * T2080/T2081 QDS board configuration file
14 #include <linux/stringify.h>
16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
17 #if defined(CONFIG_ARCH_T2080)
18 #define CONFIG_FSL_SATA_V2
19 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
20 #define CONFIG_SRIO1 /* SRIO port 1 */
21 #define CONFIG_SRIO2 /* SRIO port 2 */
24 /* High Level Configuration Options */
25 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
26 #define CONFIG_ENABLE_36BIT_PHYS
28 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
29 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
31 #ifdef CONFIG_RAMBOOT_PBL
32 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
34 #define CONFIG_SPL_FLUSH_IMAGE
35 #define CONFIG_SPL_PAD_TO 0x40000
36 #define CONFIG_SPL_MAX_SIZE 0x28000
37 #define RESET_VECTOR_OFFSET 0x27FFC
38 #define BOOT_PAGE_OFFSET 0x27000
39 #ifdef CONFIG_SPL_BUILD
40 #define CONFIG_SPL_SKIP_RELOCATE
41 #define CONFIG_SPL_COMMON_INIT_DDR
42 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
45 #ifdef CONFIG_MTD_RAW_NAND
46 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
47 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
48 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
49 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
50 #if defined(CONFIG_ARCH_T2080)
51 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg
55 #ifdef CONFIG_SPIFLASH
56 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
57 #define CONFIG_SPL_SPI_FLASH_MINIMAL
58 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
59 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
60 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
62 #ifndef CONFIG_SPL_BUILD
63 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
65 #if defined(CONFIG_ARCH_T2080)
66 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg
71 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
72 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
73 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
74 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
75 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
76 #ifndef CONFIG_SPL_BUILD
77 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
79 #if defined(CONFIG_ARCH_T2080)
80 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg
84 #endif /* CONFIG_RAMBOOT_PBL */
86 #define CONFIG_SRIO_PCIE_BOOT_MASTER
87 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
88 /* Set 1M boot space */
89 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
90 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
91 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
92 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
95 #ifndef CONFIG_RESET_VECTOR_ADDRESS
96 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
100 * These can be toggled for performance analysis, otherwise use default.
102 #define CONFIG_SYS_CACHE_STASHING
103 #define CONFIG_BTB /* toggle branch predition */
104 #define CONFIG_DDR_ECC
105 #ifdef CONFIG_DDR_ECC
106 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
107 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
111 unsigned long get_board_sys_clk(void);
112 unsigned long get_board_ddr_clk(void);
115 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
116 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
119 * Config the L3 Cache as L3 SRAM
121 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
122 #define CONFIG_SYS_L3_SIZE (512 << 10)
123 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
124 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
125 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
126 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
127 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
129 #define CONFIG_SYS_DCSRBAR 0xf0000000
130 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
133 #define CONFIG_SYS_I2C_EEPROM_NXID
134 #define CONFIG_SYS_EEPROM_BUS_NUM 0
139 #define CONFIG_VERY_BIG_RAM
140 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
141 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
142 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
143 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
144 #define CONFIG_DDR_SPD
145 #define CONFIG_SYS_SPD_BUS_NUM 0
146 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
147 #define SPD_EEPROM_ADDRESS1 0x51
148 #define SPD_EEPROM_ADDRESS2 0x52
149 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
150 #define CTRL_INTLV_PREFERED cacheline
155 #define CONFIG_SYS_FLASH_BASE 0xe0000000
156 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
157 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
158 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
160 CSPR_PORT_SIZE_16 | \
163 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
164 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
165 CSPR_PORT_SIZE_16 | \
168 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
169 /* NOR Flash Timing Params */
170 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
172 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
173 FTIM0_NOR_TEADC(0x5) | \
174 FTIM0_NOR_TEAHC(0x5))
175 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
176 FTIM1_NOR_TRAD_NOR(0x1A) |\
177 FTIM1_NOR_TSEQRAD_NOR(0x13))
178 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
179 FTIM2_NOR_TCH(0x4) | \
180 FTIM2_NOR_TWPH(0x0E) | \
182 #define CONFIG_SYS_NOR_FTIM3 0x0
184 #define CONFIG_SYS_FLASH_QUIET_TEST
185 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
187 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
188 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
189 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
190 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
192 #define CONFIG_SYS_FLASH_EMPTY_INFO
193 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
194 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
196 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
197 #define QIXIS_BASE 0xffdf0000
198 #define QIXIS_LBMAP_SWITCH 6
199 #define QIXIS_LBMAP_MASK 0x0f
200 #define QIXIS_LBMAP_SHIFT 0
201 #define QIXIS_LBMAP_DFLTBANK 0x00
202 #define QIXIS_LBMAP_ALTBANK 0x04
203 #define QIXIS_LBMAP_NAND 0x09
204 #define QIXIS_LBMAP_SD 0x00
205 #define QIXIS_RCW_SRC_NAND 0x104
206 #define QIXIS_RCW_SRC_SD 0x040
207 #define QIXIS_RST_CTL_RESET 0x83
208 #define QIXIS_RST_FORCE_MEM 0x1
209 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
210 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
211 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
212 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
214 #define CONFIG_SYS_CSPR3_EXT (0xf)
215 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
219 #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
220 #define CONFIG_SYS_CSOR3 0x0
221 /* QIXIS Timing parameters for IFC CS3 */
222 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
223 FTIM0_GPCM_TEADC(0x0e) | \
224 FTIM0_GPCM_TEAHC(0x0e))
225 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
226 FTIM1_GPCM_TRAD(0x3f))
227 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
228 FTIM2_GPCM_TCH(0x8) | \
229 FTIM2_GPCM_TWP(0x1f))
230 #define CONFIG_SYS_CS3_FTIM3 0x0
232 /* NAND Flash on IFC */
233 #define CONFIG_NAND_FSL_IFC
234 #define CONFIG_SYS_NAND_BASE 0xff800000
235 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
237 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
238 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
239 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
240 | CSPR_MSEL_NAND /* MSEL = NAND */ \
242 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
244 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
245 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
246 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
247 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
248 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
249 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
250 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
252 #define CONFIG_SYS_NAND_ONFI_DETECTION
254 /* ONFI NAND Flash mode0 Timing Params */
255 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
256 FTIM0_NAND_TWP(0x18) | \
257 FTIM0_NAND_TWCHT(0x07) | \
258 FTIM0_NAND_TWH(0x0a))
259 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
260 FTIM1_NAND_TWBE(0x39) | \
261 FTIM1_NAND_TRR(0x0e) | \
262 FTIM1_NAND_TRP(0x18))
263 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
264 FTIM2_NAND_TREH(0x0a) | \
265 FTIM2_NAND_TWHRE(0x1e))
266 #define CONFIG_SYS_NAND_FTIM3 0x0
268 #define CONFIG_SYS_NAND_DDR_LAW 11
269 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
270 #define CONFIG_SYS_MAX_NAND_DEVICE 1
271 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
273 #if defined(CONFIG_MTD_RAW_NAND)
274 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
275 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
276 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
277 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
278 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
279 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
280 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
281 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
282 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
283 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
284 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
285 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
286 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
287 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
288 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
289 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
290 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
291 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
292 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
293 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
294 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
295 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
296 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
297 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
299 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
300 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
301 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
302 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
303 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
304 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
305 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
306 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
307 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
308 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
309 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
310 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
311 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
312 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
313 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
314 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
315 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
316 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
317 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
318 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
319 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
320 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
321 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
322 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
325 #if defined(CONFIG_RAMBOOT_PBL)
326 #define CONFIG_SYS_RAMBOOT
329 #ifdef CONFIG_SPL_BUILD
330 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
332 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
335 #define CONFIG_HWCONFIG
337 /* define to use L1 as initial stack */
338 #define CONFIG_L1_INIT_RAM
339 #define CONFIG_SYS_INIT_RAM_LOCK
340 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
341 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
342 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
343 /* The assembler doesn't like typecast */
344 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
345 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
346 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
347 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
348 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
349 GENERATED_GBL_DATA_SIZE)
350 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
351 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
352 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
357 #define CONFIG_SYS_NS16550_SERIAL
358 #define CONFIG_SYS_NS16550_REG_SIZE 1
359 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
360 #define CONFIG_SYS_BAUDRATE_TABLE \
361 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
362 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
363 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
364 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
365 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
371 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
372 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
373 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
374 #define I2C_MUX_CH_DEFAULT 0x8
376 #define I2C_MUX_CH_VOL_MONITOR 0xa
378 /* Voltage monitor on channel 2*/
379 #define I2C_VOL_MONITOR_ADDR 0x40
380 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
381 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
382 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
384 #define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv"
385 #ifndef CONFIG_SPL_BUILD
388 #define CONFIG_VOL_MONITOR_IR36021_SET
389 #define CONFIG_VOL_MONITOR_IR36021_READ
390 /* The lowest and highest voltage allowed for T208xQDS */
391 #define VDD_MV_MIN 819
392 #define VDD_MV_MAX 1212
397 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
398 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
399 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
400 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
401 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
402 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
404 * for slave u-boot IMAGE instored in master memory space,
405 * PHYS must be aligned based on the SIZE
407 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
408 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
409 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
410 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
412 * for slave UCODE and ENV instored in master memory space,
413 * PHYS must be aligned based on the SIZE
415 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
416 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
417 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
419 /* slave core release by master*/
420 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
421 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
424 * SRIO_PCIE_BOOT - SLAVE
426 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
427 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
428 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
429 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
433 * eSPI - Enhanced SPI
438 * Memory space is mapped 1-1, but I/O space must start from 0.
440 #define CONFIG_PCIE1 /* PCIE controller 1 */
441 #define CONFIG_PCIE2 /* PCIE controller 2 */
442 #define CONFIG_PCIE3 /* PCIE controller 3 */
443 #define CONFIG_PCIE4 /* PCIE controller 4 */
444 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
445 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
446 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
447 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
448 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
449 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
451 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
452 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
453 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
454 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
455 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
457 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
458 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
459 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
460 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
461 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
463 /* controller 4, Base address 203000 */
464 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
465 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
466 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
469 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
473 #ifndef CONFIG_NOBQFMAN
474 #define CONFIG_SYS_BMAN_NUM_PORTALS 18
475 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
476 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
477 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
478 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
479 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
480 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
481 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
482 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
483 CONFIG_SYS_BMAN_CENA_SIZE)
484 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
485 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
486 #define CONFIG_SYS_QMAN_NUM_PORTALS 18
487 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
488 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
489 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
490 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
491 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
492 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
493 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
494 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
495 CONFIG_SYS_QMAN_CENA_SIZE)
496 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
497 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
499 #define CONFIG_SYS_DPAA_FMAN
500 #define CONFIG_SYS_DPAA_PME
501 #define CONFIG_SYS_PMAN
502 #define CONFIG_SYS_DPAA_DCE
503 #define CONFIG_SYS_DPAA_RMAN /* RMan */
504 #define CONFIG_SYS_INTERLAKEN
506 /* Default address of microcode for the Linux Fman driver */
507 #if defined(CONFIG_SPIFLASH)
509 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
510 * env, so we got 0x110000.
512 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
513 #elif defined(CONFIG_SDCARD)
515 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
516 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
517 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
519 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
520 #elif defined(CONFIG_MTD_RAW_NAND)
521 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
522 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
524 * Slave has no ucode locally, it can fetch this from remote. When implementing
525 * in two corenet boards, slave's ucode could be stored in master's memory
526 * space, the address can be mapped from slave TLB->slave LAW->
527 * slave SRIO or PCIE outbound window->master inbound window->
528 * master LAW->the ucode address in master's memory space.
530 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
532 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
534 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
535 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
536 #endif /* CONFIG_NOBQFMAN */
538 #ifdef CONFIG_SYS_DPAA_FMAN
539 #define RGMII_PHY1_ADDR 0x1
540 #define RGMII_PHY2_ADDR 0x2
541 #define FM1_10GEC1_PHY_ADDR 0x3
542 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
543 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
544 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
545 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
548 #ifdef CONFIG_FMAN_ENET
549 #define CONFIG_ETHPRIME "FM1@DTSEC3"
555 #ifdef CONFIG_FSL_SATA_V2
556 #define CONFIG_SYS_SATA_MAX_DEVICE 2
558 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
559 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
561 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
562 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
569 #ifdef CONFIG_USB_EHCI_HCD
570 #define CONFIG_USB_EHCI_FSL
571 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
572 #define CONFIG_HAS_FSL_DR_USB
579 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
580 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
584 * Dynamic MTD Partition support with mtdparts
590 #define CONFIG_LOADS_ECHO /* echo on for serial download */
591 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
594 * Miscellaneous configurable options
596 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
599 * For booting Linux, the board info and command line data
600 * have to be in the first 64 MB of memory, since this is
601 * the maximum mapped by the Linux kernel during initialization.
603 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
604 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
606 #ifdef CONFIG_CMD_KGDB
607 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
608 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
612 * Environment Configuration
614 #define CONFIG_ROOTPATH "/opt/nfsroot"
615 #define CONFIG_BOOTFILE "uImage"
616 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
618 /* default location for tftp and bootm */
619 #define CONFIG_LOADADDR 1000000
620 #define __USB_PHY_TYPE utmi
622 #define CONFIG_EXTRA_ENV_SETTINGS \
623 "hwconfig=fsl_ddr:" \
624 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
626 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
628 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
629 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
630 "tftpflash=tftpboot $loadaddr $uboot && " \
631 "protect off $ubootaddr +$filesize && " \
632 "erase $ubootaddr +$filesize && " \
633 "cp.b $loadaddr $ubootaddr $filesize && " \
634 "protect on $ubootaddr +$filesize && " \
635 "cmp.b $loadaddr $ubootaddr $filesize\0" \
636 "consoledev=ttyS0\0" \
637 "ramdiskaddr=2000000\0" \
638 "ramdiskfile=t2080qds/ramdisk.uboot\0" \
639 "fdtaddr=1e00000\0" \
640 "fdtfile=t2080qds/t2080qds.dtb\0" \
644 * For emulation this causes u-boot to jump to the start of the
645 * proof point app code automatically
647 #define CONFIG_PROOF_POINTS \
648 "setenv bootargs root=/dev/$bdev rw " \
649 "console=$consoledev,$baudrate $othbootargs;" \
650 "cpu 1 release 0x29000000 - - -;" \
651 "cpu 2 release 0x29000000 - - -;" \
652 "cpu 3 release 0x29000000 - - -;" \
653 "cpu 4 release 0x29000000 - - -;" \
654 "cpu 5 release 0x29000000 - - -;" \
655 "cpu 6 release 0x29000000 - - -;" \
656 "cpu 7 release 0x29000000 - - -;" \
659 #define CONFIG_HVBOOT \
660 "setenv bootargs config-addr=0x60000000; " \
661 "bootm 0x01000000 - 0x00f00000"
664 "setenv bootargs root=/dev/$bdev rw " \
665 "console=$consoledev,$baudrate $othbootargs;" \
666 "cpu 1 release 0x01000000 - - -;" \
667 "cpu 2 release 0x01000000 - - -;" \
668 "cpu 3 release 0x01000000 - - -;" \
669 "cpu 4 release 0x01000000 - - -;" \
670 "cpu 5 release 0x01000000 - - -;" \
671 "cpu 6 release 0x01000000 - - -;" \
672 "cpu 7 release 0x01000000 - - -;" \
675 #define CONFIG_LINUX \
676 "setenv bootargs root=/dev/ram rw " \
677 "console=$consoledev,$baudrate $othbootargs;" \
678 "setenv ramdiskaddr 0x02000000;" \
679 "setenv fdtaddr 0x00c00000;" \
680 "setenv loadaddr 0x1000000;" \
681 "bootm $loadaddr $ramdiskaddr $fdtaddr"
683 #define CONFIG_HDBOOT \
684 "setenv bootargs root=/dev/$bdev rw " \
685 "console=$consoledev,$baudrate $othbootargs;" \
686 "tftp $loadaddr $bootfile;" \
687 "tftp $fdtaddr $fdtfile;" \
688 "bootm $loadaddr - $fdtaddr"
690 #define CONFIG_NFSBOOTCOMMAND \
691 "setenv bootargs root=/dev/nfs rw " \
692 "nfsroot=$serverip:$rootpath " \
693 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
694 "console=$consoledev,$baudrate $othbootargs;" \
695 "tftp $loadaddr $bootfile;" \
696 "tftp $fdtaddr $fdtfile;" \
697 "bootm $loadaddr - $fdtaddr"
699 #define CONFIG_RAMBOOTCOMMAND \
700 "setenv bootargs root=/dev/ram rw " \
701 "console=$consoledev,$baudrate $othbootargs;" \
702 "tftp $ramdiskaddr $ramdiskfile;" \
703 "tftp $loadaddr $bootfile;" \
704 "tftp $fdtaddr $fdtfile;" \
705 "bootm $loadaddr $ramdiskaddr $fdtaddr"
707 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
709 #include <asm/fsl_secure_boot.h>
711 #endif /* __T208xQDS_H */