Merge branch 'master' of git://git.denx.de/u-boot-spi
[platform/kernel/u-boot.git] / include / configs / T208xQDS.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2011-2013 Freescale Semiconductor, Inc.
4  */
5
6 /*
7  * T2080/T2081 QDS board configuration file
8  */
9
10 #ifndef __T208xQDS_H
11 #define __T208xQDS_H
12
13 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
14 #if defined(CONFIG_ARCH_T2080)
15 #define CONFIG_FSL_SATA_V2
16 #define CONFIG_SYS_SRIO         /* Enable Serial RapidIO Support */
17 #define CONFIG_SRIO1            /* SRIO port 1 */
18 #define CONFIG_SRIO2            /* SRIO port 2 */
19 #elif defined(CONFIG_ARCH_T2081)
20 #endif
21
22 /* High Level Configuration Options */
23 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
24 #define CONFIG_ENABLE_36BIT_PHYS
25
26 #ifdef CONFIG_PHYS_64BIT
27 #define CONFIG_ADDR_MAP 1
28 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
29 #endif
30
31 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
32 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
33 #define CONFIG_ENV_OVERWRITE
34
35 #ifdef CONFIG_RAMBOOT_PBL
36 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
37
38 #define CONFIG_SPL_FLUSH_IMAGE
39 #define CONFIG_SPL_PAD_TO               0x40000
40 #define CONFIG_SPL_MAX_SIZE             0x28000
41 #define RESET_VECTOR_OFFSET             0x27FFC
42 #define BOOT_PAGE_OFFSET                0x27000
43 #ifdef CONFIG_SPL_BUILD
44 #define CONFIG_SPL_SKIP_RELOCATE
45 #define CONFIG_SPL_COMMON_INIT_DDR
46 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
47 #endif
48
49 #ifdef CONFIG_NAND
50 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
51 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
52 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
53 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
54 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
55 #if defined(CONFIG_ARCH_T2080)
56 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg
57 #elif defined(CONFIG_ARCH_T2081)
58 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg
59 #endif
60 #define CONFIG_SPL_NAND_BOOT
61 #endif
62
63 #ifdef CONFIG_SPIFLASH
64 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
65 #define CONFIG_SPL_SPI_FLASH_MINIMAL
66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
69 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
70 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
71 #ifndef CONFIG_SPL_BUILD
72 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
73 #endif
74 #if defined(CONFIG_ARCH_T2080)
75 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg
76 #elif defined(CONFIG_ARCH_T2081)
77 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg
78 #endif
79 #define CONFIG_SPL_SPI_BOOT
80 #endif
81
82 #ifdef CONFIG_SDCARD
83 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
84 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
85 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
86 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
87 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
88 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
89 #ifndef CONFIG_SPL_BUILD
90 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
91 #endif
92 #if defined(CONFIG_ARCH_T2080)
93 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg
94 #elif defined(CONFIG_ARCH_T2081)
95 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg
96 #endif
97 #define CONFIG_SPL_MMC_BOOT
98 #endif
99
100 #endif /* CONFIG_RAMBOOT_PBL */
101
102 #define CONFIG_SRIO_PCIE_BOOT_MASTER
103 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
104 /* Set 1M boot space */
105 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
106 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
107                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
108 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
109 #endif
110
111 #ifndef CONFIG_RESET_VECTOR_ADDRESS
112 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
113 #endif
114
115 /*
116  * These can be toggled for performance analysis, otherwise use default.
117  */
118 #define CONFIG_SYS_CACHE_STASHING
119 #define CONFIG_BTB              /* toggle branch predition */
120 #define CONFIG_DDR_ECC
121 #ifdef CONFIG_DDR_ECC
122 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
123 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
124 #endif
125
126 #if defined(CONFIG_SPIFLASH)
127 #define CONFIG_ENV_SIZE         0x2000     /* 8KB */
128 #define CONFIG_ENV_OFFSET       0x100000   /* 1MB */
129 #define CONFIG_ENV_SECT_SIZE    0x10000
130 #elif defined(CONFIG_SDCARD)
131 #define CONFIG_SYS_MMC_ENV_DEV  0
132 #define CONFIG_ENV_SIZE         0x2000
133 #define CONFIG_ENV_OFFSET       (512 * 0x800)
134 #elif defined(CONFIG_NAND)
135 #define CONFIG_ENV_SIZE         0x2000
136 #define CONFIG_ENV_OFFSET       (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
137 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
138 #define CONFIG_ENV_ADDR         0xffe20000
139 #define CONFIG_ENV_SIZE         0x2000
140 #elif defined(CONFIG_ENV_IS_NOWHERE)
141 #define CONFIG_ENV_SIZE         0x2000
142 #else
143 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
144 #define CONFIG_ENV_SIZE         0x2000
145 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
146 #endif
147
148 #ifndef __ASSEMBLY__
149 unsigned long get_board_sys_clk(void);
150 unsigned long get_board_ddr_clk(void);
151 #endif
152
153 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
154 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
155
156 /*
157  * Config the L3 Cache as L3 SRAM
158  */
159 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
160 #define CONFIG_SYS_L3_SIZE              (512 << 10)
161 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
162 #ifdef CONFIG_RAMBOOT_PBL
163 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
164 #endif
165 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
166 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
167 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
168
169 #define CONFIG_SYS_DCSRBAR      0xf0000000
170 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
171
172 /* EEPROM */
173 #define CONFIG_ID_EEPROM
174 #define CONFIG_SYS_I2C_EEPROM_NXID
175 #define CONFIG_SYS_EEPROM_BUS_NUM       0
176 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
177 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
178
179 /*
180  * DDR Setup
181  */
182 #define CONFIG_VERY_BIG_RAM
183 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
184 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
185 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
186 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
187 #define CONFIG_DDR_SPD
188 #define CONFIG_SYS_SPD_BUS_NUM  0
189 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
190 #define SPD_EEPROM_ADDRESS1     0x51
191 #define SPD_EEPROM_ADDRESS2     0x52
192 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
193 #define CTRL_INTLV_PREFERED     cacheline
194
195 /*
196  * IFC Definitions
197  */
198 #define CONFIG_SYS_FLASH_BASE           0xe0000000
199 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
200 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
201 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
202                                 + 0x8000000) | \
203                                 CSPR_PORT_SIZE_16 | \
204                                 CSPR_MSEL_NOR | \
205                                 CSPR_V)
206 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
207 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
208                                 CSPR_PORT_SIZE_16 | \
209                                 CSPR_MSEL_NOR | \
210                                 CSPR_V)
211 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
212 /* NOR Flash Timing Params */
213 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
214
215 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
216                                 FTIM0_NOR_TEADC(0x5) | \
217                                 FTIM0_NOR_TEAHC(0x5))
218 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
219                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
220                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
221 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
222                                 FTIM2_NOR_TCH(0x4) | \
223                                 FTIM2_NOR_TWPH(0x0E) | \
224                                 FTIM2_NOR_TWP(0x1c))
225 #define CONFIG_SYS_NOR_FTIM3    0x0
226
227 #define CONFIG_SYS_FLASH_QUIET_TEST
228 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
229
230 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
231 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
232 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
233 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
234
235 #define CONFIG_SYS_FLASH_EMPTY_INFO
236 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
237                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
238
239 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
240 #define QIXIS_BASE                      0xffdf0000
241 #define QIXIS_LBMAP_SWITCH              6
242 #define QIXIS_LBMAP_MASK                0x0f
243 #define QIXIS_LBMAP_SHIFT               0
244 #define QIXIS_LBMAP_DFLTBANK            0x00
245 #define QIXIS_LBMAP_ALTBANK             0x04
246 #define QIXIS_LBMAP_NAND                0x09
247 #define QIXIS_LBMAP_SD                  0x00
248 #define QIXIS_RCW_SRC_NAND              0x104
249 #define QIXIS_RCW_SRC_SD                0x040
250 #define QIXIS_RST_CTL_RESET             0x83
251 #define QIXIS_RST_FORCE_MEM             0x1
252 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
253 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
254 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
255 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
256
257 #define CONFIG_SYS_CSPR3_EXT    (0xf)
258 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
259                                 | CSPR_PORT_SIZE_8 \
260                                 | CSPR_MSEL_GPCM \
261                                 | CSPR_V)
262 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
263 #define CONFIG_SYS_CSOR3        0x0
264 /* QIXIS Timing parameters for IFC CS3 */
265 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
266                                         FTIM0_GPCM_TEADC(0x0e) | \
267                                         FTIM0_GPCM_TEAHC(0x0e))
268 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
269                                         FTIM1_GPCM_TRAD(0x3f))
270 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
271                                         FTIM2_GPCM_TCH(0x8) | \
272                                         FTIM2_GPCM_TWP(0x1f))
273 #define CONFIG_SYS_CS3_FTIM3            0x0
274
275 /* NAND Flash on IFC */
276 #define CONFIG_NAND_FSL_IFC
277 #define CONFIG_SYS_NAND_BASE            0xff800000
278 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
279
280 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
281 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
282                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
283                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
284                                 | CSPR_V)
285 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
286
287 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
288                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
289                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
290                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
291                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
292                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
293                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
294
295 #define CONFIG_SYS_NAND_ONFI_DETECTION
296
297 /* ONFI NAND Flash mode0 Timing Params */
298 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
299                                         FTIM0_NAND_TWP(0x18)    | \
300                                         FTIM0_NAND_TWCHT(0x07)  | \
301                                         FTIM0_NAND_TWH(0x0a))
302 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
303                                         FTIM1_NAND_TWBE(0x39)   | \
304                                         FTIM1_NAND_TRR(0x0e)    | \
305                                         FTIM1_NAND_TRP(0x18))
306 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
307                                         FTIM2_NAND_TREH(0x0a)   | \
308                                         FTIM2_NAND_TWHRE(0x1e))
309 #define CONFIG_SYS_NAND_FTIM3           0x0
310
311 #define CONFIG_SYS_NAND_DDR_LAW         11
312 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
313 #define CONFIG_SYS_MAX_NAND_DEVICE      1
314 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
315
316 #if defined(CONFIG_NAND)
317 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
318 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
319 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
320 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
321 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
322 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
323 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
324 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
325 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
326 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
327 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
328 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
329 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
330 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
331 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
332 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
333 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
334 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
335 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
336 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
337 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
338 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
339 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
340 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
341 #else
342 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
343 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
344 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
345 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
346 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
347 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
348 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
349 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
350 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
351 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
352 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
353 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
354 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
355 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
356 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
357 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
358 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
359 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
360 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
361 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
362 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
363 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
364 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
365 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
366 #endif
367
368 #if defined(CONFIG_RAMBOOT_PBL)
369 #define CONFIG_SYS_RAMBOOT
370 #endif
371
372 #ifdef CONFIG_SPL_BUILD
373 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
374 #else
375 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
376 #endif
377
378 #define CONFIG_HWCONFIG
379
380 /* define to use L1 as initial stack */
381 #define CONFIG_L1_INIT_RAM
382 #define CONFIG_SYS_INIT_RAM_LOCK
383 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
384 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
385 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
386 /* The assembler doesn't like typecast */
387 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
388                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
389                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
390 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
391 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
392                                                 GENERATED_GBL_DATA_SIZE)
393 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
394 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
395 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
396
397 /*
398  * Serial Port
399  */
400 #define CONFIG_SYS_NS16550_SERIAL
401 #define CONFIG_SYS_NS16550_REG_SIZE     1
402 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
403 #define CONFIG_SYS_BAUDRATE_TABLE       \
404         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
405 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
406 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
407 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
408 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
409
410 /*
411  * I2C
412  */
413 #define CONFIG_SYS_I2C
414 #define CONFIG_SYS_I2C_FSL
415 #define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
416 #define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
417 #define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
418 #define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
419 #define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
420 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
421 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
422 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
423 #define CONFIG_SYS_FSL_I2C_SPEED   100000
424 #define CONFIG_SYS_FSL_I2C2_SPEED  100000
425 #define CONFIG_SYS_FSL_I2C3_SPEED  100000
426 #define CONFIG_SYS_FSL_I2C4_SPEED  100000
427 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
428 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
429 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
430 #define I2C_MUX_CH_DEFAULT      0x8
431
432 #define I2C_MUX_CH_VOL_MONITOR 0xa
433
434 /* Voltage monitor on channel 2*/
435 #define I2C_VOL_MONITOR_ADDR           0x40
436 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
437 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
438 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
439
440 #define CONFIG_VID_FLS_ENV              "t208xqds_vdd_mv"
441 #ifndef CONFIG_SPL_BUILD
442 #define CONFIG_VID
443 #endif
444 #define CONFIG_VOL_MONITOR_IR36021_SET
445 #define CONFIG_VOL_MONITOR_IR36021_READ
446 /* The lowest and highest voltage allowed for T208xQDS */
447 #define VDD_MV_MIN                      819
448 #define VDD_MV_MAX                      1212
449
450 /*
451  * RapidIO
452  */
453 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
454 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
455 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
456 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
457 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
458 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
459 /*
460  * for slave u-boot IMAGE instored in master memory space,
461  * PHYS must be aligned based on the SIZE
462  */
463 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
464 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
465 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
466 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
467 /*
468  * for slave UCODE and ENV instored in master memory space,
469  * PHYS must be aligned based on the SIZE
470  */
471 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
472 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
473 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
474
475 /* slave core release by master*/
476 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
477 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
478
479 /*
480  * SRIO_PCIE_BOOT - SLAVE
481  */
482 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
483 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
484 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
485                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
486 #endif
487
488 /*
489  * eSPI - Enhanced SPI
490  */
491
492 /*
493  * General PCI
494  * Memory space is mapped 1-1, but I/O space must start from 0.
495  */
496 #define CONFIG_PCIE1            /* PCIE controller 1 */
497 #define CONFIG_PCIE2            /* PCIE controller 2 */
498 #define CONFIG_PCIE3            /* PCIE controller 3 */
499 #define CONFIG_PCIE4            /* PCIE controller 4 */
500 #define CONFIG_FSL_PCIE_RESET   /* pcie reset fix link width 2x-4x*/
501 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
502 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
503 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
504 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
505 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
506 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
507 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
508 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
509 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
510 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
511 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
512
513 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
514 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
515 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
516 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
517 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000 /* 256M */
518 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
519 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
520 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
521 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
522
523 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
524 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
525 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
526 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
527 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
528 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
529 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
530 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
531 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
532
533 /* controller 4, Base address 203000 */
534 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
535 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
536 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
537 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
538 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
539 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
540 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
541
542 #ifdef CONFIG_PCI
543 #define CONFIG_PCI_INDIRECT_BRIDGE
544 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
545 #endif
546
547 /* Qman/Bman */
548 #ifndef CONFIG_NOBQFMAN
549 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
550 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
551 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
552 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
553 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
554 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
555 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
556 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
557 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
558                                         CONFIG_SYS_BMAN_CENA_SIZE)
559 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
560 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
561 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
562 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
563 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
564 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
565 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
566 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
567 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
568 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
569 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
570                                         CONFIG_SYS_QMAN_CENA_SIZE)
571 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
572 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
573
574 #define CONFIG_SYS_DPAA_FMAN
575 #define CONFIG_SYS_DPAA_PME
576 #define CONFIG_SYS_PMAN
577 #define CONFIG_SYS_DPAA_DCE
578 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
579 #define CONFIG_SYS_INTERLAKEN
580
581 /* Default address of microcode for the Linux Fman driver */
582 #if defined(CONFIG_SPIFLASH)
583 /*
584  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
585  * env, so we got 0x110000.
586  */
587 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
588 #elif defined(CONFIG_SDCARD)
589 /*
590  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
591  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
592  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
593  */
594 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
595 #elif defined(CONFIG_NAND)
596 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
597 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
598 /*
599  * Slave has no ucode locally, it can fetch this from remote. When implementing
600  * in two corenet boards, slave's ucode could be stored in master's memory
601  * space, the address can be mapped from slave TLB->slave LAW->
602  * slave SRIO or PCIE outbound window->master inbound window->
603  * master LAW->the ucode address in master's memory space.
604  */
605 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
606 #else
607 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
608 #endif
609 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
610 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
611 #endif /* CONFIG_NOBQFMAN */
612
613 #ifdef CONFIG_SYS_DPAA_FMAN
614 #define CONFIG_PHY_VITESSE
615 #define CONFIG_PHY_REALTEK
616 #define CONFIG_PHY_TERANETICS
617 #define RGMII_PHY1_ADDR 0x1
618 #define RGMII_PHY2_ADDR 0x2
619 #define FM1_10GEC1_PHY_ADDR       0x3
620 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
621 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
622 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
623 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
624 #endif
625
626 #ifdef CONFIG_FMAN_ENET
627 #define CONFIG_ETHPRIME         "FM1@DTSEC3"
628 #endif
629
630 /*
631  * SATA
632  */
633 #ifdef CONFIG_FSL_SATA_V2
634 #define CONFIG_SYS_SATA_MAX_DEVICE      2
635 #define CONFIG_SATA1
636 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
637 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
638 #define CONFIG_SATA2
639 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
640 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
641 #define CONFIG_LBA48
642 #endif
643
644 /*
645  * USB
646  */
647 #ifdef CONFIG_USB_EHCI_HCD
648 #define CONFIG_USB_EHCI_FSL
649 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
650 #define CONFIG_HAS_FSL_DR_USB
651 #endif
652
653 /*
654  * SDHC
655  */
656 #ifdef CONFIG_MMC
657 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
658 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
659 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
660 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
661 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT
662 #endif
663
664 /*
665  * Dynamic MTD Partition support with mtdparts
666  */
667
668 /*
669  * Environment
670  */
671 #define CONFIG_LOADS_ECHO       /* echo on for serial download */
672 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
673
674 /*
675  * Miscellaneous configurable options
676  */
677 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
678
679 /*
680  * For booting Linux, the board info and command line data
681  * have to be in the first 64 MB of memory, since this is
682  * the maximum mapped by the Linux kernel during initialization.
683  */
684 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
685 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
686
687 #ifdef CONFIG_CMD_KGDB
688 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
689 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
690 #endif
691
692 /*
693  * Environment Configuration
694  */
695 #define CONFIG_ROOTPATH  "/opt/nfsroot"
696 #define CONFIG_BOOTFILE  "uImage"
697 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
698
699 /* default location for tftp and bootm */
700 #define CONFIG_LOADADDR         1000000
701 #define __USB_PHY_TYPE          utmi
702
703 #define CONFIG_EXTRA_ENV_SETTINGS                               \
704         "hwconfig=fsl_ddr:"                                     \
705         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
706         "bank_intlv=auto;"                                      \
707         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
708         "netdev=eth0\0"                                         \
709         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
710         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
711         "tftpflash=tftpboot $loadaddr $uboot && "               \
712         "protect off $ubootaddr +$filesize && "                 \
713         "erase $ubootaddr +$filesize && "                       \
714         "cp.b $loadaddr $ubootaddr $filesize && "               \
715         "protect on $ubootaddr +$filesize && "                  \
716         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
717         "consoledev=ttyS0\0"                                    \
718         "ramdiskaddr=2000000\0"                                 \
719         "ramdiskfile=t2080qds/ramdisk.uboot\0"                  \
720         "fdtaddr=1e00000\0"                                     \
721         "fdtfile=t2080qds/t2080qds.dtb\0"                       \
722         "bdev=sda3\0"
723
724 /*
725  * For emulation this causes u-boot to jump to the start of the
726  * proof point app code automatically
727  */
728 #define CONFIG_PROOF_POINTS                             \
729         "setenv bootargs root=/dev/$bdev rw "           \
730         "console=$consoledev,$baudrate $othbootargs;"   \
731         "cpu 1 release 0x29000000 - - -;"               \
732         "cpu 2 release 0x29000000 - - -;"               \
733         "cpu 3 release 0x29000000 - - -;"               \
734         "cpu 4 release 0x29000000 - - -;"               \
735         "cpu 5 release 0x29000000 - - -;"               \
736         "cpu 6 release 0x29000000 - - -;"               \
737         "cpu 7 release 0x29000000 - - -;"               \
738         "go 0x29000000"
739
740 #define CONFIG_HVBOOT                           \
741         "setenv bootargs config-addr=0x60000000; "      \
742         "bootm 0x01000000 - 0x00f00000"
743
744 #define CONFIG_ALU                              \
745         "setenv bootargs root=/dev/$bdev rw "           \
746         "console=$consoledev,$baudrate $othbootargs;"   \
747         "cpu 1 release 0x01000000 - - -;"               \
748         "cpu 2 release 0x01000000 - - -;"               \
749         "cpu 3 release 0x01000000 - - -;"               \
750         "cpu 4 release 0x01000000 - - -;"               \
751         "cpu 5 release 0x01000000 - - -;"               \
752         "cpu 6 release 0x01000000 - - -;"               \
753         "cpu 7 release 0x01000000 - - -;"               \
754         "go 0x01000000"
755
756 #define CONFIG_LINUX                            \
757         "setenv bootargs root=/dev/ram rw "             \
758         "console=$consoledev,$baudrate $othbootargs;"   \
759         "setenv ramdiskaddr 0x02000000;"                \
760         "setenv fdtaddr 0x00c00000;"                    \
761         "setenv loadaddr 0x1000000;"                    \
762         "bootm $loadaddr $ramdiskaddr $fdtaddr"
763
764 #define CONFIG_HDBOOT                                   \
765         "setenv bootargs root=/dev/$bdev rw "           \
766         "console=$consoledev,$baudrate $othbootargs;"   \
767         "tftp $loadaddr $bootfile;"                     \
768         "tftp $fdtaddr $fdtfile;"                       \
769         "bootm $loadaddr - $fdtaddr"
770
771 #define CONFIG_NFSBOOTCOMMAND                   \
772         "setenv bootargs root=/dev/nfs rw "     \
773         "nfsroot=$serverip:$rootpath "          \
774         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
775         "console=$consoledev,$baudrate $othbootargs;"   \
776         "tftp $loadaddr $bootfile;"             \
777         "tftp $fdtaddr $fdtfile;"               \
778         "bootm $loadaddr - $fdtaddr"
779
780 #define CONFIG_RAMBOOTCOMMAND                           \
781         "setenv bootargs root=/dev/ram rw "             \
782         "console=$consoledev,$baudrate $othbootargs;"   \
783         "tftp $ramdiskaddr $ramdiskfile;"               \
784         "tftp $loadaddr $bootfile;"                     \
785         "tftp $fdtaddr $fdtfile;"                       \
786         "bootm $loadaddr $ramdiskaddr $fdtaddr"
787
788 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
789
790 #include <asm/fsl_secure_boot.h>
791
792 #endif  /* __T208xQDS_H */