include/configs/T208xQDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2013 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 /*
   8  * T2080/T2081 QDS board configuration file
   9  */
  10
  11 #ifndef __T208xQDS_H
  12 #define __T208xQDS_H
  13
  14 #include <linux/stringify.h>
  15
  16 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  17 #if defined(CONFIG_ARCH_T2080)
  18 #define CONFIG_FSL_SATA_V2
  19 #define CONFIG_SYS_SRIO         /* Enable Serial RapidIO Support */
  20 #define CONFIG_SRIO1            /* SRIO port 1 */
  21 #define CONFIG_SRIO2            /* SRIO port 2 */
  22 #elif defined(CONFIG_ARCH_T2081)
  23 #endif
  24
  25 /* High Level Configuration Options */
  26 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
  27 #define CONFIG_ENABLE_36BIT_PHYS
  28
  29 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  30 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  31
  32 #ifdef CONFIG_RAMBOOT_PBL
  33 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
  34
  35 #define CONFIG_SPL_FLUSH_IMAGE
  36 #define CONFIG_SPL_PAD_TO               0x40000
  37 #define CONFIG_SPL_MAX_SIZE             0x28000
  38 #define RESET_VECTOR_OFFSET             0x27FFC
  39 #define BOOT_PAGE_OFFSET                0x27000
  40 #ifdef CONFIG_SPL_BUILD
  41 #define CONFIG_SPL_SKIP_RELOCATE
  42 #define CONFIG_SPL_COMMON_INIT_DDR
  43 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  44 #endif
  45
  46 #ifdef CONFIG_MTD_RAW_NAND
  47 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  48 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  49 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  50 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  51 #if defined(CONFIG_ARCH_T2080)
  52 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg
  53 #elif defined(CONFIG_ARCH_T2081)
  54 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg
  55 #endif
  56 #endif
  57
  58 #ifdef CONFIG_SPIFLASH
  59 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  60 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  62 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
  63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
  64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  65 #ifndef CONFIG_SPL_BUILD
  66 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  67 #endif
  68 #if defined(CONFIG_ARCH_T2080)
  69 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg
  70 #elif defined(CONFIG_ARCH_T2081)
  71 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg
  72 #endif
  73 #endif
  74
  75 #ifdef CONFIG_SDCARD
  76 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  77 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  78 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
  79 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
  80 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  81 #ifndef CONFIG_SPL_BUILD
  82 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  83 #endif
  84 #if defined(CONFIG_ARCH_T2080)
  85 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg
  86 #elif defined(CONFIG_ARCH_T2081)
  87 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg
  88 #endif
  89 #endif
  90
  91 #endif /* CONFIG_RAMBOOT_PBL */
  92
  93 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  94 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  95 /* Set 1M boot space */
  96 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  97 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  98                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  99 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 100 #endif
 101
 102 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 103 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 104 #endif
 105
 106 /*
 107  * These can be toggled for performance analysis, otherwise use default.
 108  */
 109 #define CONFIG_SYS_CACHE_STASHING
 110 #define CONFIG_BTB              /* toggle branch predition */
 111 #define CONFIG_DDR_ECC
 112 #ifdef CONFIG_DDR_ECC
 113 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 114 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 115 #endif
 116
 117 #ifndef __ASSEMBLY__
 118 unsigned long get_board_sys_clk(void);
 119 unsigned long get_board_ddr_clk(void);
 120 #endif
 121
 122 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
 123 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 124
 125 /*
 126  * Config the L3 Cache as L3 SRAM
 127  */
 128 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 129 #define CONFIG_SYS_L3_SIZE              (512 << 10)
 130 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 131 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
 132 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 133 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
 134 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 135
 136 #define CONFIG_SYS_DCSRBAR      0xf0000000
 137 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
 138
 139 /* EEPROM */
 140 #define CONFIG_ID_EEPROM
 141 #define CONFIG_SYS_I2C_EEPROM_NXID
 142 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 143 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 144 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 145
 146 /*
 147  * DDR Setup
 148  */
 149 #define CONFIG_VERY_BIG_RAM
 150 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 151 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 152 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
 153 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 154 #define CONFIG_DDR_SPD
 155 #define CONFIG_SYS_SPD_BUS_NUM  0
 156 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 157 #define SPD_EEPROM_ADDRESS1     0x51
 158 #define SPD_EEPROM_ADDRESS2     0x52
 159 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 160 #define CTRL_INTLV_PREFERED     cacheline
 161
 162 /*
 163  * IFC Definitions
 164  */
 165 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 166 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 167 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 168 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 169                                 + 0x8000000) | \
 170                                 CSPR_PORT_SIZE_16 | \
 171                                 CSPR_MSEL_NOR | \
 172                                 CSPR_V)
 173 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 174 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 175                                 CSPR_PORT_SIZE_16 | \
 176                                 CSPR_MSEL_NOR | \
 177                                 CSPR_V)
 178 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 179 /* NOR Flash Timing Params */
 180 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 181
 182 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 183                                 FTIM0_NOR_TEADC(0x5) | \
 184                                 FTIM0_NOR_TEAHC(0x5))
 185 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 186                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 187                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 188 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 189                                 FTIM2_NOR_TCH(0x4) | \
 190                                 FTIM2_NOR_TWPH(0x0E) | \
 191                                 FTIM2_NOR_TWP(0x1c))
 192 #define CONFIG_SYS_NOR_FTIM3    0x0
 193
 194 #define CONFIG_SYS_FLASH_QUIET_TEST
 195 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 196
 197 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 198 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 199 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 200 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 201
 202 #define CONFIG_SYS_FLASH_EMPTY_INFO
 203 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 204                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 205
 206 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 207 #define QIXIS_BASE                      0xffdf0000
 208 #define QIXIS_LBMAP_SWITCH              6
 209 #define QIXIS_LBMAP_MASK                0x0f
 210 #define QIXIS_LBMAP_SHIFT               0
 211 #define QIXIS_LBMAP_DFLTBANK            0x00
 212 #define QIXIS_LBMAP_ALTBANK             0x04
 213 #define QIXIS_LBMAP_NAND                0x09
 214 #define QIXIS_LBMAP_SD                  0x00
 215 #define QIXIS_RCW_SRC_NAND              0x104
 216 #define QIXIS_RCW_SRC_SD                0x040
 217 #define QIXIS_RST_CTL_RESET             0x83
 218 #define QIXIS_RST_FORCE_MEM             0x1
 219 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 220 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 221 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 222 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 223
 224 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 225 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 226                                 | CSPR_PORT_SIZE_8 \
 227                                 | CSPR_MSEL_GPCM \
 228                                 | CSPR_V)
 229 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 230 #define CONFIG_SYS_CSOR3        0x0
 231 /* QIXIS Timing parameters for IFC CS3 */
 232 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 233                                         FTIM0_GPCM_TEADC(0x0e) | \
 234                                         FTIM0_GPCM_TEAHC(0x0e))
 235 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 236                                         FTIM1_GPCM_TRAD(0x3f))
 237 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 238                                         FTIM2_GPCM_TCH(0x8) | \
 239                                         FTIM2_GPCM_TWP(0x1f))
 240 #define CONFIG_SYS_CS3_FTIM3            0x0
 241
 242 /* NAND Flash on IFC */
 243 #define CONFIG_NAND_FSL_IFC
 244 #define CONFIG_SYS_NAND_BASE            0xff800000
 245 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 246
 247 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 248 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 249                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 250                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 251                                 | CSPR_V)
 252 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 253
 254 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 255                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 256                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 257                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 258                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 259                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 260                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 261
 262 #define CONFIG_SYS_NAND_ONFI_DETECTION
 263
 264 /* ONFI NAND Flash mode0 Timing Params */
 265 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 266                                         FTIM0_NAND_TWP(0x18)    | \
 267                                         FTIM0_NAND_TWCHT(0x07)  | \
 268                                         FTIM0_NAND_TWH(0x0a))
 269 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 270                                         FTIM1_NAND_TWBE(0x39)   | \
 271                                         FTIM1_NAND_TRR(0x0e)    | \
 272                                         FTIM1_NAND_TRP(0x18))
 273 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 274                                         FTIM2_NAND_TREH(0x0a)   | \
 275                                         FTIM2_NAND_TWHRE(0x1e))
 276 #define CONFIG_SYS_NAND_FTIM3           0x0
 277
 278 #define CONFIG_SYS_NAND_DDR_LAW         11
 279 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 280 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 281 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 282
 283 #if defined(CONFIG_MTD_RAW_NAND)
 284 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 285 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 286 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 287 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 288 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 289 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 290 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 291 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 292 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 293 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 294 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 295 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 296 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 297 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 298 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 299 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 300 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 301 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 302 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 303 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 304 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 305 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 306 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 307 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 308 #else
 309 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 310 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 311 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 312 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 313 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 314 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 315 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 316 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 317 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 318 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 319 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 320 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 321 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 322 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 323 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 324 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 325 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 326 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 327 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 328 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 329 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 330 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 331 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 332 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 333 #endif
 334
 335 #if defined(CONFIG_RAMBOOT_PBL)
 336 #define CONFIG_SYS_RAMBOOT
 337 #endif
 338
 339 #ifdef CONFIG_SPL_BUILD
 340 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 341 #else
 342 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 343 #endif
 344
 345 #define CONFIG_HWCONFIG
 346
 347 /* define to use L1 as initial stack */
 348 #define CONFIG_L1_INIT_RAM
 349 #define CONFIG_SYS_INIT_RAM_LOCK
 350 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 351 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 352 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 353 /* The assembler doesn't like typecast */
 354 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 355                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 356                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 357 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 358 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 359                                                 GENERATED_GBL_DATA_SIZE)
 360 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 361 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 362 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 363
 364 /*
 365  * Serial Port
 366  */
 367 #define CONFIG_SYS_NS16550_SERIAL
 368 #define CONFIG_SYS_NS16550_REG_SIZE     1
 369 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 370 #define CONFIG_SYS_BAUDRATE_TABLE       \
 371         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 372 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 373 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 374 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 375 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 376
 377 /*
 378  * I2C
 379  */
 380 #if !CONFIG_IS_ENABLED(DM_I2C)
 381 #define CONFIG_SYS_I2C
 382 #define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
 383 #define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
 384 #define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
 385 #define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
 386 #define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
 387 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
 388 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
 389 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
 390 #define CONFIG_SYS_FSL_I2C_SPEED   100000
 391 #define CONFIG_SYS_FSL_I2C2_SPEED  100000
 392 #define CONFIG_SYS_FSL_I2C3_SPEED  100000
 393 #define CONFIG_SYS_FSL_I2C4_SPEED  100000
 394 #endif
 395
 396 #define CONFIG_SYS_I2C_FSL
 397
 398 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 399 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 400 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 401 #define I2C_MUX_CH_DEFAULT      0x8
 402
 403 #define I2C_MUX_CH_VOL_MONITOR 0xa
 404
 405 /* Voltage monitor on channel 2*/
 406 #define I2C_VOL_MONITOR_ADDR           0x40
 407 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 408 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 409 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 410
 411 #define CONFIG_VID_FLS_ENV              "t208xqds_vdd_mv"
 412 #ifndef CONFIG_SPL_BUILD
 413 #define CONFIG_VID
 414 #endif
 415 #define CONFIG_VOL_MONITOR_IR36021_SET
 416 #define CONFIG_VOL_MONITOR_IR36021_READ
 417 /* The lowest and highest voltage allowed for T208xQDS */
 418 #define VDD_MV_MIN                      819
 419 #define VDD_MV_MAX                      1212
 420
 421 /*
 422  * RapidIO
 423  */
 424 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 425 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 426 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 427 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 428 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 429 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 430 /*
 431  * for slave u-boot IMAGE instored in master memory space,
 432  * PHYS must be aligned based on the SIZE
 433  */
 434 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 435 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 436 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 437 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 438 /*
 439  * for slave UCODE and ENV instored in master memory space,
 440  * PHYS must be aligned based on the SIZE
 441  */
 442 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 443 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 444 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 445
 446 /* slave core release by master*/
 447 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 448 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 449
 450 /*
 451  * SRIO_PCIE_BOOT - SLAVE
 452  */
 453 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 454 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 455 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 456                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 457 #endif
 458
 459 /*
 460  * eSPI - Enhanced SPI
 461  */
 462
 463 /*
 464  * General PCI
 465  * Memory space is mapped 1-1, but I/O space must start from 0.
 466  */
 467 #define CONFIG_PCIE1            /* PCIE controller 1 */
 468 #define CONFIG_PCIE2            /* PCIE controller 2 */
 469 #define CONFIG_PCIE3            /* PCIE controller 3 */
 470 #define CONFIG_PCIE4            /* PCIE controller 4 */
 471 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 472 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 473 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 474 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 475 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 476 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 477
 478 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 479 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 480 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 481 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 482 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 483
 484 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 485 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 486 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 487 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 488 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 489
 490 /* controller 4, Base address 203000 */
 491 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 492 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 493 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 494
 495 #ifdef CONFIG_PCI
 496 #if !defined(CONFIG_DM_PCI)
 497 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 498 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 499 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 500 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 501 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 502 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 503 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000 /* 256M */
 504 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 505 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 506 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 507 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 508 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 509 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 510 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 511 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 512 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 513 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 514 #define CONFIG_PCI_INDIRECT_BRIDGE
 515 #endif
 516 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 517 #endif
 518
 519 /* Qman/Bman */
 520 #ifndef CONFIG_NOBQFMAN
 521 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 522 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 523 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 524 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 525 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 526 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 527 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 528 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 529 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 530                                         CONFIG_SYS_BMAN_CENA_SIZE)
 531 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 532 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 533 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 534 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 535 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 536 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 537 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 538 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 539 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 540 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 541 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 542                                         CONFIG_SYS_QMAN_CENA_SIZE)
 543 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 544 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 545
 546 #define CONFIG_SYS_DPAA_FMAN
 547 #define CONFIG_SYS_DPAA_PME
 548 #define CONFIG_SYS_PMAN
 549 #define CONFIG_SYS_DPAA_DCE
 550 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 551 #define CONFIG_SYS_INTERLAKEN
 552
 553 /* Default address of microcode for the Linux Fman driver */
 554 #if defined(CONFIG_SPIFLASH)
 555 /*
 556  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 557  * env, so we got 0x110000.
 558  */
 559 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 560 #elif defined(CONFIG_SDCARD)
 561 /*
 562  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 563  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 564  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 565  */
 566 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 567 #elif defined(CONFIG_MTD_RAW_NAND)
 568 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 569 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 570 /*
 571  * Slave has no ucode locally, it can fetch this from remote. When implementing
 572  * in two corenet boards, slave's ucode could be stored in master's memory
 573  * space, the address can be mapped from slave TLB->slave LAW->
 574  * slave SRIO or PCIE outbound window->master inbound window->
 575  * master LAW->the ucode address in master's memory space.
 576  */
 577 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 578 #else
 579 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
 580 #endif
 581 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 582 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 583 #endif /* CONFIG_NOBQFMAN */
 584
 585 #ifdef CONFIG_SYS_DPAA_FMAN
 586 #define RGMII_PHY1_ADDR 0x1
 587 #define RGMII_PHY2_ADDR 0x2
 588 #define FM1_10GEC1_PHY_ADDR       0x3
 589 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 590 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 591 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 592 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 593 #endif
 594
 595 #ifdef CONFIG_FMAN_ENET
 596 #define CONFIG_ETHPRIME         "FM1@DTSEC3"
 597 #endif
 598
 599 /*
 600  * SATA
 601  */
 602 #ifdef CONFIG_FSL_SATA_V2
 603 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 604 #define CONFIG_SATA1
 605 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 606 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 607 #define CONFIG_SATA2
 608 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 609 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 610 #define CONFIG_LBA48
 611 #endif
 612
 613 /*
 614  * USB
 615  */
 616 #ifdef CONFIG_USB_EHCI_HCD
 617 #define CONFIG_USB_EHCI_FSL
 618 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 619 #define CONFIG_HAS_FSL_DR_USB
 620 #endif
 621
 622 /*
 623  * SDHC
 624  */
 625 #ifdef CONFIG_MMC
 626 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 627 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 628 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 629 #endif
 630
 631 /*
 632  * Dynamic MTD Partition support with mtdparts
 633  */
 634
 635 /*
 636  * Environment
 637  */
 638 #define CONFIG_LOADS_ECHO       /* echo on for serial download */
 639 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 640
 641 /*
 642  * Miscellaneous configurable options
 643  */
 644 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
 645
 646 /*
 647  * For booting Linux, the board info and command line data
 648  * have to be in the first 64 MB of memory, since this is
 649  * the maximum mapped by the Linux kernel during initialization.
 650  */
 651 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 652 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 653
 654 #ifdef CONFIG_CMD_KGDB
 655 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 656 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 657 #endif
 658
 659 /*
 660  * Environment Configuration
 661  */
 662 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 663 #define CONFIG_BOOTFILE  "uImage"
 664 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 665
 666 /* default location for tftp and bootm */
 667 #define CONFIG_LOADADDR         1000000
 668 #define __USB_PHY_TYPE          utmi
 669
 670 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 671         "hwconfig=fsl_ddr:"                                     \
 672         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 673         "bank_intlv=auto;"                                      \
 674         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 675         "netdev=eth0\0"                                         \
 676         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 677         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 678         "tftpflash=tftpboot $loadaddr $uboot && "               \
 679         "protect off $ubootaddr +$filesize && "                 \
 680         "erase $ubootaddr +$filesize && "                       \
 681         "cp.b $loadaddr $ubootaddr $filesize && "               \
 682         "protect on $ubootaddr +$filesize && "                  \
 683         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 684         "consoledev=ttyS0\0"                                    \
 685         "ramdiskaddr=2000000\0"                                 \
 686         "ramdiskfile=t2080qds/ramdisk.uboot\0"                  \
 687         "fdtaddr=1e00000\0"                                     \
 688         "fdtfile=t2080qds/t2080qds.dtb\0"                       \
 689         "bdev=sda3\0"
 690
 691 /*
 692  * For emulation this causes u-boot to jump to the start of the
 693  * proof point app code automatically
 694  */
 695 #define CONFIG_PROOF_POINTS                             \
 696         "setenv bootargs root=/dev/$bdev rw "           \
 697         "console=$consoledev,$baudrate $othbootargs;"   \
 698         "cpu 1 release 0x29000000 - - -;"               \
 699         "cpu 2 release 0x29000000 - - -;"               \
 700         "cpu 3 release 0x29000000 - - -;"               \
 701         "cpu 4 release 0x29000000 - - -;"               \
 702         "cpu 5 release 0x29000000 - - -;"               \
 703         "cpu 6 release 0x29000000 - - -;"               \
 704         "cpu 7 release 0x29000000 - - -;"               \
 705         "go 0x29000000"
 706
 707 #define CONFIG_HVBOOT                           \
 708         "setenv bootargs config-addr=0x60000000; "      \
 709         "bootm 0x01000000 - 0x00f00000"
 710
 711 #define CONFIG_ALU                              \
 712         "setenv bootargs root=/dev/$bdev rw "           \
 713         "console=$consoledev,$baudrate $othbootargs;"   \
 714         "cpu 1 release 0x01000000 - - -;"               \
 715         "cpu 2 release 0x01000000 - - -;"               \
 716         "cpu 3 release 0x01000000 - - -;"               \
 717         "cpu 4 release 0x01000000 - - -;"               \
 718         "cpu 5 release 0x01000000 - - -;"               \
 719         "cpu 6 release 0x01000000 - - -;"               \
 720         "cpu 7 release 0x01000000 - - -;"               \
 721         "go 0x01000000"
 722
 723 #define CONFIG_LINUX                            \
 724         "setenv bootargs root=/dev/ram rw "             \
 725         "console=$consoledev,$baudrate $othbootargs;"   \
 726         "setenv ramdiskaddr 0x02000000;"                \
 727         "setenv fdtaddr 0x00c00000;"                    \
 728         "setenv loadaddr 0x1000000;"                    \
 729         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 730
 731 #define CONFIG_HDBOOT                                   \
 732         "setenv bootargs root=/dev/$bdev rw "           \
 733         "console=$consoledev,$baudrate $othbootargs;"   \
 734         "tftp $loadaddr $bootfile;"                     \
 735         "tftp $fdtaddr $fdtfile;"                       \
 736         "bootm $loadaddr - $fdtaddr"
 737
 738 #define CONFIG_NFSBOOTCOMMAND                   \
 739         "setenv bootargs root=/dev/nfs rw "     \
 740         "nfsroot=$serverip:$rootpath "          \
 741         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 742         "console=$consoledev,$baudrate $othbootargs;"   \
 743         "tftp $loadaddr $bootfile;"             \
 744         "tftp $fdtaddr $fdtfile;"               \
 745         "bootm $loadaddr - $fdtaddr"
 746
 747 #define CONFIG_RAMBOOTCOMMAND                           \
 748         "setenv bootargs root=/dev/ram rw "             \
 749         "console=$consoledev,$baudrate $othbootargs;"   \
 750         "tftp $ramdiskaddr $ramdiskfile;"               \
 751         "tftp $loadaddr $bootfile;"                     \
 752         "tftp $fdtaddr $fdtfile;"                       \
 753         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 754
 755 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 756
 757 #include <asm/fsl_secure_boot.h>
 758
 759 #endif  /* __T208xQDS_H */