1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2011-2013 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
8 * T2080/T2081 QDS board configuration file
14 #include <linux/stringify.h>
16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
17 #if defined(CONFIG_ARCH_T2080)
18 #define CONFIG_FSL_SATA_V2
19 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
20 #define CONFIG_SRIO1 /* SRIO port 1 */
21 #define CONFIG_SRIO2 /* SRIO port 2 */
24 /* High Level Configuration Options */
25 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
26 #define CONFIG_ENABLE_36BIT_PHYS
28 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
29 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
31 #ifdef CONFIG_RAMBOOT_PBL
32 #define CONFIG_SPL_FLUSH_IMAGE
33 #define CONFIG_SPL_PAD_TO 0x40000
34 #define CONFIG_SPL_MAX_SIZE 0x28000
35 #define RESET_VECTOR_OFFSET 0x27FFC
36 #define BOOT_PAGE_OFFSET 0x27000
37 #ifdef CONFIG_SPL_BUILD
38 #define CONFIG_SPL_SKIP_RELOCATE
39 #define CONFIG_SPL_COMMON_INIT_DDR
40 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
43 #ifdef CONFIG_MTD_RAW_NAND
44 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
45 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
46 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
47 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
50 #ifdef CONFIG_SPIFLASH
51 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
52 #define CONFIG_SPL_SPI_FLASH_MINIMAL
53 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
54 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
55 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
56 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
57 #ifndef CONFIG_SPL_BUILD
58 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
63 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
64 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
65 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
66 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
67 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
68 #ifndef CONFIG_SPL_BUILD
69 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
73 #endif /* CONFIG_RAMBOOT_PBL */
75 #define CONFIG_SRIO_PCIE_BOOT_MASTER
76 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
77 /* Set 1M boot space */
78 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
79 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
80 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
81 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
84 #ifndef CONFIG_RESET_VECTOR_ADDRESS
85 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
89 * These can be toggled for performance analysis, otherwise use default.
91 #define CONFIG_SYS_CACHE_STASHING
92 #define CONFIG_BTB /* toggle branch predition */
94 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
98 unsigned long get_board_sys_clk(void);
101 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
104 * Config the L3 Cache as L3 SRAM
106 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
107 #define CONFIG_SYS_L3_SIZE (512 << 10)
108 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
109 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
110 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
111 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
112 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
114 #define CONFIG_SYS_DCSRBAR 0xf0000000
115 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
118 #define CONFIG_SYS_I2C_EEPROM_NXID
119 #define CONFIG_SYS_EEPROM_BUS_NUM 0
124 #define CONFIG_VERY_BIG_RAM
125 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
126 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
127 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
128 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
129 #define CONFIG_SYS_SPD_BUS_NUM 0
130 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
131 #define SPD_EEPROM_ADDRESS1 0x51
132 #define SPD_EEPROM_ADDRESS2 0x52
133 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
134 #define CTRL_INTLV_PREFERED cacheline
139 #define CONFIG_SYS_FLASH_BASE 0xe0000000
140 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
141 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
142 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
144 CSPR_PORT_SIZE_16 | \
147 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
148 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
149 CSPR_PORT_SIZE_16 | \
152 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
153 /* NOR Flash Timing Params */
154 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
156 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
157 FTIM0_NOR_TEADC(0x5) | \
158 FTIM0_NOR_TEAHC(0x5))
159 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
160 FTIM1_NOR_TRAD_NOR(0x1A) |\
161 FTIM1_NOR_TSEQRAD_NOR(0x13))
162 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
163 FTIM2_NOR_TCH(0x4) | \
164 FTIM2_NOR_TWPH(0x0E) | \
166 #define CONFIG_SYS_NOR_FTIM3 0x0
168 #define CONFIG_SYS_FLASH_QUIET_TEST
169 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
171 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
172 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
173 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
174 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
176 #define CONFIG_SYS_FLASH_EMPTY_INFO
177 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
178 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
180 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
181 #define QIXIS_BASE 0xffdf0000
182 #define QIXIS_LBMAP_SWITCH 6
183 #define QIXIS_LBMAP_MASK 0x0f
184 #define QIXIS_LBMAP_SHIFT 0
185 #define QIXIS_LBMAP_DFLTBANK 0x00
186 #define QIXIS_LBMAP_ALTBANK 0x04
187 #define QIXIS_LBMAP_NAND 0x09
188 #define QIXIS_LBMAP_SD 0x00
189 #define QIXIS_RCW_SRC_NAND 0x104
190 #define QIXIS_RCW_SRC_SD 0x040
191 #define QIXIS_RST_CTL_RESET 0x83
192 #define QIXIS_RST_FORCE_MEM 0x1
193 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
194 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
195 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
196 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
198 #define CONFIG_SYS_CSPR3_EXT (0xf)
199 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
203 #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
204 #define CONFIG_SYS_CSOR3 0x0
205 /* QIXIS Timing parameters for IFC CS3 */
206 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
207 FTIM0_GPCM_TEADC(0x0e) | \
208 FTIM0_GPCM_TEAHC(0x0e))
209 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
210 FTIM1_GPCM_TRAD(0x3f))
211 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
212 FTIM2_GPCM_TCH(0x8) | \
213 FTIM2_GPCM_TWP(0x1f))
214 #define CONFIG_SYS_CS3_FTIM3 0x0
216 /* NAND Flash on IFC */
217 #define CONFIG_SYS_NAND_BASE 0xff800000
218 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
220 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
221 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
222 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
223 | CSPR_MSEL_NAND /* MSEL = NAND */ \
225 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
227 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
228 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
229 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
230 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
231 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
232 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
233 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
235 /* ONFI NAND Flash mode0 Timing Params */
236 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
237 FTIM0_NAND_TWP(0x18) | \
238 FTIM0_NAND_TWCHT(0x07) | \
239 FTIM0_NAND_TWH(0x0a))
240 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
241 FTIM1_NAND_TWBE(0x39) | \
242 FTIM1_NAND_TRR(0x0e) | \
243 FTIM1_NAND_TRP(0x18))
244 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
245 FTIM2_NAND_TREH(0x0a) | \
246 FTIM2_NAND_TWHRE(0x1e))
247 #define CONFIG_SYS_NAND_FTIM3 0x0
249 #define CONFIG_SYS_NAND_DDR_LAW 11
250 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
251 #define CONFIG_SYS_MAX_NAND_DEVICE 1
253 #if defined(CONFIG_MTD_RAW_NAND)
254 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
255 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
256 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
257 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
258 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
259 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
260 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
261 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
262 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
263 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
264 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
265 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
266 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
267 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
268 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
269 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
270 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
271 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
272 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
273 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
274 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
275 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
276 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
277 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
279 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
280 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
281 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
282 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
283 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
284 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
285 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
286 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
287 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
288 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
289 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
290 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
291 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
292 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
293 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
294 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
295 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
296 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
297 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
298 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
299 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
300 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
301 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
302 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
305 #if defined(CONFIG_RAMBOOT_PBL)
306 #define CONFIG_SYS_RAMBOOT
309 #ifdef CONFIG_SPL_BUILD
310 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
312 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
315 #define CONFIG_HWCONFIG
317 /* define to use L1 as initial stack */
318 #define CONFIG_L1_INIT_RAM
319 #define CONFIG_SYS_INIT_RAM_LOCK
320 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
321 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
322 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
323 /* The assembler doesn't like typecast */
324 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
325 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
326 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
327 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
328 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
329 GENERATED_GBL_DATA_SIZE)
330 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
331 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
336 #define CONFIG_SYS_NS16550_SERIAL
337 #define CONFIG_SYS_NS16550_REG_SIZE 1
338 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
339 #define CONFIG_SYS_BAUDRATE_TABLE \
340 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
341 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
342 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
343 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
344 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
350 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
351 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
352 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
353 #define I2C_MUX_CH_DEFAULT 0x8
355 #define I2C_MUX_CH_VOL_MONITOR 0xa
357 /* Voltage monitor on channel 2*/
358 #define I2C_VOL_MONITOR_ADDR 0x40
359 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
360 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
361 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
363 #define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv"
364 #ifndef CONFIG_SPL_BUILD
367 #define CONFIG_VOL_MONITOR_IR36021_SET
368 #define CONFIG_VOL_MONITOR_IR36021_READ
369 /* The lowest and highest voltage allowed for T208xQDS */
370 #define VDD_MV_MIN 819
371 #define VDD_MV_MAX 1212
376 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
377 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
378 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
379 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
380 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
381 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
383 * for slave u-boot IMAGE instored in master memory space,
384 * PHYS must be aligned based on the SIZE
386 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
387 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
388 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
389 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
391 * for slave UCODE and ENV instored in master memory space,
392 * PHYS must be aligned based on the SIZE
394 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
395 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
396 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
398 /* slave core release by master*/
399 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
400 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
403 * SRIO_PCIE_BOOT - SLAVE
405 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
406 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
407 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
408 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
412 * eSPI - Enhanced SPI
417 * Memory space is mapped 1-1, but I/O space must start from 0.
419 #define CONFIG_PCIE1 /* PCIE controller 1 */
420 #define CONFIG_PCIE2 /* PCIE controller 2 */
421 #define CONFIG_PCIE3 /* PCIE controller 3 */
422 #define CONFIG_PCIE4 /* PCIE controller 4 */
423 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
424 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
425 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
426 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
427 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
428 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
430 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
431 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
432 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
433 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
434 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
436 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
437 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
438 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
439 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
440 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
442 /* controller 4, Base address 203000 */
443 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
444 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
445 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
448 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
452 #ifndef CONFIG_NOBQFMAN
453 #define CONFIG_SYS_BMAN_NUM_PORTALS 18
454 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
455 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
456 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
457 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
458 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
459 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
460 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
461 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
462 CONFIG_SYS_BMAN_CENA_SIZE)
463 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
464 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
465 #define CONFIG_SYS_QMAN_NUM_PORTALS 18
466 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
467 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
468 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
469 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
470 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
471 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
472 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
473 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
474 CONFIG_SYS_QMAN_CENA_SIZE)
475 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
476 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
478 #define CONFIG_SYS_DPAA_FMAN
479 #define CONFIG_SYS_DPAA_PME
480 #define CONFIG_SYS_PMAN
481 #define CONFIG_SYS_DPAA_DCE
482 #define CONFIG_SYS_DPAA_RMAN /* RMan */
483 #define CONFIG_SYS_INTERLAKEN
485 /* Default address of microcode for the Linux Fman driver */
486 #if defined(CONFIG_SPIFLASH)
488 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
489 * env, so we got 0x110000.
491 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
492 #elif defined(CONFIG_SDCARD)
494 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
495 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
496 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
498 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
499 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
501 * Slave has no ucode locally, it can fetch this from remote. When implementing
502 * in two corenet boards, slave's ucode could be stored in master's memory
503 * space, the address can be mapped from slave TLB->slave LAW->
504 * slave SRIO or PCIE outbound window->master inbound window->
505 * master LAW->the ucode address in master's memory space.
507 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
509 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
511 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
512 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
513 #endif /* CONFIG_NOBQFMAN */
515 #ifdef CONFIG_SYS_DPAA_FMAN
516 #define RGMII_PHY1_ADDR 0x1
517 #define RGMII_PHY2_ADDR 0x2
518 #define FM1_10GEC1_PHY_ADDR 0x3
519 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
520 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
521 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
522 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
525 #ifdef CONFIG_FMAN_ENET
526 #define CONFIG_ETHPRIME "FM1@DTSEC3"
532 #ifdef CONFIG_FSL_SATA_V2
533 #define CONFIG_SYS_SATA_MAX_DEVICE 2
535 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
536 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
538 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
539 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
546 #ifdef CONFIG_USB_EHCI_HCD
547 #define CONFIG_USB_EHCI_FSL
548 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
549 #define CONFIG_HAS_FSL_DR_USB
556 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
557 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
561 * Dynamic MTD Partition support with mtdparts
567 #define CONFIG_LOADS_ECHO /* echo on for serial download */
568 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
571 * Miscellaneous configurable options
575 * For booting Linux, the board info and command line data
576 * have to be in the first 64 MB of memory, since this is
577 * the maximum mapped by the Linux kernel during initialization.
579 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
580 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
583 * Environment Configuration
585 #define CONFIG_ROOTPATH "/opt/nfsroot"
586 #define CONFIG_BOOTFILE "uImage"
587 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
589 #define __USB_PHY_TYPE utmi
591 #define CONFIG_EXTRA_ENV_SETTINGS \
592 "hwconfig=fsl_ddr:" \
593 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
595 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
597 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
598 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
599 "tftpflash=tftpboot $loadaddr $uboot && " \
600 "protect off $ubootaddr +$filesize && " \
601 "erase $ubootaddr +$filesize && " \
602 "cp.b $loadaddr $ubootaddr $filesize && " \
603 "protect on $ubootaddr +$filesize && " \
604 "cmp.b $loadaddr $ubootaddr $filesize\0" \
605 "consoledev=ttyS0\0" \
606 "ramdiskaddr=2000000\0" \
607 "ramdiskfile=t2080qds/ramdisk.uboot\0" \
608 "fdtaddr=1e00000\0" \
609 "fdtfile=t2080qds/t2080qds.dtb\0" \
613 * For emulation this causes u-boot to jump to the start of the
614 * proof point app code automatically
616 #define PROOF_POINTS \
617 "setenv bootargs root=/dev/$bdev rw " \
618 "console=$consoledev,$baudrate $othbootargs;" \
619 "cpu 1 release 0x29000000 - - -;" \
620 "cpu 2 release 0x29000000 - - -;" \
621 "cpu 3 release 0x29000000 - - -;" \
622 "cpu 4 release 0x29000000 - - -;" \
623 "cpu 5 release 0x29000000 - - -;" \
624 "cpu 6 release 0x29000000 - - -;" \
625 "cpu 7 release 0x29000000 - - -;" \
629 "setenv bootargs config-addr=0x60000000; " \
630 "bootm 0x01000000 - 0x00f00000"
633 "setenv bootargs root=/dev/$bdev rw " \
634 "console=$consoledev,$baudrate $othbootargs;" \
635 "cpu 1 release 0x01000000 - - -;" \
636 "cpu 2 release 0x01000000 - - -;" \
637 "cpu 3 release 0x01000000 - - -;" \
638 "cpu 4 release 0x01000000 - - -;" \
639 "cpu 5 release 0x01000000 - - -;" \
640 "cpu 6 release 0x01000000 - - -;" \
641 "cpu 7 release 0x01000000 - - -;" \
644 #define LINUXBOOTCOMMAND \
645 "setenv bootargs root=/dev/ram rw " \
646 "console=$consoledev,$baudrate $othbootargs;" \
647 "setenv ramdiskaddr 0x02000000;" \
648 "setenv fdtaddr 0x00c00000;" \
649 "setenv loadaddr 0x1000000;" \
650 "bootm $loadaddr $ramdiskaddr $fdtaddr"
653 "setenv bootargs root=/dev/$bdev rw " \
654 "console=$consoledev,$baudrate $othbootargs;" \
655 "tftp $loadaddr $bootfile;" \
656 "tftp $fdtaddr $fdtfile;" \
657 "bootm $loadaddr - $fdtaddr"
659 #define NFSBOOTCOMMAND \
660 "setenv bootargs root=/dev/nfs rw " \
661 "nfsroot=$serverip:$rootpath " \
662 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
663 "console=$consoledev,$baudrate $othbootargs;" \
664 "tftp $loadaddr $bootfile;" \
665 "tftp $fdtaddr $fdtfile;" \
666 "bootm $loadaddr - $fdtaddr"
668 #define RAMBOOTCOMMAND \
669 "setenv bootargs root=/dev/ram rw " \
670 "console=$consoledev,$baudrate $othbootargs;" \
671 "tftp $ramdiskaddr $ramdiskfile;" \
672 "tftp $loadaddr $bootfile;" \
673 "tftp $fdtaddr $fdtfile;" \
674 "bootm $loadaddr $ramdiskaddr $fdtaddr"
676 #define CONFIG_BOOTCOMMAND LINUXBOOTCOMMAND
678 #include <asm/fsl_secure_boot.h>
680 #endif /* __T208xQDS_H */