include/configs/T208xQDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2013 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T2080/T2081 QDS board configuration file
   9  */
  10
  11 #ifndef __T208xQDS_H
  12 #define __T208xQDS_H
  13
  14 #include <linux/stringify.h>
  15
  16 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  17 #if defined(CONFIG_ARCH_T2080)
  18 #define CONFIG_FSL_SATA_V2
  19 #define CONFIG_SYS_SRIO         /* Enable Serial RapidIO Support */
  20 #define CONFIG_SRIO1            /* SRIO port 1 */
  21 #define CONFIG_SRIO2            /* SRIO port 2 */
  22 #endif
  23
  24 /* High Level Configuration Options */
  25 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
  26 #define CONFIG_ENABLE_36BIT_PHYS
  27
  28 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  29 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  30
  31 #ifdef CONFIG_RAMBOOT_PBL
  32 #define CONFIG_SPL_FLUSH_IMAGE
  33 #define CONFIG_SPL_PAD_TO               0x40000
  34 #define CONFIG_SPL_MAX_SIZE             0x28000
  35 #define RESET_VECTOR_OFFSET             0x27FFC
  36 #define BOOT_PAGE_OFFSET                0x27000
  37 #ifdef CONFIG_SPL_BUILD
  38 #define CONFIG_SPL_SKIP_RELOCATE
  39 #define CONFIG_SPL_COMMON_INIT_DDR
  40 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  41 #endif
  42
  43 #ifdef CONFIG_MTD_RAW_NAND
  44 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  45 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  46 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  47 #endif
  48
  49 #ifdef CONFIG_SPIFLASH
  50 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  51 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  52 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  53 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
  54 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
  55 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  56 #ifndef CONFIG_SPL_BUILD
  57 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  58 #endif
  59 #endif
  60
  61 #ifdef CONFIG_SDCARD
  62 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  63 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  64 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
  65 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
  66 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  67 #ifndef CONFIG_SPL_BUILD
  68 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  69 #endif
  70 #endif
  71
  72 #endif /* CONFIG_RAMBOOT_PBL */
  73
  74 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  75 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  76 /* Set 1M boot space */
  77 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  78 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  79                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  80 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  81 #endif
  82
  83 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  84 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  85 #endif
  86
  87 /*
  88  * These can be toggled for performance analysis, otherwise use default.
  89  */
  90 #define CONFIG_SYS_CACHE_STASHING
  91 #ifdef CONFIG_DDR_ECC
  92 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  93 #endif
  94
  95 /*
  96  * Config the L3 Cache as L3 SRAM
  97  */
  98 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
  99 #define CONFIG_SYS_L3_SIZE              (512 << 10)
 100 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 101 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
 102 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 103 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
 104 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 105
 106 #define CONFIG_SYS_DCSRBAR      0xf0000000
 107 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
 108
 109 /* EEPROM */
 110 #define CONFIG_SYS_I2C_EEPROM_NXID
 111 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 112
 113 /*
 114  * DDR Setup
 115  */
 116 #define CONFIG_VERY_BIG_RAM
 117 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 118 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 119 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
 120 #define CONFIG_SYS_SPD_BUS_NUM  0
 121 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 122 #define SPD_EEPROM_ADDRESS1     0x51
 123 #define SPD_EEPROM_ADDRESS2     0x52
 124 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 125 #define CTRL_INTLV_PREFERED     cacheline
 126
 127 /*
 128  * IFC Definitions
 129  */
 130 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 131 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 132 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 133 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 134                                 + 0x8000000) | \
 135                                 CSPR_PORT_SIZE_16 | \
 136                                 CSPR_MSEL_NOR | \
 137                                 CSPR_V)
 138 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 139 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 140                                 CSPR_PORT_SIZE_16 | \
 141                                 CSPR_MSEL_NOR | \
 142                                 CSPR_V)
 143 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 144 /* NOR Flash Timing Params */
 145 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 146
 147 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 148                                 FTIM0_NOR_TEADC(0x5) | \
 149                                 FTIM0_NOR_TEAHC(0x5))
 150 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 151                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 152                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 153 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 154                                 FTIM2_NOR_TCH(0x4) | \
 155                                 FTIM2_NOR_TWPH(0x0E) | \
 156                                 FTIM2_NOR_TWP(0x1c))
 157 #define CONFIG_SYS_NOR_FTIM3    0x0
 158
 159 #define CONFIG_SYS_FLASH_QUIET_TEST
 160 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 161
 162 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 163 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 164 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 165
 166 #define CONFIG_SYS_FLASH_EMPTY_INFO
 167 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 168                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 169
 170 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 171 #define QIXIS_BASE                      0xffdf0000
 172 #define QIXIS_LBMAP_SWITCH              6
 173 #define QIXIS_LBMAP_MASK                0x0f
 174 #define QIXIS_LBMAP_SHIFT               0
 175 #define QIXIS_LBMAP_DFLTBANK            0x00
 176 #define QIXIS_LBMAP_ALTBANK             0x04
 177 #define QIXIS_LBMAP_NAND                0x09
 178 #define QIXIS_LBMAP_SD                  0x00
 179 #define QIXIS_RCW_SRC_NAND              0x104
 180 #define QIXIS_RCW_SRC_SD                0x040
 181 #define QIXIS_RST_CTL_RESET             0x83
 182 #define QIXIS_RST_FORCE_MEM             0x1
 183 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 184 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 185 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 186 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 187
 188 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 189 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 190                                 | CSPR_PORT_SIZE_8 \
 191                                 | CSPR_MSEL_GPCM \
 192                                 | CSPR_V)
 193 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 194 #define CONFIG_SYS_CSOR3        0x0
 195 /* QIXIS Timing parameters for IFC CS3 */
 196 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 197                                         FTIM0_GPCM_TEADC(0x0e) | \
 198                                         FTIM0_GPCM_TEAHC(0x0e))
 199 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 200                                         FTIM1_GPCM_TRAD(0x3f))
 201 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 202                                         FTIM2_GPCM_TCH(0x8) | \
 203                                         FTIM2_GPCM_TWP(0x1f))
 204 #define CONFIG_SYS_CS3_FTIM3            0x0
 205
 206 /* NAND Flash on IFC */
 207 #define CONFIG_SYS_NAND_BASE            0xff800000
 208 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 209
 210 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 211 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 212                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 213                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 214                                 | CSPR_V)
 215 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 216
 217 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 218                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 219                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 220                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 221                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 222                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 223                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 224
 225 /* ONFI NAND Flash mode0 Timing Params */
 226 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 227                                         FTIM0_NAND_TWP(0x18)    | \
 228                                         FTIM0_NAND_TWCHT(0x07)  | \
 229                                         FTIM0_NAND_TWH(0x0a))
 230 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 231                                         FTIM1_NAND_TWBE(0x39)   | \
 232                                         FTIM1_NAND_TRR(0x0e)    | \
 233                                         FTIM1_NAND_TRP(0x18))
 234 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 235                                         FTIM2_NAND_TREH(0x0a)   | \
 236                                         FTIM2_NAND_TWHRE(0x1e))
 237 #define CONFIG_SYS_NAND_FTIM3           0x0
 238
 239 #define CONFIG_SYS_NAND_DDR_LAW         11
 240 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 241 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 242
 243 #if defined(CONFIG_MTD_RAW_NAND)
 244 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 245 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 246 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 247 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 248 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 249 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 250 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 251 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 252 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 253 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 254 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 255 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 256 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 257 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 258 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 259 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 260 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 261 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 262 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 263 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 264 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 265 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 266 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 267 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 268 #else
 269 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 270 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 271 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 272 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 273 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 274 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 275 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 276 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 277 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 278 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 279 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 280 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 281 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 282 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 283 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 284 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 285 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 286 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 287 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 288 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 289 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 290 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 291 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 292 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 293 #endif
 294
 295 #if defined(CONFIG_RAMBOOT_PBL)
 296 #define CONFIG_SYS_RAMBOOT
 297 #endif
 298
 299 #ifdef CONFIG_SPL_BUILD
 300 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 301 #else
 302 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 303 #endif
 304
 305 #define CONFIG_HWCONFIG
 306
 307 /* define to use L1 as initial stack */
 308 #define CONFIG_L1_INIT_RAM
 309 #define CONFIG_SYS_INIT_RAM_LOCK
 310 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 311 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 312 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 313 /* The assembler doesn't like typecast */
 314 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 315                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 316                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 317 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 318 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 319                                                 GENERATED_GBL_DATA_SIZE)
 320 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 321 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 322
 323 /*
 324  * Serial Port
 325  */
 326 #define CONFIG_SYS_NS16550_SERIAL
 327 #define CONFIG_SYS_NS16550_REG_SIZE     1
 328 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 329 #define CONFIG_SYS_BAUDRATE_TABLE       \
 330         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 331 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 332 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 333 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 334 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 335
 336 /*
 337  * I2C
 338  */
 339
 340 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 341 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 342 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 343 #define I2C_MUX_CH_DEFAULT      0x8
 344
 345 #define I2C_MUX_CH_VOL_MONITOR 0xa
 346
 347 /* Voltage monitor on channel 2*/
 348 #define I2C_VOL_MONITOR_ADDR           0x40
 349 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 350 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 351 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 352
 353 /* The lowest and highest voltage allowed for T208xQDS */
 354 #define VDD_MV_MIN                      819
 355 #define VDD_MV_MAX                      1212
 356
 357 /*
 358  * RapidIO
 359  */
 360 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 361 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 362 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 363 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 364 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 365 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 366 /*
 367  * for slave u-boot IMAGE instored in master memory space,
 368  * PHYS must be aligned based on the SIZE
 369  */
 370 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 371 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 372 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 373 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 374 /*
 375  * for slave UCODE and ENV instored in master memory space,
 376  * PHYS must be aligned based on the SIZE
 377  */
 378 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 379 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 380 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 381
 382 /* slave core release by master*/
 383 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 384 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 385
 386 /*
 387  * SRIO_PCIE_BOOT - SLAVE
 388  */
 389 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 390 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 391 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 392                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 393 #endif
 394
 395 /*
 396  * eSPI - Enhanced SPI
 397  */
 398
 399 /*
 400  * General PCI
 401  * Memory space is mapped 1-1, but I/O space must start from 0.
 402  */
 403 #define CONFIG_PCIE1            /* PCIE controller 1 */
 404 #define CONFIG_PCIE2            /* PCIE controller 2 */
 405 #define CONFIG_PCIE3            /* PCIE controller 3 */
 406 #define CONFIG_PCIE4            /* PCIE controller 4 */
 407 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 408 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 409 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 410 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 411 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 412
 413 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 414 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 415 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 416 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 417 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 418
 419 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 420 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 421 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 422 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 423 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 424
 425 /* controller 4, Base address 203000 */
 426 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 427 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 428 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 429
 430 #ifdef CONFIG_PCI
 431 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 432 #endif
 433
 434 /* Qman/Bman */
 435 #ifndef CONFIG_NOBQFMAN
 436 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 437 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 438 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 439 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 440 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 441 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 442 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 443 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 444 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 445                                         CONFIG_SYS_BMAN_CENA_SIZE)
 446 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 447 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 448 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 449 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 450 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 451 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 452 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 453 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 454 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 455 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 456 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 457                                         CONFIG_SYS_QMAN_CENA_SIZE)
 458 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 459 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 460
 461 #define CONFIG_SYS_DPAA_FMAN
 462 #define CONFIG_SYS_DPAA_PME
 463 #define CONFIG_SYS_PMAN
 464 #define CONFIG_SYS_DPAA_DCE
 465 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 466 #define CONFIG_SYS_INTERLAKEN
 467
 468 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 469 #endif /* CONFIG_NOBQFMAN */
 470
 471 #ifdef CONFIG_SYS_DPAA_FMAN
 472 #define RGMII_PHY1_ADDR 0x1
 473 #define RGMII_PHY2_ADDR 0x2
 474 #define FM1_10GEC1_PHY_ADDR       0x3
 475 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 476 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 477 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 478 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 479 #endif
 480
 481 /*
 482  * SATA
 483  */
 484 #ifdef CONFIG_FSL_SATA_V2
 485 #define CONFIG_SATA1
 486 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 487 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 488 #define CONFIG_SATA2
 489 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 490 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 491 #define CONFIG_LBA48
 492 #endif
 493
 494 /*
 495  * USB
 496  */
 497 #ifdef CONFIG_USB_EHCI_HCD
 498 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 499 #define CONFIG_HAS_FSL_DR_USB
 500 #endif
 501
 502 /*
 503  * SDHC
 504  */
 505 #ifdef CONFIG_MMC
 506 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 507 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 508 #endif
 509
 510 /*
 511  * Dynamic MTD Partition support with mtdparts
 512  */
 513
 514 /*
 515  * Environment
 516  */
 517 #define CONFIG_LOADS_ECHO       /* echo on for serial download */
 518 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 519
 520 /*
 521  * Miscellaneous configurable options
 522  */
 523
 524 /*
 525  * For booting Linux, the board info and command line data
 526  * have to be in the first 64 MB of memory, since this is
 527  * the maximum mapped by the Linux kernel during initialization.
 528  */
 529 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 530 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 531
 532 /*
 533  * Environment Configuration
 534  */
 535 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 536 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 537
 538 #define __USB_PHY_TYPE          utmi
 539
 540 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 541         "hwconfig=fsl_ddr:"                                     \
 542         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 543         "bank_intlv=auto;"                                      \
 544         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 545         "netdev=eth0\0"                                         \
 546         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 547         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 548         "tftpflash=tftpboot $loadaddr $uboot && "               \
 549         "protect off $ubootaddr +$filesize && "                 \
 550         "erase $ubootaddr +$filesize && "                       \
 551         "cp.b $loadaddr $ubootaddr $filesize && "               \
 552         "protect on $ubootaddr +$filesize && "                  \
 553         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 554         "consoledev=ttyS0\0"                                    \
 555         "ramdiskaddr=2000000\0"                                 \
 556         "ramdiskfile=t2080qds/ramdisk.uboot\0"                  \
 557         "fdtaddr=1e00000\0"                                     \
 558         "fdtfile=t2080qds/t2080qds.dtb\0"                       \
 559         "bdev=sda3\0"
 560
 561 /*
 562  * For emulation this causes u-boot to jump to the start of the
 563  * proof point app code automatically
 564  */
 565 #define PROOF_POINTS                            \
 566         "setenv bootargs root=/dev/$bdev rw "           \
 567         "console=$consoledev,$baudrate $othbootargs;"   \
 568         "cpu 1 release 0x29000000 - - -;"               \
 569         "cpu 2 release 0x29000000 - - -;"               \
 570         "cpu 3 release 0x29000000 - - -;"               \
 571         "cpu 4 release 0x29000000 - - -;"               \
 572         "cpu 5 release 0x29000000 - - -;"               \
 573         "cpu 6 release 0x29000000 - - -;"               \
 574         "cpu 7 release 0x29000000 - - -;"               \
 575         "go 0x29000000"
 576
 577 #define HVBOOT                          \
 578         "setenv bootargs config-addr=0x60000000; "      \
 579         "bootm 0x01000000 - 0x00f00000"
 580
 581 #define ALU                             \
 582         "setenv bootargs root=/dev/$bdev rw "           \
 583         "console=$consoledev,$baudrate $othbootargs;"   \
 584         "cpu 1 release 0x01000000 - - -;"               \
 585         "cpu 2 release 0x01000000 - - -;"               \
 586         "cpu 3 release 0x01000000 - - -;"               \
 587         "cpu 4 release 0x01000000 - - -;"               \
 588         "cpu 5 release 0x01000000 - - -;"               \
 589         "cpu 6 release 0x01000000 - - -;"               \
 590         "cpu 7 release 0x01000000 - - -;"               \
 591         "go 0x01000000"
 592
 593 #include <asm/fsl_secure_boot.h>
 594
 595 #endif  /* __T208xQDS_H */