include/configs/T208xQDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2013 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T2080/T2081 QDS board configuration file
   9  */
  10
  11 #ifndef __T208xQDS_H
  12 #define __T208xQDS_H
  13
  14 #include <linux/stringify.h>
  15
  16 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  17 #if defined(CONFIG_ARCH_T2080)
  18 #define CONFIG_FSL_SATA_V2
  19 #define CONFIG_SYS_SRIO         /* Enable Serial RapidIO Support */
  20 #define CONFIG_SRIO1            /* SRIO port 1 */
  21 #define CONFIG_SRIO2            /* SRIO port 2 */
  22 #endif
  23
  24 /* High Level Configuration Options */
  25 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
  26 #define CONFIG_ENABLE_36BIT_PHYS
  27
  28 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  29 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  30
  31 #ifdef CONFIG_RAMBOOT_PBL
  32 #define RESET_VECTOR_OFFSET             0x27FFC
  33 #define BOOT_PAGE_OFFSET                0x27000
  34
  35 #ifdef CONFIG_MTD_RAW_NAND
  36 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  37 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  38 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  39 #ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
  40 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  41 #endif
  42 #endif
  43
  44 #ifdef CONFIG_SPIFLASH
  45 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  46 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  47 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  48 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
  49 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
  50 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  51 #ifndef CONFIG_SPL_BUILD
  52 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  53 #endif
  54 #endif
  55
  56 #ifdef CONFIG_SDCARD
  57 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  58 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  59 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
  60 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
  61 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  62 #ifndef CONFIG_SPL_BUILD
  63 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  64 #endif
  65 #endif
  66
  67 #endif /* CONFIG_RAMBOOT_PBL */
  68
  69 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  70 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  71 /* Set 1M boot space */
  72 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  73 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  74                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  75 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  76 #endif
  77
  78 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  79 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  80 #endif
  81
  82 /*
  83  * These can be toggled for performance analysis, otherwise use default.
  84  */
  85 #define CONFIG_SYS_CACHE_STASHING
  86 #ifdef CONFIG_DDR_ECC
  87 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  88 #endif
  89
  90 /*
  91  * Config the L3 Cache as L3 SRAM
  92  */
  93 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
  94 #define CONFIG_SYS_L3_SIZE              (512 << 10)
  95 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  96 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
  97 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
  98 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
  99 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 100
 101 #define CONFIG_SYS_DCSRBAR      0xf0000000
 102 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
 103
 104 /* EEPROM */
 105 #define CONFIG_SYS_I2C_EEPROM_NXID
 106 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 107
 108 /*
 109  * DDR Setup
 110  */
 111 #define CONFIG_VERY_BIG_RAM
 112 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 113 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 114 #define CONFIG_SYS_SPD_BUS_NUM  0
 115 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 116 #define SPD_EEPROM_ADDRESS1     0x51
 117 #define SPD_EEPROM_ADDRESS2     0x52
 118 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 119 #define CTRL_INTLV_PREFERED     cacheline
 120
 121 /*
 122  * IFC Definitions
 123  */
 124 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 125 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 126 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 127 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 128                                 + 0x8000000) | \
 129                                 CSPR_PORT_SIZE_16 | \
 130                                 CSPR_MSEL_NOR | \
 131                                 CSPR_V)
 132 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 133 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 134                                 CSPR_PORT_SIZE_16 | \
 135                                 CSPR_MSEL_NOR | \
 136                                 CSPR_V)
 137 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 138 /* NOR Flash Timing Params */
 139 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 140
 141 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 142                                 FTIM0_NOR_TEADC(0x5) | \
 143                                 FTIM0_NOR_TEAHC(0x5))
 144 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 145                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 146                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 147 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 148                                 FTIM2_NOR_TCH(0x4) | \
 149                                 FTIM2_NOR_TWPH(0x0E) | \
 150                                 FTIM2_NOR_TWP(0x1c))
 151 #define CONFIG_SYS_NOR_FTIM3    0x0
 152
 153 #define CONFIG_SYS_FLASH_QUIET_TEST
 154 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 155
 156 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 157 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 158 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 159
 160 #define CONFIG_SYS_FLASH_EMPTY_INFO
 161 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 162                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 163
 164 #define QIXIS_BASE                      0xffdf0000
 165 #define QIXIS_LBMAP_SWITCH              6
 166 #define QIXIS_LBMAP_MASK                0x0f
 167 #define QIXIS_LBMAP_SHIFT               0
 168 #define QIXIS_LBMAP_DFLTBANK            0x00
 169 #define QIXIS_LBMAP_ALTBANK             0x04
 170 #define QIXIS_LBMAP_NAND                0x09
 171 #define QIXIS_LBMAP_SD                  0x00
 172 #define QIXIS_RCW_SRC_NAND              0x104
 173 #define QIXIS_RCW_SRC_SD                0x040
 174 #define QIXIS_RST_CTL_RESET             0x83
 175 #define QIXIS_RST_FORCE_MEM             0x1
 176 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 177 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 178 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 179 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 180
 181 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 182 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 183                                 | CSPR_PORT_SIZE_8 \
 184                                 | CSPR_MSEL_GPCM \
 185                                 | CSPR_V)
 186 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 187 #define CONFIG_SYS_CSOR3        0x0
 188 /* QIXIS Timing parameters for IFC CS3 */
 189 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 190                                         FTIM0_GPCM_TEADC(0x0e) | \
 191                                         FTIM0_GPCM_TEAHC(0x0e))
 192 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 193                                         FTIM1_GPCM_TRAD(0x3f))
 194 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 195                                         FTIM2_GPCM_TCH(0x8) | \
 196                                         FTIM2_GPCM_TWP(0x1f))
 197 #define CONFIG_SYS_CS3_FTIM3            0x0
 198
 199 /* NAND Flash on IFC */
 200 #define CONFIG_SYS_NAND_BASE            0xff800000
 201 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 202
 203 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 204 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 205                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 206                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 207                                 | CSPR_V)
 208 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 209
 210 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 211                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 212                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 213                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 214                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 215                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 216                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 217
 218 /* ONFI NAND Flash mode0 Timing Params */
 219 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 220                                         FTIM0_NAND_TWP(0x18)    | \
 221                                         FTIM0_NAND_TWCHT(0x07)  | \
 222                                         FTIM0_NAND_TWH(0x0a))
 223 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 224                                         FTIM1_NAND_TWBE(0x39)   | \
 225                                         FTIM1_NAND_TRR(0x0e)    | \
 226                                         FTIM1_NAND_TRP(0x18))
 227 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 228                                         FTIM2_NAND_TREH(0x0a)   | \
 229                                         FTIM2_NAND_TWHRE(0x1e))
 230 #define CONFIG_SYS_NAND_FTIM3           0x0
 231
 232 #define CONFIG_SYS_NAND_DDR_LAW         11
 233 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 234 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 235
 236 #if defined(CONFIG_MTD_RAW_NAND)
 237 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 238 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 239 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 240 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 241 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 242 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 243 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 244 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 245 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 246 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 247 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 248 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 249 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 250 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 251 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 252 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 253 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 254 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 255 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 256 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 257 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 258 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 259 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 260 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 261 #else
 262 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 263 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 264 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 265 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 266 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 267 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 268 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 269 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 270 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 271 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 272 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 273 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 274 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 275 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 276 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 277 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 278 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 279 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 280 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 281 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 282 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 283 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 284 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 285 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 286 #endif
 287
 288 #if defined(CONFIG_RAMBOOT_PBL)
 289 #define CONFIG_SYS_RAMBOOT
 290 #endif
 291
 292 #define CONFIG_HWCONFIG
 293
 294 /* define to use L1 as initial stack */
 295 #define CONFIG_L1_INIT_RAM
 296 #define CONFIG_SYS_INIT_RAM_LOCK
 297 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 298 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 299 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 300 /* The assembler doesn't like typecast */
 301 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 302                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 303                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 304 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 305 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 306 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 307 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 308
 309 /*
 310  * Serial Port
 311  */
 312 #define CONFIG_SYS_NS16550_SERIAL
 313 #define CONFIG_SYS_NS16550_REG_SIZE     1
 314 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 315 #define CONFIG_SYS_BAUDRATE_TABLE       \
 316         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 317 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 318 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 319 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 320 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 321
 322 /*
 323  * I2C
 324  */
 325
 326 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 327 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 328 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 329 #define I2C_MUX_CH_DEFAULT      0x8
 330
 331 #define I2C_MUX_CH_VOL_MONITOR 0xa
 332
 333 /* Voltage monitor on channel 2*/
 334 #define I2C_VOL_MONITOR_ADDR           0x40
 335 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 336 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 337 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 338
 339 /* The lowest and highest voltage allowed for T208xQDS */
 340 #define VDD_MV_MIN                      819
 341 #define VDD_MV_MAX                      1212
 342
 343 /*
 344  * RapidIO
 345  */
 346 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 347 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 348 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 349 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 350 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 351 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 352 /*
 353  * for slave u-boot IMAGE instored in master memory space,
 354  * PHYS must be aligned based on the SIZE
 355  */
 356 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 357 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 358 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 359 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 360 /*
 361  * for slave UCODE and ENV instored in master memory space,
 362  * PHYS must be aligned based on the SIZE
 363  */
 364 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 365 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 366 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 367
 368 /* slave core release by master*/
 369 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 370 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 371
 372 /*
 373  * SRIO_PCIE_BOOT - SLAVE
 374  */
 375 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 376 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 377 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 378                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 379 #endif
 380
 381 /*
 382  * eSPI - Enhanced SPI
 383  */
 384
 385 /*
 386  * General PCI
 387  * Memory space is mapped 1-1, but I/O space must start from 0.
 388  */
 389 #define CONFIG_PCIE1            /* PCIE controller 1 */
 390 #define CONFIG_PCIE2            /* PCIE controller 2 */
 391 #define CONFIG_PCIE3            /* PCIE controller 3 */
 392 #define CONFIG_PCIE4            /* PCIE controller 4 */
 393 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 394 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 395 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 396 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 397 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 398
 399 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 400 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 401 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 402 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 403 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 404
 405 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 406 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 407 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 408 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 409 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 410
 411 /* controller 4, Base address 203000 */
 412 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 413 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 414 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 415
 416 #ifdef CONFIG_PCI
 417 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 418 #endif
 419
 420 /* Qman/Bman */
 421 #ifndef CONFIG_NOBQFMAN
 422 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 423 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 424 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 425 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 426 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 427 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 428 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 429 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 430 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 431                                         CONFIG_SYS_BMAN_CENA_SIZE)
 432 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 433 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 434 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 435 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 436 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 437 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 438 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 439 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 440 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 441 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 442 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 443                                         CONFIG_SYS_QMAN_CENA_SIZE)
 444 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 445 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 446
 447 #define CONFIG_SYS_DPAA_FMAN
 448 #define CONFIG_SYS_DPAA_PME
 449 #define CONFIG_SYS_PMAN
 450 #define CONFIG_SYS_DPAA_DCE
 451 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 452 #define CONFIG_SYS_INTERLAKEN
 453
 454 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 455 #endif /* CONFIG_NOBQFMAN */
 456
 457 #ifdef CONFIG_SYS_DPAA_FMAN
 458 #define RGMII_PHY1_ADDR 0x1
 459 #define RGMII_PHY2_ADDR 0x2
 460 #define FM1_10GEC1_PHY_ADDR       0x3
 461 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 462 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 463 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 464 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 465 #endif
 466
 467 /*
 468  * SATA
 469  */
 470 #ifdef CONFIG_FSL_SATA_V2
 471 #define CONFIG_SATA1
 472 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 473 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 474 #define CONFIG_SATA2
 475 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 476 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 477 #define CONFIG_LBA48
 478 #endif
 479
 480 /*
 481  * USB
 482  */
 483 #ifdef CONFIG_USB_EHCI_HCD
 484 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 485 #define CONFIG_HAS_FSL_DR_USB
 486 #endif
 487
 488 /*
 489  * SDHC
 490  */
 491 #ifdef CONFIG_MMC
 492 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 493 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 494 #endif
 495
 496 /*
 497  * Dynamic MTD Partition support with mtdparts
 498  */
 499
 500 /*
 501  * Environment
 502  */
 503 #define CONFIG_LOADS_ECHO       /* echo on for serial download */
 504 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 505
 506 /*
 507  * Miscellaneous configurable options
 508  */
 509
 510 /*
 511  * For booting Linux, the board info and command line data
 512  * have to be in the first 64 MB of memory, since this is
 513  * the maximum mapped by the Linux kernel during initialization.
 514  */
 515 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 516 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 517
 518 /*
 519  * Environment Configuration
 520  */
 521 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 522 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 523
 524 #define __USB_PHY_TYPE          utmi
 525
 526 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 527         "hwconfig=fsl_ddr:"                                     \
 528         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 529         "bank_intlv=auto;"                                      \
 530         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 531         "netdev=eth0\0"                                         \
 532         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 533         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 534         "tftpflash=tftpboot $loadaddr $uboot && "               \
 535         "protect off $ubootaddr +$filesize && "                 \
 536         "erase $ubootaddr +$filesize && "                       \
 537         "cp.b $loadaddr $ubootaddr $filesize && "               \
 538         "protect on $ubootaddr +$filesize && "                  \
 539         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 540         "consoledev=ttyS0\0"                                    \
 541         "ramdiskaddr=2000000\0"                                 \
 542         "ramdiskfile=t2080qds/ramdisk.uboot\0"                  \
 543         "fdtaddr=1e00000\0"                                     \
 544         "fdtfile=t2080qds/t2080qds.dtb\0"                       \
 545         "bdev=sda3\0"
 546
 547 /*
 548  * For emulation this causes u-boot to jump to the start of the
 549  * proof point app code automatically
 550  */
 551 #define PROOF_POINTS                            \
 552         "setenv bootargs root=/dev/$bdev rw "           \
 553         "console=$consoledev,$baudrate $othbootargs;"   \
 554         "cpu 1 release 0x29000000 - - -;"               \
 555         "cpu 2 release 0x29000000 - - -;"               \
 556         "cpu 3 release 0x29000000 - - -;"               \
 557         "cpu 4 release 0x29000000 - - -;"               \
 558         "cpu 5 release 0x29000000 - - -;"               \
 559         "cpu 6 release 0x29000000 - - -;"               \
 560         "cpu 7 release 0x29000000 - - -;"               \
 561         "go 0x29000000"
 562
 563 #define HVBOOT                          \
 564         "setenv bootargs config-addr=0x60000000; "      \
 565         "bootm 0x01000000 - 0x00f00000"
 566
 567 #define ALU                             \
 568         "setenv bootargs root=/dev/$bdev rw "           \
 569         "console=$consoledev,$baudrate $othbootargs;"   \
 570         "cpu 1 release 0x01000000 - - -;"               \
 571         "cpu 2 release 0x01000000 - - -;"               \
 572         "cpu 3 release 0x01000000 - - -;"               \
 573         "cpu 4 release 0x01000000 - - -;"               \
 574         "cpu 5 release 0x01000000 - - -;"               \
 575         "cpu 6 release 0x01000000 - - -;"               \
 576         "cpu 7 release 0x01000000 - - -;"               \
 577         "go 0x01000000"
 578
 579 #include <asm/fsl_secure_boot.h>
 580
 581 #endif  /* __T208xQDS_H */