1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2011-2013 Freescale Semiconductor, Inc.
8 * T2080/T2081 QDS board configuration file
14 #include <linux/stringify.h>
16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
17 #if defined(CONFIG_ARCH_T2080)
18 #define CONFIG_FSL_SATA_V2
19 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
20 #define CONFIG_SRIO1 /* SRIO port 1 */
21 #define CONFIG_SRIO2 /* SRIO port 2 */
22 #elif defined(CONFIG_ARCH_T2081)
25 /* High Level Configuration Options */
26 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
27 #define CONFIG_ENABLE_36BIT_PHYS
29 #ifdef CONFIG_PHYS_64BIT
30 #define CONFIG_ADDR_MAP 1
31 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
34 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
35 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
36 #define CONFIG_ENV_OVERWRITE
38 #ifdef CONFIG_RAMBOOT_PBL
39 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
41 #define CONFIG_SPL_FLUSH_IMAGE
42 #define CONFIG_SPL_PAD_TO 0x40000
43 #define CONFIG_SPL_MAX_SIZE 0x28000
44 #define RESET_VECTOR_OFFSET 0x27FFC
45 #define BOOT_PAGE_OFFSET 0x27000
46 #ifdef CONFIG_SPL_BUILD
47 #define CONFIG_SPL_SKIP_RELOCATE
48 #define CONFIG_SPL_COMMON_INIT_DDR
49 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
52 #ifdef CONFIG_MTD_RAW_NAND
53 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
54 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
55 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
56 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
57 #if defined(CONFIG_ARCH_T2080)
58 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg
59 #elif defined(CONFIG_ARCH_T2081)
60 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg
64 #ifdef CONFIG_SPIFLASH
65 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
66 #define CONFIG_SPL_SPI_FLASH_MINIMAL
67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
69 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
70 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
71 #ifndef CONFIG_SPL_BUILD
72 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
74 #if defined(CONFIG_ARCH_T2080)
75 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg
76 #elif defined(CONFIG_ARCH_T2081)
77 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg
82 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
83 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
84 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
85 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
86 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
87 #ifndef CONFIG_SPL_BUILD
88 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
90 #if defined(CONFIG_ARCH_T2080)
91 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg
92 #elif defined(CONFIG_ARCH_T2081)
93 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg
97 #endif /* CONFIG_RAMBOOT_PBL */
99 #define CONFIG_SRIO_PCIE_BOOT_MASTER
100 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
101 /* Set 1M boot space */
102 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
103 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
104 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
105 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
108 #ifndef CONFIG_RESET_VECTOR_ADDRESS
109 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
113 * These can be toggled for performance analysis, otherwise use default.
115 #define CONFIG_SYS_CACHE_STASHING
116 #define CONFIG_BTB /* toggle branch predition */
117 #define CONFIG_DDR_ECC
118 #ifdef CONFIG_DDR_ECC
119 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
120 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
123 #if defined(CONFIG_SPIFLASH)
124 #elif defined(CONFIG_SDCARD)
125 #define CONFIG_SYS_MMC_ENV_DEV 0
129 unsigned long get_board_sys_clk(void);
130 unsigned long get_board_ddr_clk(void);
133 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
134 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
137 * Config the L3 Cache as L3 SRAM
139 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
140 #define CONFIG_SYS_L3_SIZE (512 << 10)
141 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
142 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
143 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
144 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
145 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
147 #define CONFIG_SYS_DCSRBAR 0xf0000000
148 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
151 #define CONFIG_ID_EEPROM
152 #define CONFIG_SYS_I2C_EEPROM_NXID
153 #define CONFIG_SYS_EEPROM_BUS_NUM 0
154 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
155 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
160 #define CONFIG_VERY_BIG_RAM
161 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
162 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
163 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
164 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
165 #define CONFIG_DDR_SPD
166 #define CONFIG_SYS_SPD_BUS_NUM 0
167 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
168 #define SPD_EEPROM_ADDRESS1 0x51
169 #define SPD_EEPROM_ADDRESS2 0x52
170 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
171 #define CTRL_INTLV_PREFERED cacheline
176 #define CONFIG_SYS_FLASH_BASE 0xe0000000
177 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
178 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
179 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
181 CSPR_PORT_SIZE_16 | \
184 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
185 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
186 CSPR_PORT_SIZE_16 | \
189 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
190 /* NOR Flash Timing Params */
191 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
193 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
194 FTIM0_NOR_TEADC(0x5) | \
195 FTIM0_NOR_TEAHC(0x5))
196 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
197 FTIM1_NOR_TRAD_NOR(0x1A) |\
198 FTIM1_NOR_TSEQRAD_NOR(0x13))
199 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
200 FTIM2_NOR_TCH(0x4) | \
201 FTIM2_NOR_TWPH(0x0E) | \
203 #define CONFIG_SYS_NOR_FTIM3 0x0
205 #define CONFIG_SYS_FLASH_QUIET_TEST
206 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
208 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
209 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
210 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
211 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
213 #define CONFIG_SYS_FLASH_EMPTY_INFO
214 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
215 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
217 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
218 #define QIXIS_BASE 0xffdf0000
219 #define QIXIS_LBMAP_SWITCH 6
220 #define QIXIS_LBMAP_MASK 0x0f
221 #define QIXIS_LBMAP_SHIFT 0
222 #define QIXIS_LBMAP_DFLTBANK 0x00
223 #define QIXIS_LBMAP_ALTBANK 0x04
224 #define QIXIS_LBMAP_NAND 0x09
225 #define QIXIS_LBMAP_SD 0x00
226 #define QIXIS_RCW_SRC_NAND 0x104
227 #define QIXIS_RCW_SRC_SD 0x040
228 #define QIXIS_RST_CTL_RESET 0x83
229 #define QIXIS_RST_FORCE_MEM 0x1
230 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
231 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
232 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
233 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
235 #define CONFIG_SYS_CSPR3_EXT (0xf)
236 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
240 #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
241 #define CONFIG_SYS_CSOR3 0x0
242 /* QIXIS Timing parameters for IFC CS3 */
243 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
244 FTIM0_GPCM_TEADC(0x0e) | \
245 FTIM0_GPCM_TEAHC(0x0e))
246 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
247 FTIM1_GPCM_TRAD(0x3f))
248 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
249 FTIM2_GPCM_TCH(0x8) | \
250 FTIM2_GPCM_TWP(0x1f))
251 #define CONFIG_SYS_CS3_FTIM3 0x0
253 /* NAND Flash on IFC */
254 #define CONFIG_NAND_FSL_IFC
255 #define CONFIG_SYS_NAND_BASE 0xff800000
256 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
258 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
259 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
260 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
261 | CSPR_MSEL_NAND /* MSEL = NAND */ \
263 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
265 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
266 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
267 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
268 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
269 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
270 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
271 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
273 #define CONFIG_SYS_NAND_ONFI_DETECTION
275 /* ONFI NAND Flash mode0 Timing Params */
276 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
277 FTIM0_NAND_TWP(0x18) | \
278 FTIM0_NAND_TWCHT(0x07) | \
279 FTIM0_NAND_TWH(0x0a))
280 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
281 FTIM1_NAND_TWBE(0x39) | \
282 FTIM1_NAND_TRR(0x0e) | \
283 FTIM1_NAND_TRP(0x18))
284 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
285 FTIM2_NAND_TREH(0x0a) | \
286 FTIM2_NAND_TWHRE(0x1e))
287 #define CONFIG_SYS_NAND_FTIM3 0x0
289 #define CONFIG_SYS_NAND_DDR_LAW 11
290 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
291 #define CONFIG_SYS_MAX_NAND_DEVICE 1
292 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
294 #if defined(CONFIG_MTD_RAW_NAND)
295 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
296 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
297 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
298 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
299 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
300 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
301 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
302 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
303 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
304 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
305 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
306 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
307 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
308 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
309 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
310 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
311 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
312 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
313 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
314 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
315 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
316 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
317 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
318 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
320 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
321 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
322 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
323 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
324 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
325 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
326 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
327 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
328 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
329 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
330 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
331 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
332 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
333 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
334 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
335 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
336 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
337 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
338 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
339 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
340 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
341 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
342 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
343 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
346 #if defined(CONFIG_RAMBOOT_PBL)
347 #define CONFIG_SYS_RAMBOOT
350 #ifdef CONFIG_SPL_BUILD
351 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
353 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
356 #define CONFIG_HWCONFIG
358 /* define to use L1 as initial stack */
359 #define CONFIG_L1_INIT_RAM
360 #define CONFIG_SYS_INIT_RAM_LOCK
361 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
362 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
363 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
364 /* The assembler doesn't like typecast */
365 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
366 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
367 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
368 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
369 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
370 GENERATED_GBL_DATA_SIZE)
371 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
372 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
373 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
378 #define CONFIG_SYS_NS16550_SERIAL
379 #define CONFIG_SYS_NS16550_REG_SIZE 1
380 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
381 #define CONFIG_SYS_BAUDRATE_TABLE \
382 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
383 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
384 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
385 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
386 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
391 #ifndef CONFIG_DM_I2C
392 #define CONFIG_SYS_I2C
393 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
394 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
395 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
396 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
397 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
398 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
399 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
400 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
401 #define CONFIG_SYS_FSL_I2C_SPEED 100000
402 #define CONFIG_SYS_FSL_I2C2_SPEED 100000
403 #define CONFIG_SYS_FSL_I2C3_SPEED 100000
404 #define CONFIG_SYS_FSL_I2C4_SPEED 100000
407 #define CONFIG_SYS_I2C_FSL
409 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
410 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
411 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
412 #define I2C_MUX_CH_DEFAULT 0x8
414 #define I2C_MUX_CH_VOL_MONITOR 0xa
416 /* Voltage monitor on channel 2*/
417 #define I2C_VOL_MONITOR_ADDR 0x40
418 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
419 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
420 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
422 #define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv"
423 #ifndef CONFIG_SPL_BUILD
426 #define CONFIG_VOL_MONITOR_IR36021_SET
427 #define CONFIG_VOL_MONITOR_IR36021_READ
428 /* The lowest and highest voltage allowed for T208xQDS */
429 #define VDD_MV_MIN 819
430 #define VDD_MV_MAX 1212
435 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
436 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
437 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
438 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
439 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
440 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
442 * for slave u-boot IMAGE instored in master memory space,
443 * PHYS must be aligned based on the SIZE
445 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
446 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
447 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
448 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
450 * for slave UCODE and ENV instored in master memory space,
451 * PHYS must be aligned based on the SIZE
453 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
454 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
455 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
457 /* slave core release by master*/
458 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
459 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
462 * SRIO_PCIE_BOOT - SLAVE
464 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
465 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
466 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
467 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
471 * eSPI - Enhanced SPI
476 * Memory space is mapped 1-1, but I/O space must start from 0.
478 #define CONFIG_PCIE1 /* PCIE controller 1 */
479 #define CONFIG_PCIE2 /* PCIE controller 2 */
480 #define CONFIG_PCIE3 /* PCIE controller 3 */
481 #define CONFIG_PCIE4 /* PCIE controller 4 */
482 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
483 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
484 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
485 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
486 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
487 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
489 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
490 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
491 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
492 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
493 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
495 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
496 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
497 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
498 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
499 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
501 /* controller 4, Base address 203000 */
502 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
503 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
504 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
507 #if !defined(CONFIG_DM_PCI)
508 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
509 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
510 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
511 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
512 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
513 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
514 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
515 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
516 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
517 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
518 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
519 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
520 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
521 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
522 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
523 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
524 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
525 #define CONFIG_PCI_INDIRECT_BRIDGE
527 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
531 #ifndef CONFIG_NOBQFMAN
532 #define CONFIG_SYS_BMAN_NUM_PORTALS 18
533 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
534 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
535 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
536 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
537 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
538 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
539 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
540 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
541 CONFIG_SYS_BMAN_CENA_SIZE)
542 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
543 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
544 #define CONFIG_SYS_QMAN_NUM_PORTALS 18
545 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
546 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
547 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
548 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
549 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
550 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
551 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
552 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
553 CONFIG_SYS_QMAN_CENA_SIZE)
554 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
555 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
557 #define CONFIG_SYS_DPAA_FMAN
558 #define CONFIG_SYS_DPAA_PME
559 #define CONFIG_SYS_PMAN
560 #define CONFIG_SYS_DPAA_DCE
561 #define CONFIG_SYS_DPAA_RMAN /* RMan */
562 #define CONFIG_SYS_INTERLAKEN
564 /* Default address of microcode for the Linux Fman driver */
565 #if defined(CONFIG_SPIFLASH)
567 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
568 * env, so we got 0x110000.
570 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
571 #elif defined(CONFIG_SDCARD)
573 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
574 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
575 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
577 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
578 #elif defined(CONFIG_MTD_RAW_NAND)
579 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
580 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
582 * Slave has no ucode locally, it can fetch this from remote. When implementing
583 * in two corenet boards, slave's ucode could be stored in master's memory
584 * space, the address can be mapped from slave TLB->slave LAW->
585 * slave SRIO or PCIE outbound window->master inbound window->
586 * master LAW->the ucode address in master's memory space.
588 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
590 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
592 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
593 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
594 #endif /* CONFIG_NOBQFMAN */
596 #ifdef CONFIG_SYS_DPAA_FMAN
597 #define RGMII_PHY1_ADDR 0x1
598 #define RGMII_PHY2_ADDR 0x2
599 #define FM1_10GEC1_PHY_ADDR 0x3
600 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
601 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
602 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
603 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
606 #ifdef CONFIG_FMAN_ENET
607 #define CONFIG_ETHPRIME "FM1@DTSEC3"
613 #ifdef CONFIG_FSL_SATA_V2
614 #define CONFIG_SYS_SATA_MAX_DEVICE 2
616 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
617 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
619 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
620 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
627 #ifdef CONFIG_USB_EHCI_HCD
628 #define CONFIG_USB_EHCI_FSL
629 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
630 #define CONFIG_HAS_FSL_DR_USB
637 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
638 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
639 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
640 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT
644 * Dynamic MTD Partition support with mtdparts
650 #define CONFIG_LOADS_ECHO /* echo on for serial download */
651 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
654 * Miscellaneous configurable options
656 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
659 * For booting Linux, the board info and command line data
660 * have to be in the first 64 MB of memory, since this is
661 * the maximum mapped by the Linux kernel during initialization.
663 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
664 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
666 #ifdef CONFIG_CMD_KGDB
667 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
668 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
672 * Environment Configuration
674 #define CONFIG_ROOTPATH "/opt/nfsroot"
675 #define CONFIG_BOOTFILE "uImage"
676 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
678 /* default location for tftp and bootm */
679 #define CONFIG_LOADADDR 1000000
680 #define __USB_PHY_TYPE utmi
682 #define CONFIG_EXTRA_ENV_SETTINGS \
683 "hwconfig=fsl_ddr:" \
684 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
686 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
688 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
689 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
690 "tftpflash=tftpboot $loadaddr $uboot && " \
691 "protect off $ubootaddr +$filesize && " \
692 "erase $ubootaddr +$filesize && " \
693 "cp.b $loadaddr $ubootaddr $filesize && " \
694 "protect on $ubootaddr +$filesize && " \
695 "cmp.b $loadaddr $ubootaddr $filesize\0" \
696 "consoledev=ttyS0\0" \
697 "ramdiskaddr=2000000\0" \
698 "ramdiskfile=t2080qds/ramdisk.uboot\0" \
699 "fdtaddr=1e00000\0" \
700 "fdtfile=t2080qds/t2080qds.dtb\0" \
704 * For emulation this causes u-boot to jump to the start of the
705 * proof point app code automatically
707 #define CONFIG_PROOF_POINTS \
708 "setenv bootargs root=/dev/$bdev rw " \
709 "console=$consoledev,$baudrate $othbootargs;" \
710 "cpu 1 release 0x29000000 - - -;" \
711 "cpu 2 release 0x29000000 - - -;" \
712 "cpu 3 release 0x29000000 - - -;" \
713 "cpu 4 release 0x29000000 - - -;" \
714 "cpu 5 release 0x29000000 - - -;" \
715 "cpu 6 release 0x29000000 - - -;" \
716 "cpu 7 release 0x29000000 - - -;" \
719 #define CONFIG_HVBOOT \
720 "setenv bootargs config-addr=0x60000000; " \
721 "bootm 0x01000000 - 0x00f00000"
724 "setenv bootargs root=/dev/$bdev rw " \
725 "console=$consoledev,$baudrate $othbootargs;" \
726 "cpu 1 release 0x01000000 - - -;" \
727 "cpu 2 release 0x01000000 - - -;" \
728 "cpu 3 release 0x01000000 - - -;" \
729 "cpu 4 release 0x01000000 - - -;" \
730 "cpu 5 release 0x01000000 - - -;" \
731 "cpu 6 release 0x01000000 - - -;" \
732 "cpu 7 release 0x01000000 - - -;" \
735 #define CONFIG_LINUX \
736 "setenv bootargs root=/dev/ram rw " \
737 "console=$consoledev,$baudrate $othbootargs;" \
738 "setenv ramdiskaddr 0x02000000;" \
739 "setenv fdtaddr 0x00c00000;" \
740 "setenv loadaddr 0x1000000;" \
741 "bootm $loadaddr $ramdiskaddr $fdtaddr"
743 #define CONFIG_HDBOOT \
744 "setenv bootargs root=/dev/$bdev rw " \
745 "console=$consoledev,$baudrate $othbootargs;" \
746 "tftp $loadaddr $bootfile;" \
747 "tftp $fdtaddr $fdtfile;" \
748 "bootm $loadaddr - $fdtaddr"
750 #define CONFIG_NFSBOOTCOMMAND \
751 "setenv bootargs root=/dev/nfs rw " \
752 "nfsroot=$serverip:$rootpath " \
753 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
754 "console=$consoledev,$baudrate $othbootargs;" \
755 "tftp $loadaddr $bootfile;" \
756 "tftp $fdtaddr $fdtfile;" \
757 "bootm $loadaddr - $fdtaddr"
759 #define CONFIG_RAMBOOTCOMMAND \
760 "setenv bootargs root=/dev/ram rw " \
761 "console=$consoledev,$baudrate $othbootargs;" \
762 "tftp $ramdiskaddr $ramdiskfile;" \
763 "tftp $loadaddr $bootfile;" \
764 "tftp $fdtaddr $fdtfile;" \
765 "bootm $loadaddr $ramdiskaddr $fdtaddr"
767 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
769 #include <asm/fsl_secure_boot.h>
771 #endif /* __T208xQDS_H */