include/configs/T208xQDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2013 Freescale Semiconductor, Inc.
   4  */
   5
   6 /*
   7  * T2080/T2081 QDS board configuration file
   8  */
   9
  10 #ifndef __T208xQDS_H
  11 #define __T208xQDS_H
  12
  13 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  14 #if defined(CONFIG_ARCH_T2080)
  15 #define CONFIG_FSL_SATA_V2
  16 #define CONFIG_SYS_SRIO         /* Enable Serial RapidIO Support */
  17 #define CONFIG_SRIO1            /* SRIO port 1 */
  18 #define CONFIG_SRIO2            /* SRIO port 2 */
  19 #elif defined(CONFIG_ARCH_T2081)
  20 #endif
  21
  22 /* High Level Configuration Options */
  23 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
  24 #define CONFIG_ENABLE_36BIT_PHYS
  25
  26 #ifdef CONFIG_PHYS_64BIT
  27 #define CONFIG_ADDR_MAP 1
  28 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  29 #endif
  30
  31 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  32 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  33 #define CONFIG_ENV_OVERWRITE
  34
  35 #ifdef CONFIG_RAMBOOT_PBL
  36 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
  37
  38 #define CONFIG_SPL_FLUSH_IMAGE
  39 #define CONFIG_SPL_PAD_TO               0x40000
  40 #define CONFIG_SPL_MAX_SIZE             0x28000
  41 #define RESET_VECTOR_OFFSET             0x27FFC
  42 #define BOOT_PAGE_OFFSET                0x27000
  43 #ifdef CONFIG_SPL_BUILD
  44 #define CONFIG_SPL_SKIP_RELOCATE
  45 #define CONFIG_SPL_COMMON_INIT_DDR
  46 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  47 #endif
  48
  49 #ifdef CONFIG_NAND
  50 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  51 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  52 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  53 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  54 #if defined(CONFIG_ARCH_T2080)
  55 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg
  56 #elif defined(CONFIG_ARCH_T2081)
  57 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg
  58 #endif
  59 #endif
  60
  61 #ifdef CONFIG_SPIFLASH
  62 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  63 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
  66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
  67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  68 #ifndef CONFIG_SPL_BUILD
  69 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  70 #endif
  71 #if defined(CONFIG_ARCH_T2080)
  72 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg
  73 #elif defined(CONFIG_ARCH_T2081)
  74 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg
  75 #endif
  76 #endif
  77
  78 #ifdef CONFIG_SDCARD
  79 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  80 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  81 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
  82 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
  83 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  84 #ifndef CONFIG_SPL_BUILD
  85 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  86 #endif
  87 #if defined(CONFIG_ARCH_T2080)
  88 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg
  89 #elif defined(CONFIG_ARCH_T2081)
  90 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg
  91 #endif
  92 #endif
  93
  94 #endif /* CONFIG_RAMBOOT_PBL */
  95
  96 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  97 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  98 /* Set 1M boot space */
  99 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 100 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
 101                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 102 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 103 #endif
 104
 105 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 106 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 107 #endif
 108
 109 /*
 110  * These can be toggled for performance analysis, otherwise use default.
 111  */
 112 #define CONFIG_SYS_CACHE_STASHING
 113 #define CONFIG_BTB              /* toggle branch predition */
 114 #define CONFIG_DDR_ECC
 115 #ifdef CONFIG_DDR_ECC
 116 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 117 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 118 #endif
 119
 120 #if defined(CONFIG_SPIFLASH)
 121 #define CONFIG_ENV_SIZE         0x2000     /* 8KB */
 122 #define CONFIG_ENV_OFFSET       0x100000   /* 1MB */
 123 #define CONFIG_ENV_SECT_SIZE    0x10000
 124 #elif defined(CONFIG_SDCARD)
 125 #define CONFIG_SYS_MMC_ENV_DEV  0
 126 #define CONFIG_ENV_SIZE         0x2000
 127 #define CONFIG_ENV_OFFSET       (512 * 0x800)
 128 #elif defined(CONFIG_NAND)
 129 #define CONFIG_ENV_SIZE         0x2000
 130 #define CONFIG_ENV_OFFSET       (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 131 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 132 #define CONFIG_ENV_ADDR         0xffe20000
 133 #define CONFIG_ENV_SIZE         0x2000
 134 #elif defined(CONFIG_ENV_IS_NOWHERE)
 135 #define CONFIG_ENV_SIZE         0x2000
 136 #else
 137 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 138 #define CONFIG_ENV_SIZE         0x2000
 139 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 140 #endif
 141
 142 #ifndef __ASSEMBLY__
 143 unsigned long get_board_sys_clk(void);
 144 unsigned long get_board_ddr_clk(void);
 145 #endif
 146
 147 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
 148 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 149
 150 /*
 151  * Config the L3 Cache as L3 SRAM
 152  */
 153 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 154 #define CONFIG_SYS_L3_SIZE              (512 << 10)
 155 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 156 #ifdef CONFIG_RAMBOOT_PBL
 157 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 158 #endif
 159 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 160 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
 161 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 162
 163 #define CONFIG_SYS_DCSRBAR      0xf0000000
 164 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
 165
 166 /* EEPROM */
 167 #define CONFIG_ID_EEPROM
 168 #define CONFIG_SYS_I2C_EEPROM_NXID
 169 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 170 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 171 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 172
 173 /*
 174  * DDR Setup
 175  */
 176 #define CONFIG_VERY_BIG_RAM
 177 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 178 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 179 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
 180 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 181 #define CONFIG_DDR_SPD
 182 #define CONFIG_SYS_SPD_BUS_NUM  0
 183 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 184 #define SPD_EEPROM_ADDRESS1     0x51
 185 #define SPD_EEPROM_ADDRESS2     0x52
 186 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 187 #define CTRL_INTLV_PREFERED     cacheline
 188
 189 /*
 190  * IFC Definitions
 191  */
 192 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 193 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 194 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 195 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 196                                 + 0x8000000) | \
 197                                 CSPR_PORT_SIZE_16 | \
 198                                 CSPR_MSEL_NOR | \
 199                                 CSPR_V)
 200 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 201 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 202                                 CSPR_PORT_SIZE_16 | \
 203                                 CSPR_MSEL_NOR | \
 204                                 CSPR_V)
 205 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 206 /* NOR Flash Timing Params */
 207 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 208
 209 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 210                                 FTIM0_NOR_TEADC(0x5) | \
 211                                 FTIM0_NOR_TEAHC(0x5))
 212 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 213                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 214                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 215 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 216                                 FTIM2_NOR_TCH(0x4) | \
 217                                 FTIM2_NOR_TWPH(0x0E) | \
 218                                 FTIM2_NOR_TWP(0x1c))
 219 #define CONFIG_SYS_NOR_FTIM3    0x0
 220
 221 #define CONFIG_SYS_FLASH_QUIET_TEST
 222 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 223
 224 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 225 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 226 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 227 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 228
 229 #define CONFIG_SYS_FLASH_EMPTY_INFO
 230 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 231                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 232
 233 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 234 #define QIXIS_BASE                      0xffdf0000
 235 #define QIXIS_LBMAP_SWITCH              6
 236 #define QIXIS_LBMAP_MASK                0x0f
 237 #define QIXIS_LBMAP_SHIFT               0
 238 #define QIXIS_LBMAP_DFLTBANK            0x00
 239 #define QIXIS_LBMAP_ALTBANK             0x04
 240 #define QIXIS_LBMAP_NAND                0x09
 241 #define QIXIS_LBMAP_SD                  0x00
 242 #define QIXIS_RCW_SRC_NAND              0x104
 243 #define QIXIS_RCW_SRC_SD                0x040
 244 #define QIXIS_RST_CTL_RESET             0x83
 245 #define QIXIS_RST_FORCE_MEM             0x1
 246 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 247 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 248 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 249 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 250
 251 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 252 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 253                                 | CSPR_PORT_SIZE_8 \
 254                                 | CSPR_MSEL_GPCM \
 255                                 | CSPR_V)
 256 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 257 #define CONFIG_SYS_CSOR3        0x0
 258 /* QIXIS Timing parameters for IFC CS3 */
 259 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 260                                         FTIM0_GPCM_TEADC(0x0e) | \
 261                                         FTIM0_GPCM_TEAHC(0x0e))
 262 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 263                                         FTIM1_GPCM_TRAD(0x3f))
 264 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 265                                         FTIM2_GPCM_TCH(0x8) | \
 266                                         FTIM2_GPCM_TWP(0x1f))
 267 #define CONFIG_SYS_CS3_FTIM3            0x0
 268
 269 /* NAND Flash on IFC */
 270 #define CONFIG_NAND_FSL_IFC
 271 #define CONFIG_SYS_NAND_BASE            0xff800000
 272 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 273
 274 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 275 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 276                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 277                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 278                                 | CSPR_V)
 279 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 280
 281 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 282                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 283                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 284                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 285                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 286                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 287                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 288
 289 #define CONFIG_SYS_NAND_ONFI_DETECTION
 290
 291 /* ONFI NAND Flash mode0 Timing Params */
 292 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 293                                         FTIM0_NAND_TWP(0x18)    | \
 294                                         FTIM0_NAND_TWCHT(0x07)  | \
 295                                         FTIM0_NAND_TWH(0x0a))
 296 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 297                                         FTIM1_NAND_TWBE(0x39)   | \
 298                                         FTIM1_NAND_TRR(0x0e)    | \
 299                                         FTIM1_NAND_TRP(0x18))
 300 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 301                                         FTIM2_NAND_TREH(0x0a)   | \
 302                                         FTIM2_NAND_TWHRE(0x1e))
 303 #define CONFIG_SYS_NAND_FTIM3           0x0
 304
 305 #define CONFIG_SYS_NAND_DDR_LAW         11
 306 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 307 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 308 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 309
 310 #if defined(CONFIG_NAND)
 311 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 312 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 313 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 314 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 315 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 316 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 317 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 318 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 319 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 320 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 321 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 322 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 323 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 324 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 325 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 326 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 327 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 328 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 329 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 330 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 331 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 332 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 333 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 334 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 335 #else
 336 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 337 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 338 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 339 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 340 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 341 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 342 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 343 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 344 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 345 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 346 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 347 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 348 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 349 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 350 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 351 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 352 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 353 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 354 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 355 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 356 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 357 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 358 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 359 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 360 #endif
 361
 362 #if defined(CONFIG_RAMBOOT_PBL)
 363 #define CONFIG_SYS_RAMBOOT
 364 #endif
 365
 366 #ifdef CONFIG_SPL_BUILD
 367 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 368 #else
 369 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 370 #endif
 371
 372 #define CONFIG_HWCONFIG
 373
 374 /* define to use L1 as initial stack */
 375 #define CONFIG_L1_INIT_RAM
 376 #define CONFIG_SYS_INIT_RAM_LOCK
 377 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 378 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 379 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 380 /* The assembler doesn't like typecast */
 381 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 382                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 383                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 384 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 385 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 386                                                 GENERATED_GBL_DATA_SIZE)
 387 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 388 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 389 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 390
 391 /*
 392  * Serial Port
 393  */
 394 #define CONFIG_SYS_NS16550_SERIAL
 395 #define CONFIG_SYS_NS16550_REG_SIZE     1
 396 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 397 #define CONFIG_SYS_BAUDRATE_TABLE       \
 398         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 399 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 400 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 401 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 402 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 403
 404 /*
 405  * I2C
 406  */
 407 #define CONFIG_SYS_I2C
 408 #define CONFIG_SYS_I2C_FSL
 409 #define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
 410 #define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
 411 #define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
 412 #define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
 413 #define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
 414 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
 415 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
 416 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
 417 #define CONFIG_SYS_FSL_I2C_SPEED   100000
 418 #define CONFIG_SYS_FSL_I2C2_SPEED  100000
 419 #define CONFIG_SYS_FSL_I2C3_SPEED  100000
 420 #define CONFIG_SYS_FSL_I2C4_SPEED  100000
 421 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 422 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 423 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 424 #define I2C_MUX_CH_DEFAULT      0x8
 425
 426 #define I2C_MUX_CH_VOL_MONITOR 0xa
 427
 428 /* Voltage monitor on channel 2*/
 429 #define I2C_VOL_MONITOR_ADDR           0x40
 430 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 431 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 432 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 433
 434 #define CONFIG_VID_FLS_ENV              "t208xqds_vdd_mv"
 435 #ifndef CONFIG_SPL_BUILD
 436 #define CONFIG_VID
 437 #endif
 438 #define CONFIG_VOL_MONITOR_IR36021_SET
 439 #define CONFIG_VOL_MONITOR_IR36021_READ
 440 /* The lowest and highest voltage allowed for T208xQDS */
 441 #define VDD_MV_MIN                      819
 442 #define VDD_MV_MAX                      1212
 443
 444 /*
 445  * RapidIO
 446  */
 447 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 448 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 449 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 450 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 451 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 452 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 453 /*
 454  * for slave u-boot IMAGE instored in master memory space,
 455  * PHYS must be aligned based on the SIZE
 456  */
 457 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 458 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 459 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 460 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 461 /*
 462  * for slave UCODE and ENV instored in master memory space,
 463  * PHYS must be aligned based on the SIZE
 464  */
 465 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 466 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 467 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 468
 469 /* slave core release by master*/
 470 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 471 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 472
 473 /*
 474  * SRIO_PCIE_BOOT - SLAVE
 475  */
 476 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 477 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 478 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 479                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 480 #endif
 481
 482 /*
 483  * eSPI - Enhanced SPI
 484  */
 485
 486 /*
 487  * General PCI
 488  * Memory space is mapped 1-1, but I/O space must start from 0.
 489  */
 490 #define CONFIG_PCIE1            /* PCIE controller 1 */
 491 #define CONFIG_PCIE2            /* PCIE controller 2 */
 492 #define CONFIG_PCIE3            /* PCIE controller 3 */
 493 #define CONFIG_PCIE4            /* PCIE controller 4 */
 494 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 495 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 496 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 497 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 498 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 499 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 500
 501 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 502 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 503 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 504 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 505 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 506
 507 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 508 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 509 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 510 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 511 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 512
 513 /* controller 4, Base address 203000 */
 514 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 515 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 516 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 517
 518 #ifdef CONFIG_PCI
 519 #if !defined(CONFIG_DM_PCI)
 520 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 521 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 522 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 523 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 524 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 525 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 526 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000 /* 256M */
 527 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 528 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 529 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 530 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 531 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 532 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 533 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 534 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 535 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 536 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 537 #define CONFIG_PCI_INDIRECT_BRIDGE
 538 #endif
 539 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 540 #endif
 541
 542 /* Qman/Bman */
 543 #ifndef CONFIG_NOBQFMAN
 544 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 545 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 546 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 547 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 548 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 549 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 550 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 551 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 552 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 553                                         CONFIG_SYS_BMAN_CENA_SIZE)
 554 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 555 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 556 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 557 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 558 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 559 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 560 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 561 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 562 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 563 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 564 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 565                                         CONFIG_SYS_QMAN_CENA_SIZE)
 566 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 567 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 568
 569 #define CONFIG_SYS_DPAA_FMAN
 570 #define CONFIG_SYS_DPAA_PME
 571 #define CONFIG_SYS_PMAN
 572 #define CONFIG_SYS_DPAA_DCE
 573 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 574 #define CONFIG_SYS_INTERLAKEN
 575
 576 /* Default address of microcode for the Linux Fman driver */
 577 #if defined(CONFIG_SPIFLASH)
 578 /*
 579  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 580  * env, so we got 0x110000.
 581  */
 582 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 583 #elif defined(CONFIG_SDCARD)
 584 /*
 585  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 586  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 587  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 588  */
 589 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 590 #elif defined(CONFIG_NAND)
 591 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 592 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 593 /*
 594  * Slave has no ucode locally, it can fetch this from remote. When implementing
 595  * in two corenet boards, slave's ucode could be stored in master's memory
 596  * space, the address can be mapped from slave TLB->slave LAW->
 597  * slave SRIO or PCIE outbound window->master inbound window->
 598  * master LAW->the ucode address in master's memory space.
 599  */
 600 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 601 #else
 602 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
 603 #endif
 604 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 605 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 606 #endif /* CONFIG_NOBQFMAN */
 607
 608 #ifdef CONFIG_SYS_DPAA_FMAN
 609 #define CONFIG_PHY_VITESSE
 610 #define CONFIG_PHY_REALTEK
 611 #define CONFIG_PHY_TERANETICS
 612 #define RGMII_PHY1_ADDR 0x1
 613 #define RGMII_PHY2_ADDR 0x2
 614 #define FM1_10GEC1_PHY_ADDR       0x3
 615 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 616 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 617 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 618 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 619 #endif
 620
 621 #ifdef CONFIG_FMAN_ENET
 622 #define CONFIG_ETHPRIME         "FM1@DTSEC3"
 623 #endif
 624
 625 /*
 626  * SATA
 627  */
 628 #ifdef CONFIG_FSL_SATA_V2
 629 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 630 #define CONFIG_SATA1
 631 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 632 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 633 #define CONFIG_SATA2
 634 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 635 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 636 #define CONFIG_LBA48
 637 #endif
 638
 639 /*
 640  * USB
 641  */
 642 #ifdef CONFIG_USB_EHCI_HCD
 643 #define CONFIG_USB_EHCI_FSL
 644 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 645 #define CONFIG_HAS_FSL_DR_USB
 646 #endif
 647
 648 /*
 649  * SDHC
 650  */
 651 #ifdef CONFIG_MMC
 652 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
 653 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 654 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 655 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 656 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT
 657 #endif
 658
 659 /*
 660  * Dynamic MTD Partition support with mtdparts
 661  */
 662
 663 /*
 664  * Environment
 665  */
 666 #define CONFIG_LOADS_ECHO       /* echo on for serial download */
 667 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 668
 669 /*
 670  * Miscellaneous configurable options
 671  */
 672 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
 673
 674 /*
 675  * For booting Linux, the board info and command line data
 676  * have to be in the first 64 MB of memory, since this is
 677  * the maximum mapped by the Linux kernel during initialization.
 678  */
 679 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 680 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 681
 682 #ifdef CONFIG_CMD_KGDB
 683 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 684 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 685 #endif
 686
 687 /*
 688  * Environment Configuration
 689  */
 690 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 691 #define CONFIG_BOOTFILE  "uImage"
 692 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 693
 694 /* default location for tftp and bootm */
 695 #define CONFIG_LOADADDR         1000000
 696 #define __USB_PHY_TYPE          utmi
 697
 698 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 699         "hwconfig=fsl_ddr:"                                     \
 700         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 701         "bank_intlv=auto;"                                      \
 702         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 703         "netdev=eth0\0"                                         \
 704         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 705         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 706         "tftpflash=tftpboot $loadaddr $uboot && "               \
 707         "protect off $ubootaddr +$filesize && "                 \
 708         "erase $ubootaddr +$filesize && "                       \
 709         "cp.b $loadaddr $ubootaddr $filesize && "               \
 710         "protect on $ubootaddr +$filesize && "                  \
 711         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 712         "consoledev=ttyS0\0"                                    \
 713         "ramdiskaddr=2000000\0"                                 \
 714         "ramdiskfile=t2080qds/ramdisk.uboot\0"                  \
 715         "fdtaddr=1e00000\0"                                     \
 716         "fdtfile=t2080qds/t2080qds.dtb\0"                       \
 717         "bdev=sda3\0"
 718
 719 /*
 720  * For emulation this causes u-boot to jump to the start of the
 721  * proof point app code automatically
 722  */
 723 #define CONFIG_PROOF_POINTS                             \
 724         "setenv bootargs root=/dev/$bdev rw "           \
 725         "console=$consoledev,$baudrate $othbootargs;"   \
 726         "cpu 1 release 0x29000000 - - -;"               \
 727         "cpu 2 release 0x29000000 - - -;"               \
 728         "cpu 3 release 0x29000000 - - -;"               \
 729         "cpu 4 release 0x29000000 - - -;"               \
 730         "cpu 5 release 0x29000000 - - -;"               \
 731         "cpu 6 release 0x29000000 - - -;"               \
 732         "cpu 7 release 0x29000000 - - -;"               \
 733         "go 0x29000000"
 734
 735 #define CONFIG_HVBOOT                           \
 736         "setenv bootargs config-addr=0x60000000; "      \
 737         "bootm 0x01000000 - 0x00f00000"
 738
 739 #define CONFIG_ALU                              \
 740         "setenv bootargs root=/dev/$bdev rw "           \
 741         "console=$consoledev,$baudrate $othbootargs;"   \
 742         "cpu 1 release 0x01000000 - - -;"               \
 743         "cpu 2 release 0x01000000 - - -;"               \
 744         "cpu 3 release 0x01000000 - - -;"               \
 745         "cpu 4 release 0x01000000 - - -;"               \
 746         "cpu 5 release 0x01000000 - - -;"               \
 747         "cpu 6 release 0x01000000 - - -;"               \
 748         "cpu 7 release 0x01000000 - - -;"               \
 749         "go 0x01000000"
 750
 751 #define CONFIG_LINUX                            \
 752         "setenv bootargs root=/dev/ram rw "             \
 753         "console=$consoledev,$baudrate $othbootargs;"   \
 754         "setenv ramdiskaddr 0x02000000;"                \
 755         "setenv fdtaddr 0x00c00000;"                    \
 756         "setenv loadaddr 0x1000000;"                    \
 757         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 758
 759 #define CONFIG_HDBOOT                                   \
 760         "setenv bootargs root=/dev/$bdev rw "           \
 761         "console=$consoledev,$baudrate $othbootargs;"   \
 762         "tftp $loadaddr $bootfile;"                     \
 763         "tftp $fdtaddr $fdtfile;"                       \
 764         "bootm $loadaddr - $fdtaddr"
 765
 766 #define CONFIG_NFSBOOTCOMMAND                   \
 767         "setenv bootargs root=/dev/nfs rw "     \
 768         "nfsroot=$serverip:$rootpath "          \
 769         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 770         "console=$consoledev,$baudrate $othbootargs;"   \
 771         "tftp $loadaddr $bootfile;"             \
 772         "tftp $fdtaddr $fdtfile;"               \
 773         "bootm $loadaddr - $fdtaddr"
 774
 775 #define CONFIG_RAMBOOTCOMMAND                           \
 776         "setenv bootargs root=/dev/ram rw "             \
 777         "console=$consoledev,$baudrate $othbootargs;"   \
 778         "tftp $ramdiskaddr $ramdiskfile;"               \
 779         "tftp $loadaddr $bootfile;"                     \
 780         "tftp $fdtaddr $fdtfile;"                       \
 781         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 782
 783 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 784
 785 #include <asm/fsl_secure_boot.h>
 786
 787 #endif  /* __T208xQDS_H */