41926f76e68a920b2ab4c1de6b0dd131b291ab9a
[platform/kernel/u-boot.git] / include / configs / T208xQDS.h
1 /*
2  * Copyright 2011-2013 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 /*
8  * T2080/T2081 QDS board configuration file
9  */
10
11 #ifndef __T208xQDS_H
12 #define __T208xQDS_H
13
14 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
15 #if defined(CONFIG_ARCH_T2080)
16 #define CONFIG_FSL_SATA_V2
17 #define CONFIG_SYS_SRIO         /* Enable Serial RapidIO Support */
18 #define CONFIG_SRIO1            /* SRIO port 1 */
19 #define CONFIG_SRIO2            /* SRIO port 2 */
20 #elif defined(CONFIG_ARCH_T2081)
21 #endif
22
23 /* High Level Configuration Options */
24 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
25 #define CONFIG_MP               /* support multiple processors */
26 #define CONFIG_ENABLE_36BIT_PHYS
27
28 #ifdef CONFIG_PHYS_64BIT
29 #define CONFIG_ADDR_MAP 1
30 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
31 #endif
32
33 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
34 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
35 #define CONFIG_ENV_OVERWRITE
36
37 #ifdef CONFIG_RAMBOOT_PBL
38 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
39
40 #define CONFIG_SPL_FLUSH_IMAGE
41 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
42 #define CONFIG_SYS_TEXT_BASE            0x00201000
43 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
44 #define CONFIG_SPL_PAD_TO               0x40000
45 #define CONFIG_SPL_MAX_SIZE             0x28000
46 #define RESET_VECTOR_OFFSET             0x27FFC
47 #define BOOT_PAGE_OFFSET                0x27000
48 #ifdef CONFIG_SPL_BUILD
49 #define CONFIG_SPL_SKIP_RELOCATE
50 #define CONFIG_SPL_COMMON_INIT_DDR
51 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
52 #endif
53
54 #ifdef CONFIG_NAND
55 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
56 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
57 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
58 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
59 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
60 #if defined(CONFIG_ARCH_T2080)
61 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg
62 #elif defined(CONFIG_ARCH_T2081)
63 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg
64 #endif
65 #define CONFIG_SPL_NAND_BOOT
66 #endif
67
68 #ifdef CONFIG_SPIFLASH
69 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
70 #define CONFIG_SPL_SPI_FLASH_MINIMAL
71 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
72 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
73 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
74 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
75 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
76 #ifndef CONFIG_SPL_BUILD
77 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
78 #endif
79 #if defined(CONFIG_ARCH_T2080)
80 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg
81 #elif defined(CONFIG_ARCH_T2081)
82 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg
83 #endif
84 #define CONFIG_SPL_SPI_BOOT
85 #endif
86
87 #ifdef CONFIG_SDCARD
88 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
89 #define CONFIG_SPL_MMC_MINIMAL
90 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
91 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
92 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
93 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
94 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
95 #ifndef CONFIG_SPL_BUILD
96 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
97 #endif
98 #if defined(CONFIG_ARCH_T2080)
99 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg
100 #elif defined(CONFIG_ARCH_T2081)
101 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg
102 #endif
103 #define CONFIG_SPL_MMC_BOOT
104 #endif
105
106 #endif /* CONFIG_RAMBOOT_PBL */
107
108 #define CONFIG_SRIO_PCIE_BOOT_MASTER
109 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
110 /* Set 1M boot space */
111 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
112 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
113                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
114 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
115 #endif
116
117 #ifndef CONFIG_SYS_TEXT_BASE
118 #define CONFIG_SYS_TEXT_BASE    0xeff40000
119 #endif
120
121 #ifndef CONFIG_RESET_VECTOR_ADDRESS
122 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
123 #endif
124
125 /*
126  * These can be toggled for performance analysis, otherwise use default.
127  */
128 #define CONFIG_SYS_CACHE_STASHING
129 #define CONFIG_BTB              /* toggle branch predition */
130 #define CONFIG_DDR_ECC
131 #ifdef CONFIG_DDR_ECC
132 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
133 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
134 #endif
135
136 #ifdef CONFIG_MTD_NOR_FLASH
137 #define CONFIG_FLASH_CFI_DRIVER
138 #define CONFIG_SYS_FLASH_CFI
139 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
140 #endif
141
142 #if defined(CONFIG_SPIFLASH)
143 #define CONFIG_SYS_EXTRA_ENV_RELOC
144 #define CONFIG_ENV_SPI_BUS      0
145 #define CONFIG_ENV_SPI_CS       0
146 #define CONFIG_ENV_SPI_MAX_HZ   10000000
147 #define CONFIG_ENV_SPI_MODE     0
148 #define CONFIG_ENV_SIZE         0x2000     /* 8KB */
149 #define CONFIG_ENV_OFFSET       0x100000   /* 1MB */
150 #define CONFIG_ENV_SECT_SIZE    0x10000
151 #elif defined(CONFIG_SDCARD)
152 #define CONFIG_SYS_EXTRA_ENV_RELOC
153 #define CONFIG_SYS_MMC_ENV_DEV  0
154 #define CONFIG_ENV_SIZE         0x2000
155 #define CONFIG_ENV_OFFSET       (512 * 0x800)
156 #elif defined(CONFIG_NAND)
157 #define CONFIG_SYS_EXTRA_ENV_RELOC
158 #define CONFIG_ENV_SIZE         0x2000
159 #define CONFIG_ENV_OFFSET       (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
160 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
161 #define CONFIG_ENV_ADDR         0xffe20000
162 #define CONFIG_ENV_SIZE         0x2000
163 #elif defined(CONFIG_ENV_IS_NOWHERE)
164 #define CONFIG_ENV_SIZE         0x2000
165 #else
166 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
167 #define CONFIG_ENV_SIZE         0x2000
168 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
169 #endif
170
171 #ifndef __ASSEMBLY__
172 unsigned long get_board_sys_clk(void);
173 unsigned long get_board_ddr_clk(void);
174 #endif
175
176 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
177 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
178
179 /*
180  * Config the L3 Cache as L3 SRAM
181  */
182 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
183 #define CONFIG_SYS_L3_SIZE              (512 << 10)
184 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
185 #ifdef CONFIG_RAMBOOT_PBL
186 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
187 #endif
188 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
189 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
190 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
191 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
192
193 #define CONFIG_SYS_DCSRBAR      0xf0000000
194 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
195
196 /* EEPROM */
197 #define CONFIG_ID_EEPROM
198 #define CONFIG_SYS_I2C_EEPROM_NXID
199 #define CONFIG_SYS_EEPROM_BUS_NUM       0
200 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
201 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
202
203 /*
204  * DDR Setup
205  */
206 #define CONFIG_VERY_BIG_RAM
207 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
208 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
209 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
210 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
211 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
212 #define CONFIG_DDR_SPD
213 #define CONFIG_FSL_DDR_INTERACTIVE
214 #define CONFIG_SYS_SPD_BUS_NUM  0
215 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
216 #define SPD_EEPROM_ADDRESS1     0x51
217 #define SPD_EEPROM_ADDRESS2     0x52
218 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
219 #define CTRL_INTLV_PREFERED     cacheline
220
221 /*
222  * IFC Definitions
223  */
224 #define CONFIG_SYS_FLASH_BASE           0xe0000000
225 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
226 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
227 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
228                                 + 0x8000000) | \
229                                 CSPR_PORT_SIZE_16 | \
230                                 CSPR_MSEL_NOR | \
231                                 CSPR_V)
232 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
233 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
234                                 CSPR_PORT_SIZE_16 | \
235                                 CSPR_MSEL_NOR | \
236                                 CSPR_V)
237 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
238 /* NOR Flash Timing Params */
239 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
240
241 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
242                                 FTIM0_NOR_TEADC(0x5) | \
243                                 FTIM0_NOR_TEAHC(0x5))
244 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
245                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
246                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
247 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
248                                 FTIM2_NOR_TCH(0x4) | \
249                                 FTIM2_NOR_TWPH(0x0E) | \
250                                 FTIM2_NOR_TWP(0x1c))
251 #define CONFIG_SYS_NOR_FTIM3    0x0
252
253 #define CONFIG_SYS_FLASH_QUIET_TEST
254 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
255
256 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
257 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
258 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
259 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
260
261 #define CONFIG_SYS_FLASH_EMPTY_INFO
262 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
263                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
264
265 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
266 #define QIXIS_BASE                      0xffdf0000
267 #define QIXIS_LBMAP_SWITCH              6
268 #define QIXIS_LBMAP_MASK                0x0f
269 #define QIXIS_LBMAP_SHIFT               0
270 #define QIXIS_LBMAP_DFLTBANK            0x00
271 #define QIXIS_LBMAP_ALTBANK             0x04
272 #define QIXIS_LBMAP_NAND                0x09
273 #define QIXIS_LBMAP_SD                  0x00
274 #define QIXIS_RCW_SRC_NAND              0x104
275 #define QIXIS_RCW_SRC_SD                0x040
276 #define QIXIS_RST_CTL_RESET             0x83
277 #define QIXIS_RST_FORCE_MEM             0x1
278 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
279 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
280 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
281 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
282
283 #define CONFIG_SYS_CSPR3_EXT    (0xf)
284 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
285                                 | CSPR_PORT_SIZE_8 \
286                                 | CSPR_MSEL_GPCM \
287                                 | CSPR_V)
288 #define CONFIG_SYS_AMASK3       IFC_AMASK(4*1024)
289 #define CONFIG_SYS_CSOR3        0x0
290 /* QIXIS Timing parameters for IFC CS3 */
291 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
292                                         FTIM0_GPCM_TEADC(0x0e) | \
293                                         FTIM0_GPCM_TEAHC(0x0e))
294 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
295                                         FTIM1_GPCM_TRAD(0x3f))
296 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
297                                         FTIM2_GPCM_TCH(0x8) | \
298                                         FTIM2_GPCM_TWP(0x1f))
299 #define CONFIG_SYS_CS3_FTIM3            0x0
300
301 /* NAND Flash on IFC */
302 #define CONFIG_NAND_FSL_IFC
303 #define CONFIG_SYS_NAND_BASE            0xff800000
304 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
305
306 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
307 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
308                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
309                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
310                                 | CSPR_V)
311 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
312
313 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
314                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
315                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
316                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
317                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
318                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
319                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
320
321 #define CONFIG_SYS_NAND_ONFI_DETECTION
322
323 /* ONFI NAND Flash mode0 Timing Params */
324 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
325                                         FTIM0_NAND_TWP(0x18)    | \
326                                         FTIM0_NAND_TWCHT(0x07)  | \
327                                         FTIM0_NAND_TWH(0x0a))
328 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
329                                         FTIM1_NAND_TWBE(0x39)   | \
330                                         FTIM1_NAND_TRR(0x0e)    | \
331                                         FTIM1_NAND_TRP(0x18))
332 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
333                                         FTIM2_NAND_TREH(0x0a)   | \
334                                         FTIM2_NAND_TWHRE(0x1e))
335 #define CONFIG_SYS_NAND_FTIM3           0x0
336
337 #define CONFIG_SYS_NAND_DDR_LAW         11
338 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
339 #define CONFIG_SYS_MAX_NAND_DEVICE      1
340 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
341
342 #if defined(CONFIG_NAND)
343 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
344 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
345 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
346 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
347 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
348 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
349 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
350 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
351 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
352 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
353 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
354 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
355 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
356 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
357 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
358 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
359 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
360 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
361 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
362 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
363 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
364 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
365 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
366 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
367 #else
368 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
369 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
370 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
371 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
372 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
373 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
374 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
375 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
376 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
377 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
378 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
379 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
380 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
381 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
382 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
383 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
384 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
385 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
386 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
387 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
388 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
389 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
390 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
391 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
392 #endif
393
394 #if defined(CONFIG_RAMBOOT_PBL)
395 #define CONFIG_SYS_RAMBOOT
396 #endif
397
398 #ifdef CONFIG_SPL_BUILD
399 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
400 #else
401 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
402 #endif
403
404 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
405 #define CONFIG_MISC_INIT_R
406 #define CONFIG_HWCONFIG
407
408 /* define to use L1 as initial stack */
409 #define CONFIG_L1_INIT_RAM
410 #define CONFIG_SYS_INIT_RAM_LOCK
411 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
412 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
413 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
414 /* The assembler doesn't like typecast */
415 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
416                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
417                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
418 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
419 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
420                                                 GENERATED_GBL_DATA_SIZE)
421 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
422 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
423 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
424
425 /*
426  * Serial Port
427  */
428 #define CONFIG_CONS_INDEX               1
429 #define CONFIG_SYS_NS16550_SERIAL
430 #define CONFIG_SYS_NS16550_REG_SIZE     1
431 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
432 #define CONFIG_SYS_BAUDRATE_TABLE       \
433         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
434 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
435 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
436 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
437 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
438
439 /*
440  * I2C
441  */
442 #define CONFIG_SYS_I2C
443 #define CONFIG_SYS_I2C_FSL
444 #define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
445 #define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
446 #define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
447 #define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
448 #define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
449 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
450 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
451 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
452 #define CONFIG_SYS_FSL_I2C_SPEED   100000
453 #define CONFIG_SYS_FSL_I2C2_SPEED  100000
454 #define CONFIG_SYS_FSL_I2C3_SPEED  100000
455 #define CONFIG_SYS_FSL_I2C4_SPEED  100000
456 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
457 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
458 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
459 #define I2C_MUX_CH_DEFAULT      0x8
460
461 #define I2C_MUX_CH_VOL_MONITOR 0xa
462
463 /* Voltage monitor on channel 2*/
464 #define I2C_VOL_MONITOR_ADDR           0x40
465 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
466 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
467 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
468
469 #define CONFIG_VID_FLS_ENV              "t208xqds_vdd_mv"
470 #ifndef CONFIG_SPL_BUILD
471 #define CONFIG_VID
472 #endif
473 #define CONFIG_VOL_MONITOR_IR36021_SET
474 #define CONFIG_VOL_MONITOR_IR36021_READ
475 /* The lowest and highest voltage allowed for T208xQDS */
476 #define VDD_MV_MIN                      819
477 #define VDD_MV_MAX                      1212
478
479 /*
480  * RapidIO
481  */
482 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
483 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
484 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
485 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
486 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
487 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
488 /*
489  * for slave u-boot IMAGE instored in master memory space,
490  * PHYS must be aligned based on the SIZE
491  */
492 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
493 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
494 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
495 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
496 /*
497  * for slave UCODE and ENV instored in master memory space,
498  * PHYS must be aligned based on the SIZE
499  */
500 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
501 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
502 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
503
504 /* slave core release by master*/
505 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
506 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
507
508 /*
509  * SRIO_PCIE_BOOT - SLAVE
510  */
511 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
512 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
513 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
514                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
515 #endif
516
517 /*
518  * eSPI - Enhanced SPI
519  */
520 #ifdef CONFIG_SPI_FLASH
521 #ifndef CONFIG_SPL_BUILD
522 #endif
523
524 #define CONFIG_SPI_FLASH_BAR
525 #define CONFIG_SF_DEFAULT_SPEED  10000000
526 #define CONFIG_SF_DEFAULT_MODE    0
527 #endif
528
529 /*
530  * General PCI
531  * Memory space is mapped 1-1, but I/O space must start from 0.
532  */
533 #define CONFIG_PCIE1            /* PCIE controller 1 */
534 #define CONFIG_PCIE2            /* PCIE controller 2 */
535 #define CONFIG_PCIE3            /* PCIE controller 3 */
536 #define CONFIG_PCIE4            /* PCIE controller 4 */
537 #define CONFIG_FSL_PCIE_RESET
538 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
539 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
540 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
541 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
542 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
543 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
544 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
545 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
546 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
547 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
548 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
549
550 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
551 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
552 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
553 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
554 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000 /* 256M */
555 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
556 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
557 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
558 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
559
560 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
561 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
562 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
563 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
564 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
565 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
566 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
567 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
568 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
569
570 /* controller 4, Base address 203000 */
571 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
572 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
573 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
574 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
575 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
576 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
577 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
578
579 #ifdef CONFIG_PCI
580 #define CONFIG_PCI_INDIRECT_BRIDGE
581 #define CONFIG_FSL_PCIE_RESET      /* need PCIe reset errata */
582 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
583 #endif
584
585 /* Qman/Bman */
586 #ifndef CONFIG_NOBQFMAN
587 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
588 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
589 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
590 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
591 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
592 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
593 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
594 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
595 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
596 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
597                                         CONFIG_SYS_BMAN_CENA_SIZE)
598 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
599 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
600 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
601 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
602 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
603 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
604 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
605 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
606 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
607 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
608 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
609                                         CONFIG_SYS_QMAN_CENA_SIZE)
610 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
611 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
612
613 #define CONFIG_SYS_DPAA_FMAN
614 #define CONFIG_SYS_DPAA_PME
615 #define CONFIG_SYS_PMAN
616 #define CONFIG_SYS_DPAA_DCE
617 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
618 #define CONFIG_SYS_INTERLAKEN
619
620 /* Default address of microcode for the Linux Fman driver */
621 #if defined(CONFIG_SPIFLASH)
622 /*
623  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
624  * env, so we got 0x110000.
625  */
626 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
627 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
628 #elif defined(CONFIG_SDCARD)
629 /*
630  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
631  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
632  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
633  */
634 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
635 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
636 #elif defined(CONFIG_NAND)
637 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
638 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
639 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
640 /*
641  * Slave has no ucode locally, it can fetch this from remote. When implementing
642  * in two corenet boards, slave's ucode could be stored in master's memory
643  * space, the address can be mapped from slave TLB->slave LAW->
644  * slave SRIO or PCIE outbound window->master inbound window->
645  * master LAW->the ucode address in master's memory space.
646  */
647 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
648 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
649 #else
650 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
651 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
652 #endif
653 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
654 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
655 #endif /* CONFIG_NOBQFMAN */
656
657 #ifdef CONFIG_SYS_DPAA_FMAN
658 #define CONFIG_FMAN_ENET
659 #define CONFIG_PHYLIB_10G
660 #define CONFIG_PHY_VITESSE
661 #define CONFIG_PHY_REALTEK
662 #define CONFIG_PHY_TERANETICS
663 #define RGMII_PHY1_ADDR 0x1
664 #define RGMII_PHY2_ADDR 0x2
665 #define FM1_10GEC1_PHY_ADDR       0x3
666 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
667 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
668 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
669 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
670 #endif
671
672 #ifdef CONFIG_FMAN_ENET
673 #define CONFIG_MII              /* MII PHY management */
674 #define CONFIG_ETHPRIME         "FM1@DTSEC3"
675 #endif
676
677 /*
678  * SATA
679  */
680 #ifdef CONFIG_FSL_SATA_V2
681 #define CONFIG_LIBATA
682 #define CONFIG_FSL_SATA
683 #define CONFIG_SYS_SATA_MAX_DEVICE      2
684 #define CONFIG_SATA1
685 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
686 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
687 #define CONFIG_SATA2
688 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
689 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
690 #define CONFIG_LBA48
691 #endif
692
693 /*
694  * USB
695  */
696 #ifdef CONFIG_USB_EHCI_HCD
697 #define CONFIG_USB_EHCI_FSL
698 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
699 #define CONFIG_HAS_FSL_DR_USB
700 #endif
701
702 /*
703  * SDHC
704  */
705 #ifdef CONFIG_MMC
706 #define CONFIG_FSL_ESDHC
707 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
708 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
709 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
710 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
711 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT
712 #endif
713
714 /*
715  * Dynamic MTD Partition support with mtdparts
716  */
717 #ifdef CONFIG_MTD_NOR_FLASH
718 #define CONFIG_MTD_DEVICE
719 #define CONFIG_MTD_PARTITIONS
720 #define CONFIG_FLASH_CFI_MTD
721 #endif
722
723 /*
724  * Environment
725  */
726 #define CONFIG_LOADS_ECHO       /* echo on for serial download */
727 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
728
729 /*
730  * Miscellaneous configurable options
731  */
732 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
733 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
734 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support */
735 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
736
737 /*
738  * For booting Linux, the board info and command line data
739  * have to be in the first 64 MB of memory, since this is
740  * the maximum mapped by the Linux kernel during initialization.
741  */
742 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
743 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
744
745 #ifdef CONFIG_CMD_KGDB
746 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
747 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
748 #endif
749
750 /*
751  * Environment Configuration
752  */
753 #define CONFIG_ROOTPATH  "/opt/nfsroot"
754 #define CONFIG_BOOTFILE  "uImage"
755 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
756
757 /* default location for tftp and bootm */
758 #define CONFIG_LOADADDR         1000000
759 #define __USB_PHY_TYPE          utmi
760
761 #define CONFIG_EXTRA_ENV_SETTINGS                               \
762         "hwconfig=fsl_ddr:"                                     \
763         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
764         "bank_intlv=auto;"                                      \
765         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
766         "netdev=eth0\0"                                         \
767         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
768         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
769         "tftpflash=tftpboot $loadaddr $uboot && "               \
770         "protect off $ubootaddr +$filesize && "                 \
771         "erase $ubootaddr +$filesize && "                       \
772         "cp.b $loadaddr $ubootaddr $filesize && "               \
773         "protect on $ubootaddr +$filesize && "                  \
774         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
775         "consoledev=ttyS0\0"                                    \
776         "ramdiskaddr=2000000\0"                                 \
777         "ramdiskfile=t2080qds/ramdisk.uboot\0"                  \
778         "fdtaddr=1e00000\0"                                     \
779         "fdtfile=t2080qds/t2080qds.dtb\0"                       \
780         "bdev=sda3\0"
781
782 /*
783  * For emulation this causes u-boot to jump to the start of the
784  * proof point app code automatically
785  */
786 #define CONFIG_PROOF_POINTS                             \
787         "setenv bootargs root=/dev/$bdev rw "           \
788         "console=$consoledev,$baudrate $othbootargs;"   \
789         "cpu 1 release 0x29000000 - - -;"               \
790         "cpu 2 release 0x29000000 - - -;"               \
791         "cpu 3 release 0x29000000 - - -;"               \
792         "cpu 4 release 0x29000000 - - -;"               \
793         "cpu 5 release 0x29000000 - - -;"               \
794         "cpu 6 release 0x29000000 - - -;"               \
795         "cpu 7 release 0x29000000 - - -;"               \
796         "go 0x29000000"
797
798 #define CONFIG_HVBOOT                           \
799         "setenv bootargs config-addr=0x60000000; "      \
800         "bootm 0x01000000 - 0x00f00000"
801
802 #define CONFIG_ALU                              \
803         "setenv bootargs root=/dev/$bdev rw "           \
804         "console=$consoledev,$baudrate $othbootargs;"   \
805         "cpu 1 release 0x01000000 - - -;"               \
806         "cpu 2 release 0x01000000 - - -;"               \
807         "cpu 3 release 0x01000000 - - -;"               \
808         "cpu 4 release 0x01000000 - - -;"               \
809         "cpu 5 release 0x01000000 - - -;"               \
810         "cpu 6 release 0x01000000 - - -;"               \
811         "cpu 7 release 0x01000000 - - -;"               \
812         "go 0x01000000"
813
814 #define CONFIG_LINUX                            \
815         "setenv bootargs root=/dev/ram rw "             \
816         "console=$consoledev,$baudrate $othbootargs;"   \
817         "setenv ramdiskaddr 0x02000000;"                \
818         "setenv fdtaddr 0x00c00000;"                    \
819         "setenv loadaddr 0x1000000;"                    \
820         "bootm $loadaddr $ramdiskaddr $fdtaddr"
821
822 #define CONFIG_HDBOOT                                   \
823         "setenv bootargs root=/dev/$bdev rw "           \
824         "console=$consoledev,$baudrate $othbootargs;"   \
825         "tftp $loadaddr $bootfile;"                     \
826         "tftp $fdtaddr $fdtfile;"                       \
827         "bootm $loadaddr - $fdtaddr"
828
829 #define CONFIG_NFSBOOTCOMMAND                   \
830         "setenv bootargs root=/dev/nfs rw "     \
831         "nfsroot=$serverip:$rootpath "          \
832         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
833         "console=$consoledev,$baudrate $othbootargs;"   \
834         "tftp $loadaddr $bootfile;"             \
835         "tftp $fdtaddr $fdtfile;"               \
836         "bootm $loadaddr - $fdtaddr"
837
838 #define CONFIG_RAMBOOTCOMMAND                           \
839         "setenv bootargs root=/dev/ram rw "             \
840         "console=$consoledev,$baudrate $othbootargs;"   \
841         "tftp $ramdiskaddr $ramdiskfile;"               \
842         "tftp $loadaddr $bootfile;"                     \
843         "tftp $fdtaddr $fdtfile;"                       \
844         "bootm $loadaddr $ramdiskaddr $fdtaddr"
845
846 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
847
848 #include <asm/fsl_secure_boot.h>
849
850 #endif  /* __T208xQDS_H */