1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2011-2013 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
8 * T2080/T2081 QDS board configuration file
14 #include <linux/stringify.h>
16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
17 #if defined(CONFIG_ARCH_T2080)
18 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
19 #define CONFIG_SRIO1 /* SRIO port 1 */
20 #define CONFIG_SRIO2 /* SRIO port 2 */
23 /* High Level Configuration Options */
25 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
26 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
28 #ifdef CONFIG_RAMBOOT_PBL
29 #define RESET_VECTOR_OFFSET 0x27FFC
30 #define BOOT_PAGE_OFFSET 0x27000
32 #ifdef CONFIG_MTD_RAW_NAND
33 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
34 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
35 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
38 #ifdef CONFIG_SPIFLASH
39 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
40 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
41 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
42 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
43 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
47 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
48 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
49 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
50 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
51 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
54 #endif /* CONFIG_RAMBOOT_PBL */
56 #define CONFIG_SRIO_PCIE_BOOT_MASTER
57 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
58 /* Set 1M boot space */
59 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
60 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
61 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
62 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
65 #ifndef CONFIG_RESET_VECTOR_ADDRESS
66 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
70 * These can be toggled for performance analysis, otherwise use default.
72 #define CONFIG_SYS_CACHE_STASHING
74 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
78 * Config the L3 Cache as L3 SRAM
80 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
81 #define CONFIG_SYS_L3_SIZE (512 << 10)
82 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
84 #define CONFIG_SYS_DCSRBAR 0xf0000000
85 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
88 #define CONFIG_SYS_I2C_EEPROM_NXID
89 #define CONFIG_SYS_EEPROM_BUS_NUM 0
94 #define CONFIG_VERY_BIG_RAM
95 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
96 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
97 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
98 #define SPD_EEPROM_ADDRESS1 0x51
99 #define SPD_EEPROM_ADDRESS2 0x52
100 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
101 #define CTRL_INTLV_PREFERED cacheline
106 #define CONFIG_SYS_FLASH_BASE 0xe0000000
107 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
108 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
109 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
111 CSPR_PORT_SIZE_16 | \
114 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
115 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
116 CSPR_PORT_SIZE_16 | \
119 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
120 /* NOR Flash Timing Params */
121 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
123 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
124 FTIM0_NOR_TEADC(0x5) | \
125 FTIM0_NOR_TEAHC(0x5))
126 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
127 FTIM1_NOR_TRAD_NOR(0x1A) |\
128 FTIM1_NOR_TSEQRAD_NOR(0x13))
129 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
130 FTIM2_NOR_TCH(0x4) | \
131 FTIM2_NOR_TWPH(0x0E) | \
133 #define CONFIG_SYS_NOR_FTIM3 0x0
135 #define CONFIG_SYS_FLASH_QUIET_TEST
136 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
138 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
139 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
140 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
142 #define CONFIG_SYS_FLASH_EMPTY_INFO
143 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
144 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
146 #define QIXIS_BASE 0xffdf0000
147 #define QIXIS_LBMAP_SWITCH 6
148 #define QIXIS_LBMAP_MASK 0x0f
149 #define QIXIS_LBMAP_SHIFT 0
150 #define QIXIS_LBMAP_DFLTBANK 0x00
151 #define QIXIS_LBMAP_ALTBANK 0x04
152 #define QIXIS_LBMAP_NAND 0x09
153 #define QIXIS_LBMAP_SD 0x00
154 #define QIXIS_RCW_SRC_NAND 0x104
155 #define QIXIS_RCW_SRC_SD 0x040
156 #define QIXIS_RST_CTL_RESET 0x83
157 #define QIXIS_RST_FORCE_MEM 0x1
158 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
159 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
160 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
161 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
163 #define CONFIG_SYS_CSPR3_EXT (0xf)
164 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
168 #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
169 #define CONFIG_SYS_CSOR3 0x0
170 /* QIXIS Timing parameters for IFC CS3 */
171 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
172 FTIM0_GPCM_TEADC(0x0e) | \
173 FTIM0_GPCM_TEAHC(0x0e))
174 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
175 FTIM1_GPCM_TRAD(0x3f))
176 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
177 FTIM2_GPCM_TCH(0x8) | \
178 FTIM2_GPCM_TWP(0x1f))
179 #define CONFIG_SYS_CS3_FTIM3 0x0
181 /* NAND Flash on IFC */
182 #define CONFIG_SYS_NAND_BASE 0xff800000
183 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
185 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
186 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
187 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
188 | CSPR_MSEL_NAND /* MSEL = NAND */ \
190 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
192 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
193 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
194 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
195 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
196 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
197 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
198 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
200 /* ONFI NAND Flash mode0 Timing Params */
201 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
202 FTIM0_NAND_TWP(0x18) | \
203 FTIM0_NAND_TWCHT(0x07) | \
204 FTIM0_NAND_TWH(0x0a))
205 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
206 FTIM1_NAND_TWBE(0x39) | \
207 FTIM1_NAND_TRR(0x0e) | \
208 FTIM1_NAND_TRP(0x18))
209 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
210 FTIM2_NAND_TREH(0x0a) | \
211 FTIM2_NAND_TWHRE(0x1e))
212 #define CONFIG_SYS_NAND_FTIM3 0x0
214 #define CONFIG_SYS_NAND_DDR_LAW 11
215 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
216 #define CONFIG_SYS_MAX_NAND_DEVICE 1
218 #if defined(CONFIG_MTD_RAW_NAND)
219 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
220 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
221 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
222 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
223 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
224 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
225 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
226 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
227 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
228 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
229 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
230 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
231 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
232 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
233 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
234 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
235 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
236 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
237 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
238 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
239 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
240 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
241 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
242 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
244 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
245 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
246 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
247 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
248 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
249 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
250 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
251 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
252 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
253 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
254 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
255 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
256 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
257 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
258 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
259 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
260 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
261 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
262 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
263 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
264 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
265 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
266 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
267 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
270 #define CONFIG_HWCONFIG
272 /* define to use L1 as initial stack */
273 #define CONFIG_L1_INIT_RAM
274 #define CONFIG_SYS_INIT_RAM_LOCK
275 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
276 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
277 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
278 /* The assembler doesn't like typecast */
279 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
280 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
281 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
282 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
283 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
284 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
289 #define CONFIG_SYS_NS16550_SERIAL
290 #define CONFIG_SYS_NS16550_REG_SIZE 1
291 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
292 #define CONFIG_SYS_BAUDRATE_TABLE \
293 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
294 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
295 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
296 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
297 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
303 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
304 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
305 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
306 #define I2C_MUX_CH_DEFAULT 0x8
308 #define I2C_MUX_CH_VOL_MONITOR 0xa
310 /* Voltage monitor on channel 2*/
311 #define I2C_VOL_MONITOR_ADDR 0x40
312 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
313 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
314 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
316 /* The lowest and highest voltage allowed for T208xQDS */
317 #define VDD_MV_MIN 819
318 #define VDD_MV_MAX 1212
323 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
324 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
325 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
326 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
327 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
328 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
330 * for slave u-boot IMAGE instored in master memory space,
331 * PHYS must be aligned based on the SIZE
333 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
334 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
335 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
336 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
338 * for slave UCODE and ENV instored in master memory space,
339 * PHYS must be aligned based on the SIZE
341 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
342 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
343 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
345 /* slave core release by master*/
346 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
347 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
350 * SRIO_PCIE_BOOT - SLAVE
352 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
353 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
354 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
355 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
359 * eSPI - Enhanced SPI
364 * Memory space is mapped 1-1, but I/O space must start from 0.
366 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
367 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
368 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
369 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
370 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
372 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
373 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
374 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
375 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
376 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
378 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
379 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
380 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
381 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
382 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
384 /* controller 4, Base address 203000 */
385 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
386 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
387 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
390 #ifndef CONFIG_NOBQFMAN
391 #define CONFIG_SYS_BMAN_NUM_PORTALS 18
392 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
393 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
394 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
395 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
396 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
397 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
398 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
399 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
400 CONFIG_SYS_BMAN_CENA_SIZE)
401 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
402 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
403 #define CONFIG_SYS_QMAN_NUM_PORTALS 18
404 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
405 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
406 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
407 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
408 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
409 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
410 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
411 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
412 CONFIG_SYS_QMAN_CENA_SIZE)
413 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
414 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
416 #define CONFIG_SYS_DPAA_FMAN
417 #define CONFIG_SYS_DPAA_PME
418 #define CONFIG_SYS_PMAN
419 #define CONFIG_SYS_DPAA_DCE
420 #define CONFIG_SYS_DPAA_RMAN /* RMan */
421 #define CONFIG_SYS_INTERLAKEN
423 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
424 #endif /* CONFIG_NOBQFMAN */
426 #ifdef CONFIG_SYS_DPAA_FMAN
427 #define RGMII_PHY1_ADDR 0x1
428 #define RGMII_PHY2_ADDR 0x2
429 #define FM1_10GEC1_PHY_ADDR 0x3
430 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
431 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
432 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
433 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
444 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
445 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
449 * Dynamic MTD Partition support with mtdparts
455 #define CONFIG_LOADS_ECHO /* echo on for serial download */
456 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
459 * Miscellaneous configurable options
463 * For booting Linux, the board info and command line data
464 * have to be in the first 64 MB of memory, since this is
465 * the maximum mapped by the Linux kernel during initialization.
467 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
468 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
471 * Environment Configuration
473 #define CONFIG_ROOTPATH "/opt/nfsroot"
474 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
476 #define __USB_PHY_TYPE utmi
478 #define CONFIG_EXTRA_ENV_SETTINGS \
479 "hwconfig=fsl_ddr:" \
480 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
482 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
484 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
485 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
486 "tftpflash=tftpboot $loadaddr $uboot && " \
487 "protect off $ubootaddr +$filesize && " \
488 "erase $ubootaddr +$filesize && " \
489 "cp.b $loadaddr $ubootaddr $filesize && " \
490 "protect on $ubootaddr +$filesize && " \
491 "cmp.b $loadaddr $ubootaddr $filesize\0" \
492 "consoledev=ttyS0\0" \
493 "ramdiskaddr=2000000\0" \
494 "ramdiskfile=t2080qds/ramdisk.uboot\0" \
495 "fdtaddr=1e00000\0" \
496 "fdtfile=t2080qds/t2080qds.dtb\0" \
500 * For emulation this causes u-boot to jump to the start of the
501 * proof point app code automatically
503 #define PROOF_POINTS \
504 "setenv bootargs root=/dev/$bdev rw " \
505 "console=$consoledev,$baudrate $othbootargs;" \
506 "cpu 1 release 0x29000000 - - -;" \
507 "cpu 2 release 0x29000000 - - -;" \
508 "cpu 3 release 0x29000000 - - -;" \
509 "cpu 4 release 0x29000000 - - -;" \
510 "cpu 5 release 0x29000000 - - -;" \
511 "cpu 6 release 0x29000000 - - -;" \
512 "cpu 7 release 0x29000000 - - -;" \
516 "setenv bootargs config-addr=0x60000000; " \
517 "bootm 0x01000000 - 0x00f00000"
520 "setenv bootargs root=/dev/$bdev rw " \
521 "console=$consoledev,$baudrate $othbootargs;" \
522 "cpu 1 release 0x01000000 - - -;" \
523 "cpu 2 release 0x01000000 - - -;" \
524 "cpu 3 release 0x01000000 - - -;" \
525 "cpu 4 release 0x01000000 - - -;" \
526 "cpu 5 release 0x01000000 - - -;" \
527 "cpu 6 release 0x01000000 - - -;" \
528 "cpu 7 release 0x01000000 - - -;" \
531 #include <asm/fsl_secure_boot.h>
533 #endif /* __T208xQDS_H */