1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2011-2013 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
8 * T2080/T2081 QDS board configuration file
14 #include <linux/stringify.h>
16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
17 #if defined(CONFIG_ARCH_T2080)
18 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
19 #define CONFIG_SRIO1 /* SRIO port 1 */
20 #define CONFIG_SRIO2 /* SRIO port 2 */
23 /* High Level Configuration Options */
24 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
25 #define CONFIG_ENABLE_36BIT_PHYS
27 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
28 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
30 #ifdef CONFIG_RAMBOOT_PBL
31 #define RESET_VECTOR_OFFSET 0x27FFC
32 #define BOOT_PAGE_OFFSET 0x27000
34 #ifdef CONFIG_MTD_RAW_NAND
35 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
36 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
37 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
40 #ifdef CONFIG_SPIFLASH
41 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
42 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
43 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
44 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
45 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
49 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
50 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
51 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
52 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
53 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
56 #endif /* CONFIG_RAMBOOT_PBL */
58 #define CONFIG_SRIO_PCIE_BOOT_MASTER
59 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
60 /* Set 1M boot space */
61 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
62 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
63 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
64 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
67 #ifndef CONFIG_RESET_VECTOR_ADDRESS
68 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
72 * These can be toggled for performance analysis, otherwise use default.
74 #define CONFIG_SYS_CACHE_STASHING
76 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
80 * Config the L3 Cache as L3 SRAM
82 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
83 #define CONFIG_SYS_L3_SIZE (512 << 10)
84 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
86 #define CONFIG_SYS_DCSRBAR 0xf0000000
87 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
90 #define CONFIG_SYS_I2C_EEPROM_NXID
91 #define CONFIG_SYS_EEPROM_BUS_NUM 0
96 #define CONFIG_VERY_BIG_RAM
97 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
98 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
99 #define CONFIG_SYS_SPD_BUS_NUM 0
100 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
101 #define SPD_EEPROM_ADDRESS1 0x51
102 #define SPD_EEPROM_ADDRESS2 0x52
103 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
104 #define CTRL_INTLV_PREFERED cacheline
109 #define CONFIG_SYS_FLASH_BASE 0xe0000000
110 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
111 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
112 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
114 CSPR_PORT_SIZE_16 | \
117 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
118 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
119 CSPR_PORT_SIZE_16 | \
122 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
123 /* NOR Flash Timing Params */
124 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
126 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
127 FTIM0_NOR_TEADC(0x5) | \
128 FTIM0_NOR_TEAHC(0x5))
129 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
130 FTIM1_NOR_TRAD_NOR(0x1A) |\
131 FTIM1_NOR_TSEQRAD_NOR(0x13))
132 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
133 FTIM2_NOR_TCH(0x4) | \
134 FTIM2_NOR_TWPH(0x0E) | \
136 #define CONFIG_SYS_NOR_FTIM3 0x0
138 #define CONFIG_SYS_FLASH_QUIET_TEST
139 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
141 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
142 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
143 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
145 #define CONFIG_SYS_FLASH_EMPTY_INFO
146 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
147 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
149 #define QIXIS_BASE 0xffdf0000
150 #define QIXIS_LBMAP_SWITCH 6
151 #define QIXIS_LBMAP_MASK 0x0f
152 #define QIXIS_LBMAP_SHIFT 0
153 #define QIXIS_LBMAP_DFLTBANK 0x00
154 #define QIXIS_LBMAP_ALTBANK 0x04
155 #define QIXIS_LBMAP_NAND 0x09
156 #define QIXIS_LBMAP_SD 0x00
157 #define QIXIS_RCW_SRC_NAND 0x104
158 #define QIXIS_RCW_SRC_SD 0x040
159 #define QIXIS_RST_CTL_RESET 0x83
160 #define QIXIS_RST_FORCE_MEM 0x1
161 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
162 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
163 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
164 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
166 #define CONFIG_SYS_CSPR3_EXT (0xf)
167 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
171 #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
172 #define CONFIG_SYS_CSOR3 0x0
173 /* QIXIS Timing parameters for IFC CS3 */
174 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
175 FTIM0_GPCM_TEADC(0x0e) | \
176 FTIM0_GPCM_TEAHC(0x0e))
177 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
178 FTIM1_GPCM_TRAD(0x3f))
179 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
180 FTIM2_GPCM_TCH(0x8) | \
181 FTIM2_GPCM_TWP(0x1f))
182 #define CONFIG_SYS_CS3_FTIM3 0x0
184 /* NAND Flash on IFC */
185 #define CONFIG_SYS_NAND_BASE 0xff800000
186 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
188 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
189 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
190 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
191 | CSPR_MSEL_NAND /* MSEL = NAND */ \
193 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
195 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
196 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
197 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
198 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
199 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
200 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
201 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
203 /* ONFI NAND Flash mode0 Timing Params */
204 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
205 FTIM0_NAND_TWP(0x18) | \
206 FTIM0_NAND_TWCHT(0x07) | \
207 FTIM0_NAND_TWH(0x0a))
208 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
209 FTIM1_NAND_TWBE(0x39) | \
210 FTIM1_NAND_TRR(0x0e) | \
211 FTIM1_NAND_TRP(0x18))
212 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
213 FTIM2_NAND_TREH(0x0a) | \
214 FTIM2_NAND_TWHRE(0x1e))
215 #define CONFIG_SYS_NAND_FTIM3 0x0
217 #define CONFIG_SYS_NAND_DDR_LAW 11
218 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
219 #define CONFIG_SYS_MAX_NAND_DEVICE 1
221 #if defined(CONFIG_MTD_RAW_NAND)
222 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
223 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
224 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
225 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
226 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
227 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
228 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
229 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
230 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
231 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
232 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
233 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
234 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
235 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
236 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
237 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
238 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
239 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
240 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
241 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
242 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
243 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
244 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
245 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
247 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
248 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
249 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
250 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
251 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
252 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
253 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
254 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
255 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
256 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
257 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
258 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
259 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
260 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
261 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
262 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
263 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
264 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
265 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
266 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
267 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
268 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
269 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
270 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
273 #if defined(CONFIG_RAMBOOT_PBL)
274 #define CONFIG_SYS_RAMBOOT
277 #define CONFIG_HWCONFIG
279 /* define to use L1 as initial stack */
280 #define CONFIG_L1_INIT_RAM
281 #define CONFIG_SYS_INIT_RAM_LOCK
282 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
283 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
284 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
285 /* The assembler doesn't like typecast */
286 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
287 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
288 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
289 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
290 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
291 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
296 #define CONFIG_SYS_NS16550_SERIAL
297 #define CONFIG_SYS_NS16550_REG_SIZE 1
298 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
299 #define CONFIG_SYS_BAUDRATE_TABLE \
300 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
301 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
302 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
303 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
304 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
310 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
311 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
312 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
313 #define I2C_MUX_CH_DEFAULT 0x8
315 #define I2C_MUX_CH_VOL_MONITOR 0xa
317 /* Voltage monitor on channel 2*/
318 #define I2C_VOL_MONITOR_ADDR 0x40
319 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
320 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
321 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
323 /* The lowest and highest voltage allowed for T208xQDS */
324 #define VDD_MV_MIN 819
325 #define VDD_MV_MAX 1212
330 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
331 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
332 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
333 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
334 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
335 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
337 * for slave u-boot IMAGE instored in master memory space,
338 * PHYS must be aligned based on the SIZE
340 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
341 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
342 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
343 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
345 * for slave UCODE and ENV instored in master memory space,
346 * PHYS must be aligned based on the SIZE
348 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
349 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
350 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
352 /* slave core release by master*/
353 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
354 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
357 * SRIO_PCIE_BOOT - SLAVE
359 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
360 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
361 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
362 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
366 * eSPI - Enhanced SPI
371 * Memory space is mapped 1-1, but I/O space must start from 0.
373 #define CONFIG_PCIE1 /* PCIE controller 1 */
374 #define CONFIG_PCIE2 /* PCIE controller 2 */
375 #define CONFIG_PCIE3 /* PCIE controller 3 */
376 #define CONFIG_PCIE4 /* PCIE controller 4 */
377 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
378 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
379 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
380 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
381 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
383 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
384 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
385 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
386 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
387 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
389 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
390 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
391 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
392 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
393 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
395 /* controller 4, Base address 203000 */
396 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
397 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
398 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
401 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
405 #ifndef CONFIG_NOBQFMAN
406 #define CONFIG_SYS_BMAN_NUM_PORTALS 18
407 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
408 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
409 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
410 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
411 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
412 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
413 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
414 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
415 CONFIG_SYS_BMAN_CENA_SIZE)
416 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
417 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
418 #define CONFIG_SYS_QMAN_NUM_PORTALS 18
419 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
420 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
421 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
422 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
423 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
424 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
425 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
426 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
427 CONFIG_SYS_QMAN_CENA_SIZE)
428 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
429 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
431 #define CONFIG_SYS_DPAA_FMAN
432 #define CONFIG_SYS_DPAA_PME
433 #define CONFIG_SYS_PMAN
434 #define CONFIG_SYS_DPAA_DCE
435 #define CONFIG_SYS_DPAA_RMAN /* RMan */
436 #define CONFIG_SYS_INTERLAKEN
438 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
439 #endif /* CONFIG_NOBQFMAN */
441 #ifdef CONFIG_SYS_DPAA_FMAN
442 #define RGMII_PHY1_ADDR 0x1
443 #define RGMII_PHY2_ADDR 0x2
444 #define FM1_10GEC1_PHY_ADDR 0x3
445 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
446 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
447 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
448 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
459 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
460 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
464 * Dynamic MTD Partition support with mtdparts
470 #define CONFIG_LOADS_ECHO /* echo on for serial download */
471 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
474 * Miscellaneous configurable options
478 * For booting Linux, the board info and command line data
479 * have to be in the first 64 MB of memory, since this is
480 * the maximum mapped by the Linux kernel during initialization.
482 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
483 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
486 * Environment Configuration
488 #define CONFIG_ROOTPATH "/opt/nfsroot"
489 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
491 #define __USB_PHY_TYPE utmi
493 #define CONFIG_EXTRA_ENV_SETTINGS \
494 "hwconfig=fsl_ddr:" \
495 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
497 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
499 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
500 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
501 "tftpflash=tftpboot $loadaddr $uboot && " \
502 "protect off $ubootaddr +$filesize && " \
503 "erase $ubootaddr +$filesize && " \
504 "cp.b $loadaddr $ubootaddr $filesize && " \
505 "protect on $ubootaddr +$filesize && " \
506 "cmp.b $loadaddr $ubootaddr $filesize\0" \
507 "consoledev=ttyS0\0" \
508 "ramdiskaddr=2000000\0" \
509 "ramdiskfile=t2080qds/ramdisk.uboot\0" \
510 "fdtaddr=1e00000\0" \
511 "fdtfile=t2080qds/t2080qds.dtb\0" \
515 * For emulation this causes u-boot to jump to the start of the
516 * proof point app code automatically
518 #define PROOF_POINTS \
519 "setenv bootargs root=/dev/$bdev rw " \
520 "console=$consoledev,$baudrate $othbootargs;" \
521 "cpu 1 release 0x29000000 - - -;" \
522 "cpu 2 release 0x29000000 - - -;" \
523 "cpu 3 release 0x29000000 - - -;" \
524 "cpu 4 release 0x29000000 - - -;" \
525 "cpu 5 release 0x29000000 - - -;" \
526 "cpu 6 release 0x29000000 - - -;" \
527 "cpu 7 release 0x29000000 - - -;" \
531 "setenv bootargs config-addr=0x60000000; " \
532 "bootm 0x01000000 - 0x00f00000"
535 "setenv bootargs root=/dev/$bdev rw " \
536 "console=$consoledev,$baudrate $othbootargs;" \
537 "cpu 1 release 0x01000000 - - -;" \
538 "cpu 2 release 0x01000000 - - -;" \
539 "cpu 3 release 0x01000000 - - -;" \
540 "cpu 4 release 0x01000000 - - -;" \
541 "cpu 5 release 0x01000000 - - -;" \
542 "cpu 6 release 0x01000000 - - -;" \
543 "cpu 7 release 0x01000000 - - -;" \
546 #include <asm/fsl_secure_boot.h>
548 #endif /* __T208xQDS_H */