include/configs/T208xQDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2013 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T2080/T2081 QDS board configuration file
   9  */
  10
  11 #ifndef __T208xQDS_H
  12 #define __T208xQDS_H
  13
  14 #include <linux/stringify.h>
  15
  16 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  17
  18 /* High Level Configuration Options */
  19
  20 #define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  21
  22 #ifdef CONFIG_RAMBOOT_PBL
  23 #define RESET_VECTOR_OFFSET             0x27FFC
  24 #define BOOT_PAGE_OFFSET                0x27000
  25
  26 #ifdef CONFIG_MTD_RAW_NAND
  27 #define CFG_SYS_NAND_U_BOOT_SIZE        (768 << 10)
  28 #define CFG_SYS_NAND_U_BOOT_DST 0x00200000
  29 #define CFG_SYS_NAND_U_BOOT_START       0x00200000
  30 #endif
  31
  32 #ifdef CONFIG_SPIFLASH
  33 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  34 #define CFG_SYS_SPI_FLASH_U_BOOT_SIZE   (768 << 10)
  35 #define CFG_SYS_SPI_FLASH_U_BOOT_DST            (0x00200000)
  36 #define CFG_SYS_SPI_FLASH_U_BOOT_START  (0x00200000)
  37 #define CFG_SYS_SPI_FLASH_U_BOOT_OFFS   (256 << 10)
  38 #endif
  39
  40 #ifdef CONFIG_SDCARD
  41 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  42 #define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  43 #define CFG_SYS_MMC_U_BOOT_DST  (0x00200000)
  44 #define CFG_SYS_MMC_U_BOOT_START        (0x00200000)
  45 #define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10)
  46 #endif
  47
  48 #endif /* CONFIG_RAMBOOT_PBL */
  49
  50 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  51 /* Set 1M boot space */
  52 #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
  53 #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  54                 (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  55 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  56 #endif
  57
  58 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  59 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  60 #endif
  61
  62 /*
  63  * These can be toggled for performance analysis, otherwise use default.
  64  */
  65 #ifdef CONFIG_DDR_ECC
  66 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  67 #endif
  68
  69 /*
  70  * Config the L3 Cache as L3 SRAM
  71  */
  72 #define CFG_SYS_INIT_L3_ADDR            0xFFFC0000
  73 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
  74
  75 #define CFG_SYS_DCSRBAR 0xf0000000
  76 #define CFG_SYS_DCSRBAR_PHYS    0xf00000000ull
  77
  78 /*
  79  * DDR Setup
  80  */
  81 #define CFG_SYS_DDR_SDRAM_BASE  0x00000000
  82 #define CFG_SYS_SDRAM_BASE              CFG_SYS_DDR_SDRAM_BASE
  83 #define CFG_SYS_SDRAM_SIZE      2048    /* for fixed parameter use */
  84 #define SPD_EEPROM_ADDRESS1     0x51
  85 #define SPD_EEPROM_ADDRESS2     0x52
  86 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  87 #define CTRL_INTLV_PREFERED     cacheline
  88
  89 /*
  90  * IFC Definitions
  91  */
  92 #define CFG_SYS_FLASH_BASE              0xe0000000
  93 #define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
  94 #define CFG_SYS_NOR0_CSPR_EXT   (0xf)
  95 #define CFG_SYS_NOR0_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \
  96                                 + 0x8000000) | \
  97                                 CSPR_PORT_SIZE_16 | \
  98                                 CSPR_MSEL_NOR | \
  99                                 CSPR_V)
 100 #define CFG_SYS_NOR1_CSPR_EXT   (0xf)
 101 #define CFG_SYS_NOR1_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
 102                                 CSPR_PORT_SIZE_16 | \
 103                                 CSPR_MSEL_NOR | \
 104                                 CSPR_V)
 105 #define CFG_SYS_NOR_AMASK       IFC_AMASK(128*1024*1024)
 106 /* NOR Flash Timing Params */
 107 #define CFG_SYS_NOR_CSOR        CSOR_NAND_TRHZ_80
 108
 109 #define CFG_SYS_NOR_FTIM0       (FTIM0_NOR_TACSE(0x4) | \
 110                                 FTIM0_NOR_TEADC(0x5) | \
 111                                 FTIM0_NOR_TEAHC(0x5))
 112 #define CFG_SYS_NOR_FTIM1       (FTIM1_NOR_TACO(0x35) | \
 113                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 114                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 115 #define CFG_SYS_NOR_FTIM2       (FTIM2_NOR_TCS(0x4) | \
 116                                 FTIM2_NOR_TCH(0x4) | \
 117                                 FTIM2_NOR_TWPH(0x0E) | \
 118                                 FTIM2_NOR_TWP(0x1c))
 119 #define CFG_SYS_NOR_FTIM3       0x0
 120
 121 #define CFG_SYS_FLASH_BANKS_LIST        {CFG_SYS_FLASH_BASE_PHYS \
 122                                         + 0x8000000, CFG_SYS_FLASH_BASE_PHYS}
 123
 124 #define QIXIS_BASE                      0xffdf0000
 125 #define QIXIS_LBMAP_SWITCH              6
 126 #define QIXIS_LBMAP_MASK                0x0f
 127 #define QIXIS_LBMAP_SHIFT               0
 128 #define QIXIS_LBMAP_DFLTBANK            0x00
 129 #define QIXIS_LBMAP_ALTBANK             0x04
 130 #define QIXIS_LBMAP_NAND                0x09
 131 #define QIXIS_LBMAP_SD                  0x00
 132 #define QIXIS_RCW_SRC_NAND              0x104
 133 #define QIXIS_RCW_SRC_SD                0x040
 134 #define QIXIS_RST_CTL_RESET             0x83
 135 #define QIXIS_RST_FORCE_MEM             0x1
 136 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 137 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 138 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 139 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 140
 141 #define CFG_SYS_CSPR3_EXT       (0xf)
 142 #define CFG_SYS_CSPR3   (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 143                                 | CSPR_PORT_SIZE_8 \
 144                                 | CSPR_MSEL_GPCM \
 145                                 | CSPR_V)
 146 #define CFG_SYS_AMASK3  IFC_AMASK(64 * 1024)
 147 #define CFG_SYS_CSOR3   0x0
 148 /* QIXIS Timing parameters for IFC CS3 */
 149 #define CFG_SYS_CS3_FTIM0               (FTIM0_GPCM_TACSE(0x0e) | \
 150                                         FTIM0_GPCM_TEADC(0x0e) | \
 151                                         FTIM0_GPCM_TEAHC(0x0e))
 152 #define CFG_SYS_CS3_FTIM1               (FTIM1_GPCM_TACO(0xff) | \
 153                                         FTIM1_GPCM_TRAD(0x3f))
 154 #define CFG_SYS_CS3_FTIM2               (FTIM2_GPCM_TCS(0x0e) | \
 155                                         FTIM2_GPCM_TCH(0x8) | \
 156                                         FTIM2_GPCM_TWP(0x1f))
 157 #define CFG_SYS_CS3_FTIM3               0x0
 158
 159 /* NAND Flash on IFC */
 160 #define CFG_SYS_NAND_BASE               0xff800000
 161 #define CFG_SYS_NAND_BASE_PHYS  (0xf00000000ull | CFG_SYS_NAND_BASE)
 162
 163 #define CFG_SYS_NAND_CSPR_EXT   (0xf)
 164 #define CFG_SYS_NAND_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 165                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 166                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 167                                 | CSPR_V)
 168 #define CFG_SYS_NAND_AMASK      IFC_AMASK(64*1024)
 169
 170 #define CFG_SYS_NAND_CSOR       (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 171                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 172                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 173                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 174                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 175                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 176                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 177
 178 /* ONFI NAND Flash mode0 Timing Params */
 179 #define CFG_SYS_NAND_FTIM0              (FTIM0_NAND_TCCST(0x07) | \
 180                                         FTIM0_NAND_TWP(0x18)    | \
 181                                         FTIM0_NAND_TWCHT(0x07)  | \
 182                                         FTIM0_NAND_TWH(0x0a))
 183 #define CFG_SYS_NAND_FTIM1              (FTIM1_NAND_TADLE(0x32) | \
 184                                         FTIM1_NAND_TWBE(0x39)   | \
 185                                         FTIM1_NAND_TRR(0x0e)    | \
 186                                         FTIM1_NAND_TRP(0x18))
 187 #define CFG_SYS_NAND_FTIM2              (FTIM2_NAND_TRAD(0x0f)  | \
 188                                         FTIM2_NAND_TREH(0x0a)   | \
 189                                         FTIM2_NAND_TWHRE(0x1e))
 190 #define CFG_SYS_NAND_FTIM3              0x0
 191
 192 #define CFG_SYS_NAND_BASE_LIST  { CFG_SYS_NAND_BASE }
 193
 194 #if defined(CONFIG_MTD_RAW_NAND)
 195 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NAND_CSPR_EXT
 196 #define CFG_SYS_CSPR0           CFG_SYS_NAND_CSPR
 197 #define CFG_SYS_AMASK0          CFG_SYS_NAND_AMASK
 198 #define CFG_SYS_CSOR0           CFG_SYS_NAND_CSOR
 199 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NAND_FTIM0
 200 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NAND_FTIM1
 201 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NAND_FTIM2
 202 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NAND_FTIM3
 203 #define CFG_SYS_CSPR1_EXT               CFG_SYS_NOR0_CSPR_EXT
 204 #define CFG_SYS_CSPR1           CFG_SYS_NOR0_CSPR
 205 #define CFG_SYS_AMASK1          CFG_SYS_NOR_AMASK
 206 #define CFG_SYS_CSOR1           CFG_SYS_NOR_CSOR
 207 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NOR_FTIM0
 208 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NOR_FTIM1
 209 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NOR_FTIM2
 210 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NOR_FTIM3
 211 #define CFG_SYS_CSPR2_EXT               CFG_SYS_NOR1_CSPR_EXT
 212 #define CFG_SYS_CSPR2           CFG_SYS_NOR1_CSPR
 213 #define CFG_SYS_AMASK2          CFG_SYS_NOR_AMASK
 214 #define CFG_SYS_CSOR2           CFG_SYS_NOR_CSOR
 215 #define CFG_SYS_CS2_FTIM0               CFG_SYS_NOR_FTIM0
 216 #define CFG_SYS_CS2_FTIM1               CFG_SYS_NOR_FTIM1
 217 #define CFG_SYS_CS2_FTIM2               CFG_SYS_NOR_FTIM2
 218 #define CFG_SYS_CS2_FTIM3               CFG_SYS_NOR_FTIM3
 219 #else
 220 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NOR0_CSPR_EXT
 221 #define CFG_SYS_CSPR0           CFG_SYS_NOR0_CSPR
 222 #define CFG_SYS_AMASK0          CFG_SYS_NOR_AMASK
 223 #define CFG_SYS_CSOR0           CFG_SYS_NOR_CSOR
 224 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NOR_FTIM0
 225 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NOR_FTIM1
 226 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NOR_FTIM2
 227 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NOR_FTIM3
 228 #define CFG_SYS_CSPR1_EXT               CFG_SYS_NOR1_CSPR_EXT
 229 #define CFG_SYS_CSPR1           CFG_SYS_NOR1_CSPR
 230 #define CFG_SYS_AMASK1          CFG_SYS_NOR_AMASK
 231 #define CFG_SYS_CSOR1           CFG_SYS_NOR_CSOR
 232 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NOR_FTIM0
 233 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NOR_FTIM1
 234 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NOR_FTIM2
 235 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NOR_FTIM3
 236 #define CFG_SYS_CSPR2_EXT               CFG_SYS_NAND_CSPR_EXT
 237 #define CFG_SYS_CSPR2           CFG_SYS_NAND_CSPR
 238 #define CFG_SYS_AMASK2          CFG_SYS_NAND_AMASK
 239 #define CFG_SYS_CSOR2           CFG_SYS_NAND_CSOR
 240 #define CFG_SYS_CS2_FTIM0               CFG_SYS_NAND_FTIM0
 241 #define CFG_SYS_CS2_FTIM1               CFG_SYS_NAND_FTIM1
 242 #define CFG_SYS_CS2_FTIM2               CFG_SYS_NAND_FTIM2
 243 #define CFG_SYS_CS2_FTIM3               CFG_SYS_NAND_FTIM3
 244 #endif
 245
 246 /* define to use L1 as initial stack */
 247 #define CFG_SYS_INIT_RAM_ADDR   0xfdd00000 /* Initial L1 address */
 248 #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 249 #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW  0xfe03c000
 250 /* The assembler doesn't like typecast */
 251 #define CFG_SYS_INIT_RAM_ADDR_PHYS \
 252                         ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 253                         CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 254 #define CFG_SYS_INIT_RAM_SIZE   0x00004000
 255 #define CFG_SYS_INIT_SP_OFFSET  (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 256
 257 /*
 258  * Serial Port
 259  */
 260 #define CFG_SYS_NS16550_CLK             (get_bus_freq(0)/2)
 261 #define CFG_SYS_BAUDRATE_TABLE  \
 262         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 263 #define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
 264 #define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600)
 265 #define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500)
 266 #define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
 267
 268 /*
 269  * I2C
 270  */
 271
 272 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 273 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 274 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 275 #define I2C_MUX_CH_DEFAULT      0x8
 276
 277 #define I2C_MUX_CH_VOL_MONITOR 0xa
 278
 279 /* Voltage monitor on channel 2*/
 280 #define I2C_VOL_MONITOR_ADDR           0x40
 281 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 282 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 283 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 284
 285 /* The lowest and highest voltage allowed for T208xQDS */
 286 #define VDD_MV_MIN                      819
 287 #define VDD_MV_MAX                      1212
 288
 289 /*
 290  * RapidIO
 291  */
 292 #define CFG_SYS_SRIO1_MEM_VIRT  0xa0000000
 293 #define CFG_SYS_SRIO1_MEM_PHYS  0xc20000000ull
 294 #define CFG_SYS_SRIO1_MEM_SIZE  0x10000000 /* 256M */
 295 #define CFG_SYS_SRIO2_MEM_VIRT  0xb0000000
 296 #define CFG_SYS_SRIO2_MEM_PHYS  0xc30000000ull
 297 #define CFG_SYS_SRIO2_MEM_SIZE  0x10000000 /* 256M */
 298 /*
 299  * for slave u-boot IMAGE instored in master memory space,
 300  * PHYS must be aligned based on the SIZE
 301  */
 302 #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 303 #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 304 #define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 305 #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 306 /*
 307  * for slave UCODE and ENV instored in master memory space,
 308  * PHYS must be aligned based on the SIZE
 309  */
 310 #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 311 #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 312 #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000    /* 256K */
 313
 314 /* slave core release by master*/
 315 #define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 316 #define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 317
 318 /*
 319  * SRIO_PCIE_BOOT - SLAVE
 320  */
 321 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 322 #define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 323 #define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 324                 (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 325 #endif
 326
 327 /*
 328  * eSPI - Enhanced SPI
 329  */
 330
 331 /*
 332  * General PCI
 333  * Memory space is mapped 1-1, but I/O space must start from 0.
 334  */
 335 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 336 #define CFG_SYS_PCIE1_MEM_VIRT  0x80000000
 337 #define CFG_SYS_PCIE1_MEM_PHYS  0xc00000000ull
 338 #define CFG_SYS_PCIE1_IO_VIRT   0xf8000000
 339 #define CFG_SYS_PCIE1_IO_PHYS   0xff8000000ull
 340
 341 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 342 #define CFG_SYS_PCIE2_MEM_VIRT  0xa0000000
 343 #define CFG_SYS_PCIE2_MEM_PHYS  0xc20000000ull
 344 #define CFG_SYS_PCIE2_IO_VIRT   0xf8010000
 345 #define CFG_SYS_PCIE2_IO_PHYS   0xff8010000ull
 346
 347 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 348 #define CFG_SYS_PCIE3_MEM_VIRT  0xb0000000
 349 #define CFG_SYS_PCIE3_MEM_PHYS  0xc30000000ull
 350
 351 /* controller 4, Base address 203000 */
 352 #define CFG_SYS_PCIE4_MEM_VIRT       0xc0000000
 353 #define CFG_SYS_PCIE4_MEM_PHYS  0xc40000000ull
 354
 355 /* Qman/Bman */
 356 #ifndef CONFIG_NOBQFMAN
 357 #define CFG_SYS_BMAN_NUM_PORTALS        18
 358 #define CFG_SYS_BMAN_MEM_BASE   0xf4000000
 359 #define CFG_SYS_BMAN_MEM_PHYS   0xff4000000ull
 360 #define CFG_SYS_BMAN_MEM_SIZE   0x02000000
 361 #define CFG_SYS_BMAN_SP_CENA_SIZE    0x4000
 362 #define CFG_SYS_BMAN_SP_CINH_SIZE    0x1000
 363 #define CFG_SYS_BMAN_CENA_BASE       CFG_SYS_BMAN_MEM_BASE
 364 #define CFG_SYS_BMAN_CENA_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
 365 #define CFG_SYS_BMAN_CINH_BASE       (CFG_SYS_BMAN_MEM_BASE + \
 366                                         CFG_SYS_BMAN_CENA_SIZE)
 367 #define CFG_SYS_BMAN_CINH_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
 368 #define CFG_SYS_BMAN_SWP_ISDR_REG    0xE08
 369 #define CFG_SYS_QMAN_NUM_PORTALS        18
 370 #define CFG_SYS_QMAN_MEM_BASE   0xf6000000
 371 #define CFG_SYS_QMAN_MEM_PHYS   0xff6000000ull
 372 #define CFG_SYS_QMAN_MEM_SIZE   0x02000000
 373 #define CFG_SYS_QMAN_SP_CINH_SIZE    0x1000
 374 #define CFG_SYS_QMAN_CENA_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
 375 #define CFG_SYS_QMAN_CINH_BASE       (CFG_SYS_QMAN_MEM_BASE + \
 376                                         CFG_SYS_QMAN_CENA_SIZE)
 377 #define CFG_SYS_QMAN_CINH_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
 378 #define CFG_SYS_QMAN_SWP_ISDR_REG       0xE08
 379 #endif /* CONFIG_NOBQFMAN */
 380
 381 #ifdef CONFIG_SYS_DPAA_FMAN
 382 #define RGMII_PHY1_ADDR 0x1
 383 #define RGMII_PHY2_ADDR 0x2
 384 #define FM1_10GEC1_PHY_ADDR       0x3
 385 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 386 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 387 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 388 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 389 #endif
 390
 391 /*
 392  * USB
 393  */
 394
 395 /*
 396  * SDHC
 397  */
 398 #ifdef CONFIG_MMC
 399 #define CFG_SYS_FSL_ESDHC_ADDR  CFG_SYS_MPC85xx_ESDHC_ADDR
 400 #endif
 401
 402 /*
 403  * Dynamic MTD Partition support with mtdparts
 404  */
 405
 406 /*
 407  * Miscellaneous configurable options
 408  */
 409
 410 /*
 411  * For booting Linux, the board info and command line data
 412  * have to be in the first 64 MB of memory, since this is
 413  * the maximum mapped by the Linux kernel during initialization.
 414  */
 415 #define CFG_SYS_BOOTMAPSZ       (64 << 20)      /* Initial map for Linux*/
 416
 417 /*
 418  * Environment Configuration
 419  */
 420
 421 #define __USB_PHY_TYPE          utmi
 422
 423 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 424         "hwconfig=fsl_ddr:"                                     \
 425         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 426         "bank_intlv=auto;"                                      \
 427         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 428         "netdev=eth0\0"                                         \
 429         "uboot=" CONFIG_UBOOTPATH "\0"          \
 430         "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
 431         "tftpflash=tftpboot $loadaddr $uboot && "               \
 432         "protect off $ubootaddr +$filesize && "                 \
 433         "erase $ubootaddr +$filesize && "                       \
 434         "cp.b $loadaddr $ubootaddr $filesize && "               \
 435         "protect on $ubootaddr +$filesize && "                  \
 436         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 437         "consoledev=ttyS0\0"                                    \
 438         "ramdiskaddr=2000000\0"                                 \
 439         "ramdiskfile=t2080qds/ramdisk.uboot\0"                  \
 440         "fdtaddr=1e00000\0"                                     \
 441         "fdtfile=t2080qds/t2080qds.dtb\0"                       \
 442         "bdev=sda3\0"
 443
 444 /*
 445  * For emulation this causes u-boot to jump to the start of the
 446  * proof point app code automatically
 447  */
 448 #define PROOF_POINTS                            \
 449         "setenv bootargs root=/dev/$bdev rw "           \
 450         "console=$consoledev,$baudrate $othbootargs;"   \
 451         "cpu 1 release 0x29000000 - - -;"               \
 452         "cpu 2 release 0x29000000 - - -;"               \
 453         "cpu 3 release 0x29000000 - - -;"               \
 454         "cpu 4 release 0x29000000 - - -;"               \
 455         "cpu 5 release 0x29000000 - - -;"               \
 456         "cpu 6 release 0x29000000 - - -;"               \
 457         "cpu 7 release 0x29000000 - - -;"               \
 458         "go 0x29000000"
 459
 460 #define HVBOOT                          \
 461         "setenv bootargs config-addr=0x60000000; "      \
 462         "bootm 0x01000000 - 0x00f00000"
 463
 464 #define ALU                             \
 465         "setenv bootargs root=/dev/$bdev rw "           \
 466         "console=$consoledev,$baudrate $othbootargs;"   \
 467         "cpu 1 release 0x01000000 - - -;"               \
 468         "cpu 2 release 0x01000000 - - -;"               \
 469         "cpu 3 release 0x01000000 - - -;"               \
 470         "cpu 4 release 0x01000000 - - -;"               \
 471         "cpu 5 release 0x01000000 - - -;"               \
 472         "cpu 6 release 0x01000000 - - -;"               \
 473         "cpu 7 release 0x01000000 - - -;"               \
 474         "go 0x01000000"
 475
 476 #include <asm/fsl_secure_boot.h>
 477
 478 #endif  /* __T208xQDS_H */