include/configs/T208xQDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2013 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T2080/T2081 QDS board configuration file
   9  */
  10
  11 #ifndef __T208xQDS_H
  12 #define __T208xQDS_H
  13
  14 #include <linux/stringify.h>
  15
  16 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  17 #if defined(CONFIG_ARCH_T2080)
  18 #define CONFIG_FSL_SATA_V2
  19 #define CONFIG_SYS_SRIO         /* Enable Serial RapidIO Support */
  20 #define CONFIG_SRIO1            /* SRIO port 1 */
  21 #define CONFIG_SRIO2            /* SRIO port 2 */
  22 #endif
  23
  24 /* High Level Configuration Options */
  25 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
  26 #define CONFIG_ENABLE_36BIT_PHYS
  27
  28 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  29 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  30
  31 #ifdef CONFIG_RAMBOOT_PBL
  32 #define RESET_VECTOR_OFFSET             0x27FFC
  33 #define BOOT_PAGE_OFFSET                0x27000
  34
  35 #ifdef CONFIG_MTD_RAW_NAND
  36 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  37 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  38 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  39 #ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
  40 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  41 #endif
  42 #endif
  43
  44 #ifdef CONFIG_SPIFLASH
  45 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  46 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  47 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  48 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
  49 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
  50 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  51 #ifndef CONFIG_SPL_BUILD
  52 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  53 #endif
  54 #endif
  55
  56 #ifdef CONFIG_SDCARD
  57 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  58 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  59 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
  60 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
  61 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  62 #ifndef CONFIG_SPL_BUILD
  63 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  64 #endif
  65 #endif
  66
  67 #endif /* CONFIG_RAMBOOT_PBL */
  68
  69 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  70 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  71 /* Set 1M boot space */
  72 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  73 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  74                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  75 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  76 #endif
  77
  78 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  79 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  80 #endif
  81
  82 /*
  83  * These can be toggled for performance analysis, otherwise use default.
  84  */
  85 #define CONFIG_SYS_CACHE_STASHING
  86 #ifdef CONFIG_DDR_ECC
  87 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  88 #endif
  89
  90 /*
  91  * Config the L3 Cache as L3 SRAM
  92  */
  93 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
  94 #define CONFIG_SYS_L3_SIZE              (512 << 10)
  95 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  96 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
  97
  98 #define CONFIG_SYS_DCSRBAR      0xf0000000
  99 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
 100
 101 /* EEPROM */
 102 #define CONFIG_SYS_I2C_EEPROM_NXID
 103 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 104
 105 /*
 106  * DDR Setup
 107  */
 108 #define CONFIG_VERY_BIG_RAM
 109 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 110 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 111 #define CONFIG_SYS_SPD_BUS_NUM  0
 112 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 113 #define SPD_EEPROM_ADDRESS1     0x51
 114 #define SPD_EEPROM_ADDRESS2     0x52
 115 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 116 #define CTRL_INTLV_PREFERED     cacheline
 117
 118 /*
 119  * IFC Definitions
 120  */
 121 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 122 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 123 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 124 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 125                                 + 0x8000000) | \
 126                                 CSPR_PORT_SIZE_16 | \
 127                                 CSPR_MSEL_NOR | \
 128                                 CSPR_V)
 129 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 130 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 131                                 CSPR_PORT_SIZE_16 | \
 132                                 CSPR_MSEL_NOR | \
 133                                 CSPR_V)
 134 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 135 /* NOR Flash Timing Params */
 136 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 137
 138 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 139                                 FTIM0_NOR_TEADC(0x5) | \
 140                                 FTIM0_NOR_TEAHC(0x5))
 141 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 142                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 143                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 144 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 145                                 FTIM2_NOR_TCH(0x4) | \
 146                                 FTIM2_NOR_TWPH(0x0E) | \
 147                                 FTIM2_NOR_TWP(0x1c))
 148 #define CONFIG_SYS_NOR_FTIM3    0x0
 149
 150 #define CONFIG_SYS_FLASH_QUIET_TEST
 151 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 152
 153 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 154 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 155 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 156
 157 #define CONFIG_SYS_FLASH_EMPTY_INFO
 158 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 159                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 160
 161 #define QIXIS_BASE                      0xffdf0000
 162 #define QIXIS_LBMAP_SWITCH              6
 163 #define QIXIS_LBMAP_MASK                0x0f
 164 #define QIXIS_LBMAP_SHIFT               0
 165 #define QIXIS_LBMAP_DFLTBANK            0x00
 166 #define QIXIS_LBMAP_ALTBANK             0x04
 167 #define QIXIS_LBMAP_NAND                0x09
 168 #define QIXIS_LBMAP_SD                  0x00
 169 #define QIXIS_RCW_SRC_NAND              0x104
 170 #define QIXIS_RCW_SRC_SD                0x040
 171 #define QIXIS_RST_CTL_RESET             0x83
 172 #define QIXIS_RST_FORCE_MEM             0x1
 173 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 174 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 175 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 176 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 177
 178 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 179 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 180                                 | CSPR_PORT_SIZE_8 \
 181                                 | CSPR_MSEL_GPCM \
 182                                 | CSPR_V)
 183 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 184 #define CONFIG_SYS_CSOR3        0x0
 185 /* QIXIS Timing parameters for IFC CS3 */
 186 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 187                                         FTIM0_GPCM_TEADC(0x0e) | \
 188                                         FTIM0_GPCM_TEAHC(0x0e))
 189 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 190                                         FTIM1_GPCM_TRAD(0x3f))
 191 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 192                                         FTIM2_GPCM_TCH(0x8) | \
 193                                         FTIM2_GPCM_TWP(0x1f))
 194 #define CONFIG_SYS_CS3_FTIM3            0x0
 195
 196 /* NAND Flash on IFC */
 197 #define CONFIG_SYS_NAND_BASE            0xff800000
 198 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 199
 200 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 201 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 202                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 203                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 204                                 | CSPR_V)
 205 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 206
 207 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 208                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 209                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 210                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 211                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 212                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 213                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 214
 215 /* ONFI NAND Flash mode0 Timing Params */
 216 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 217                                         FTIM0_NAND_TWP(0x18)    | \
 218                                         FTIM0_NAND_TWCHT(0x07)  | \
 219                                         FTIM0_NAND_TWH(0x0a))
 220 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 221                                         FTIM1_NAND_TWBE(0x39)   | \
 222                                         FTIM1_NAND_TRR(0x0e)    | \
 223                                         FTIM1_NAND_TRP(0x18))
 224 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 225                                         FTIM2_NAND_TREH(0x0a)   | \
 226                                         FTIM2_NAND_TWHRE(0x1e))
 227 #define CONFIG_SYS_NAND_FTIM3           0x0
 228
 229 #define CONFIG_SYS_NAND_DDR_LAW         11
 230 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 231 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 232
 233 #if defined(CONFIG_MTD_RAW_NAND)
 234 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 235 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 236 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 237 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 238 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 239 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 240 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 241 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 242 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 243 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 244 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 245 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 246 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 247 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 248 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 249 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 250 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 251 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 252 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 253 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 254 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 255 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 256 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 257 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 258 #else
 259 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 260 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 261 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 262 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 263 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 264 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 265 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 266 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 267 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 268 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 269 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 270 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 271 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 272 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 273 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 274 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 275 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 276 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 277 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 278 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 279 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 280 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 281 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 282 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 283 #endif
 284
 285 #if defined(CONFIG_RAMBOOT_PBL)
 286 #define CONFIG_SYS_RAMBOOT
 287 #endif
 288
 289 #define CONFIG_HWCONFIG
 290
 291 /* define to use L1 as initial stack */
 292 #define CONFIG_L1_INIT_RAM
 293 #define CONFIG_SYS_INIT_RAM_LOCK
 294 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 295 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 296 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 297 /* The assembler doesn't like typecast */
 298 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 299                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 300                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 301 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 302 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 303 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 304
 305 /*
 306  * Serial Port
 307  */
 308 #define CONFIG_SYS_NS16550_SERIAL
 309 #define CONFIG_SYS_NS16550_REG_SIZE     1
 310 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 311 #define CONFIG_SYS_BAUDRATE_TABLE       \
 312         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 313 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 314 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 315 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 316 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 317
 318 /*
 319  * I2C
 320  */
 321
 322 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 323 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 324 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 325 #define I2C_MUX_CH_DEFAULT      0x8
 326
 327 #define I2C_MUX_CH_VOL_MONITOR 0xa
 328
 329 /* Voltage monitor on channel 2*/
 330 #define I2C_VOL_MONITOR_ADDR           0x40
 331 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 332 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 333 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 334
 335 /* The lowest and highest voltage allowed for T208xQDS */
 336 #define VDD_MV_MIN                      819
 337 #define VDD_MV_MAX                      1212
 338
 339 /*
 340  * RapidIO
 341  */
 342 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 343 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 344 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 345 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 346 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 347 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 348 /*
 349  * for slave u-boot IMAGE instored in master memory space,
 350  * PHYS must be aligned based on the SIZE
 351  */
 352 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 353 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 354 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 355 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 356 /*
 357  * for slave UCODE and ENV instored in master memory space,
 358  * PHYS must be aligned based on the SIZE
 359  */
 360 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 361 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 362 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 363
 364 /* slave core release by master*/
 365 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 366 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 367
 368 /*
 369  * SRIO_PCIE_BOOT - SLAVE
 370  */
 371 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 372 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 373 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 374                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 375 #endif
 376
 377 /*
 378  * eSPI - Enhanced SPI
 379  */
 380
 381 /*
 382  * General PCI
 383  * Memory space is mapped 1-1, but I/O space must start from 0.
 384  */
 385 #define CONFIG_PCIE1            /* PCIE controller 1 */
 386 #define CONFIG_PCIE2            /* PCIE controller 2 */
 387 #define CONFIG_PCIE3            /* PCIE controller 3 */
 388 #define CONFIG_PCIE4            /* PCIE controller 4 */
 389 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 390 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 391 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 392 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 393 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 394
 395 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 396 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 397 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 398 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 399 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 400
 401 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 402 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 403 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 404 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 405 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 406
 407 /* controller 4, Base address 203000 */
 408 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 409 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 410 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 411
 412 #ifdef CONFIG_PCI
 413 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 414 #endif
 415
 416 /* Qman/Bman */
 417 #ifndef CONFIG_NOBQFMAN
 418 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 419 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 420 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 421 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 422 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 423 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 424 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 425 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 426 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 427                                         CONFIG_SYS_BMAN_CENA_SIZE)
 428 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 429 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 430 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 431 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 432 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 433 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 434 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 435 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 436 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 437 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 438 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 439                                         CONFIG_SYS_QMAN_CENA_SIZE)
 440 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 441 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 442
 443 #define CONFIG_SYS_DPAA_FMAN
 444 #define CONFIG_SYS_DPAA_PME
 445 #define CONFIG_SYS_PMAN
 446 #define CONFIG_SYS_DPAA_DCE
 447 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 448 #define CONFIG_SYS_INTERLAKEN
 449
 450 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 451 #endif /* CONFIG_NOBQFMAN */
 452
 453 #ifdef CONFIG_SYS_DPAA_FMAN
 454 #define RGMII_PHY1_ADDR 0x1
 455 #define RGMII_PHY2_ADDR 0x2
 456 #define FM1_10GEC1_PHY_ADDR       0x3
 457 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 458 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 459 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 460 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 461 #endif
 462
 463 /*
 464  * SATA
 465  */
 466 #ifdef CONFIG_FSL_SATA_V2
 467 #define CONFIG_SATA1
 468 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 469 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 470 #define CONFIG_SATA2
 471 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 472 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 473 #define CONFIG_LBA48
 474 #endif
 475
 476 /*
 477  * USB
 478  */
 479 #ifdef CONFIG_USB_EHCI_HCD
 480 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 481 #define CONFIG_HAS_FSL_DR_USB
 482 #endif
 483
 484 /*
 485  * SDHC
 486  */
 487 #ifdef CONFIG_MMC
 488 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 489 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 490 #endif
 491
 492 /*
 493  * Dynamic MTD Partition support with mtdparts
 494  */
 495
 496 /*
 497  * Environment
 498  */
 499 #define CONFIG_LOADS_ECHO       /* echo on for serial download */
 500 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 501
 502 /*
 503  * Miscellaneous configurable options
 504  */
 505
 506 /*
 507  * For booting Linux, the board info and command line data
 508  * have to be in the first 64 MB of memory, since this is
 509  * the maximum mapped by the Linux kernel during initialization.
 510  */
 511 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 512 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 513
 514 /*
 515  * Environment Configuration
 516  */
 517 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 518 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 519
 520 #define __USB_PHY_TYPE          utmi
 521
 522 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 523         "hwconfig=fsl_ddr:"                                     \
 524         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 525         "bank_intlv=auto;"                                      \
 526         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 527         "netdev=eth0\0"                                         \
 528         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 529         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 530         "tftpflash=tftpboot $loadaddr $uboot && "               \
 531         "protect off $ubootaddr +$filesize && "                 \
 532         "erase $ubootaddr +$filesize && "                       \
 533         "cp.b $loadaddr $ubootaddr $filesize && "               \
 534         "protect on $ubootaddr +$filesize && "                  \
 535         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 536         "consoledev=ttyS0\0"                                    \
 537         "ramdiskaddr=2000000\0"                                 \
 538         "ramdiskfile=t2080qds/ramdisk.uboot\0"                  \
 539         "fdtaddr=1e00000\0"                                     \
 540         "fdtfile=t2080qds/t2080qds.dtb\0"                       \
 541         "bdev=sda3\0"
 542
 543 /*
 544  * For emulation this causes u-boot to jump to the start of the
 545  * proof point app code automatically
 546  */
 547 #define PROOF_POINTS                            \
 548         "setenv bootargs root=/dev/$bdev rw "           \
 549         "console=$consoledev,$baudrate $othbootargs;"   \
 550         "cpu 1 release 0x29000000 - - -;"               \
 551         "cpu 2 release 0x29000000 - - -;"               \
 552         "cpu 3 release 0x29000000 - - -;"               \
 553         "cpu 4 release 0x29000000 - - -;"               \
 554         "cpu 5 release 0x29000000 - - -;"               \
 555         "cpu 6 release 0x29000000 - - -;"               \
 556         "cpu 7 release 0x29000000 - - -;"               \
 557         "go 0x29000000"
 558
 559 #define HVBOOT                          \
 560         "setenv bootargs config-addr=0x60000000; "      \
 561         "bootm 0x01000000 - 0x00f00000"
 562
 563 #define ALU                             \
 564         "setenv bootargs root=/dev/$bdev rw "           \
 565         "console=$consoledev,$baudrate $othbootargs;"   \
 566         "cpu 1 release 0x01000000 - - -;"               \
 567         "cpu 2 release 0x01000000 - - -;"               \
 568         "cpu 3 release 0x01000000 - - -;"               \
 569         "cpu 4 release 0x01000000 - - -;"               \
 570         "cpu 5 release 0x01000000 - - -;"               \
 571         "cpu 6 release 0x01000000 - - -;"               \
 572         "cpu 7 release 0x01000000 - - -;"               \
 573         "go 0x01000000"
 574
 575 #include <asm/fsl_secure_boot.h>
 576
 577 #endif  /* __T208xQDS_H */