include/configs/T208xQDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2013 Freescale Semiconductor, Inc.
   4  */
   5
   6 /*
   7  * T2080/T2081 QDS board configuration file
   8  */
   9
  10 #ifndef __T208xQDS_H
  11 #define __T208xQDS_H
  12
  13 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  14 #if defined(CONFIG_ARCH_T2080)
  15 #define CONFIG_FSL_SATA_V2
  16 #define CONFIG_SYS_SRIO         /* Enable Serial RapidIO Support */
  17 #define CONFIG_SRIO1            /* SRIO port 1 */
  18 #define CONFIG_SRIO2            /* SRIO port 2 */
  19 #elif defined(CONFIG_ARCH_T2081)
  20 #endif
  21
  22 /* High Level Configuration Options */
  23 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
  24 #define CONFIG_ENABLE_36BIT_PHYS
  25
  26 #ifdef CONFIG_PHYS_64BIT
  27 #define CONFIG_ADDR_MAP 1
  28 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  29 #endif
  30
  31 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  32 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  33 #define CONFIG_ENV_OVERWRITE
  34
  35 #ifdef CONFIG_RAMBOOT_PBL
  36 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
  37
  38 #define CONFIG_SPL_FLUSH_IMAGE
  39 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  40 #define CONFIG_SPL_PAD_TO               0x40000
  41 #define CONFIG_SPL_MAX_SIZE             0x28000
  42 #define RESET_VECTOR_OFFSET             0x27FFC
  43 #define BOOT_PAGE_OFFSET                0x27000
  44 #ifdef CONFIG_SPL_BUILD
  45 #define CONFIG_SPL_SKIP_RELOCATE
  46 #define CONFIG_SPL_COMMON_INIT_DDR
  47 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  48 #endif
  49
  50 #ifdef CONFIG_NAND
  51 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  52 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  53 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  54 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  55 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  56 #if defined(CONFIG_ARCH_T2080)
  57 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg
  58 #elif defined(CONFIG_ARCH_T2081)
  59 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg
  60 #endif
  61 #define CONFIG_SPL_NAND_BOOT
  62 #endif
  63
  64 #ifdef CONFIG_SPIFLASH
  65 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  66 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
  69 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
  70 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  71 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  72 #ifndef CONFIG_SPL_BUILD
  73 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  74 #endif
  75 #if defined(CONFIG_ARCH_T2080)
  76 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg
  77 #elif defined(CONFIG_ARCH_T2081)
  78 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg
  79 #endif
  80 #define CONFIG_SPL_SPI_BOOT
  81 #endif
  82
  83 #ifdef CONFIG_SDCARD
  84 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  85 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  86 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
  87 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
  88 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  89 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  90 #ifndef CONFIG_SPL_BUILD
  91 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  92 #endif
  93 #if defined(CONFIG_ARCH_T2080)
  94 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg
  95 #elif defined(CONFIG_ARCH_T2081)
  96 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg
  97 #endif
  98 #define CONFIG_SPL_MMC_BOOT
  99 #endif
 100
 101 #endif /* CONFIG_RAMBOOT_PBL */
 102
 103 #define CONFIG_SRIO_PCIE_BOOT_MASTER
 104 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 105 /* Set 1M boot space */
 106 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 107 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
 108                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 109 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 110 #endif
 111
 112 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 113 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 114 #endif
 115
 116 /*
 117  * These can be toggled for performance analysis, otherwise use default.
 118  */
 119 #define CONFIG_SYS_CACHE_STASHING
 120 #define CONFIG_BTB              /* toggle branch predition */
 121 #define CONFIG_DDR_ECC
 122 #ifdef CONFIG_DDR_ECC
 123 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 124 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 125 #endif
 126
 127 #if defined(CONFIG_SPIFLASH)
 128 #define CONFIG_ENV_SIZE         0x2000     /* 8KB */
 129 #define CONFIG_ENV_OFFSET       0x100000   /* 1MB */
 130 #define CONFIG_ENV_SECT_SIZE    0x10000
 131 #elif defined(CONFIG_SDCARD)
 132 #define CONFIG_SYS_MMC_ENV_DEV  0
 133 #define CONFIG_ENV_SIZE         0x2000
 134 #define CONFIG_ENV_OFFSET       (512 * 0x800)
 135 #elif defined(CONFIG_NAND)
 136 #define CONFIG_ENV_SIZE         0x2000
 137 #define CONFIG_ENV_OFFSET       (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 138 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 139 #define CONFIG_ENV_ADDR         0xffe20000
 140 #define CONFIG_ENV_SIZE         0x2000
 141 #elif defined(CONFIG_ENV_IS_NOWHERE)
 142 #define CONFIG_ENV_SIZE         0x2000
 143 #else
 144 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 145 #define CONFIG_ENV_SIZE         0x2000
 146 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 147 #endif
 148
 149 #ifndef __ASSEMBLY__
 150 unsigned long get_board_sys_clk(void);
 151 unsigned long get_board_ddr_clk(void);
 152 #endif
 153
 154 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
 155 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 156
 157 /*
 158  * Config the L3 Cache as L3 SRAM
 159  */
 160 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 161 #define CONFIG_SYS_L3_SIZE              (512 << 10)
 162 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 163 #ifdef CONFIG_RAMBOOT_PBL
 164 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 165 #endif
 166 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 167 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
 168 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 169
 170 #define CONFIG_SYS_DCSRBAR      0xf0000000
 171 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
 172
 173 /* EEPROM */
 174 #define CONFIG_ID_EEPROM
 175 #define CONFIG_SYS_I2C_EEPROM_NXID
 176 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 177 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 178 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 179
 180 /*
 181  * DDR Setup
 182  */
 183 #define CONFIG_VERY_BIG_RAM
 184 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 185 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 186 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
 187 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 188 #define CONFIG_DDR_SPD
 189 #define CONFIG_SYS_SPD_BUS_NUM  0
 190 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 191 #define SPD_EEPROM_ADDRESS1     0x51
 192 #define SPD_EEPROM_ADDRESS2     0x52
 193 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 194 #define CTRL_INTLV_PREFERED     cacheline
 195
 196 /*
 197  * IFC Definitions
 198  */
 199 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 200 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 201 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 202 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 203                                 + 0x8000000) | \
 204                                 CSPR_PORT_SIZE_16 | \
 205                                 CSPR_MSEL_NOR | \
 206                                 CSPR_V)
 207 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 208 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 209                                 CSPR_PORT_SIZE_16 | \
 210                                 CSPR_MSEL_NOR | \
 211                                 CSPR_V)
 212 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 213 /* NOR Flash Timing Params */
 214 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 215
 216 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 217                                 FTIM0_NOR_TEADC(0x5) | \
 218                                 FTIM0_NOR_TEAHC(0x5))
 219 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 220                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 221                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 222 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 223                                 FTIM2_NOR_TCH(0x4) | \
 224                                 FTIM2_NOR_TWPH(0x0E) | \
 225                                 FTIM2_NOR_TWP(0x1c))
 226 #define CONFIG_SYS_NOR_FTIM3    0x0
 227
 228 #define CONFIG_SYS_FLASH_QUIET_TEST
 229 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 230
 231 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 232 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 233 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 234 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 235
 236 #define CONFIG_SYS_FLASH_EMPTY_INFO
 237 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 238                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 239
 240 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 241 #define QIXIS_BASE                      0xffdf0000
 242 #define QIXIS_LBMAP_SWITCH              6
 243 #define QIXIS_LBMAP_MASK                0x0f
 244 #define QIXIS_LBMAP_SHIFT               0
 245 #define QIXIS_LBMAP_DFLTBANK            0x00
 246 #define QIXIS_LBMAP_ALTBANK             0x04
 247 #define QIXIS_LBMAP_NAND                0x09
 248 #define QIXIS_LBMAP_SD                  0x00
 249 #define QIXIS_RCW_SRC_NAND              0x104
 250 #define QIXIS_RCW_SRC_SD                0x040
 251 #define QIXIS_RST_CTL_RESET             0x83
 252 #define QIXIS_RST_FORCE_MEM             0x1
 253 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 254 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 255 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 256 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 257
 258 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 259 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 260                                 | CSPR_PORT_SIZE_8 \
 261                                 | CSPR_MSEL_GPCM \
 262                                 | CSPR_V)
 263 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 264 #define CONFIG_SYS_CSOR3        0x0
 265 /* QIXIS Timing parameters for IFC CS3 */
 266 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 267                                         FTIM0_GPCM_TEADC(0x0e) | \
 268                                         FTIM0_GPCM_TEAHC(0x0e))
 269 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 270                                         FTIM1_GPCM_TRAD(0x3f))
 271 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 272                                         FTIM2_GPCM_TCH(0x8) | \
 273                                         FTIM2_GPCM_TWP(0x1f))
 274 #define CONFIG_SYS_CS3_FTIM3            0x0
 275
 276 /* NAND Flash on IFC */
 277 #define CONFIG_NAND_FSL_IFC
 278 #define CONFIG_SYS_NAND_BASE            0xff800000
 279 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 280
 281 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 282 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 283                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 284                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 285                                 | CSPR_V)
 286 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 287
 288 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 289                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 290                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 291                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 292                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 293                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 294                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 295
 296 #define CONFIG_SYS_NAND_ONFI_DETECTION
 297
 298 /* ONFI NAND Flash mode0 Timing Params */
 299 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 300                                         FTIM0_NAND_TWP(0x18)    | \
 301                                         FTIM0_NAND_TWCHT(0x07)  | \
 302                                         FTIM0_NAND_TWH(0x0a))
 303 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 304                                         FTIM1_NAND_TWBE(0x39)   | \
 305                                         FTIM1_NAND_TRR(0x0e)    | \
 306                                         FTIM1_NAND_TRP(0x18))
 307 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 308                                         FTIM2_NAND_TREH(0x0a)   | \
 309                                         FTIM2_NAND_TWHRE(0x1e))
 310 #define CONFIG_SYS_NAND_FTIM3           0x0
 311
 312 #define CONFIG_SYS_NAND_DDR_LAW         11
 313 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 314 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 315 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 316
 317 #if defined(CONFIG_NAND)
 318 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 319 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 320 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 321 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 322 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 323 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 324 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 325 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 326 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 327 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 328 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 329 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 330 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 331 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 332 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 333 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 334 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 335 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 336 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 337 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 338 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 339 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 340 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 341 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 342 #else
 343 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 344 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 345 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 346 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 347 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 348 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 349 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 350 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 351 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 352 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 353 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 354 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 355 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 356 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 357 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 358 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 359 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 360 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 361 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 362 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 363 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 364 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 365 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 366 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 367 #endif
 368
 369 #if defined(CONFIG_RAMBOOT_PBL)
 370 #define CONFIG_SYS_RAMBOOT
 371 #endif
 372
 373 #ifdef CONFIG_SPL_BUILD
 374 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 375 #else
 376 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 377 #endif
 378
 379 #define CONFIG_HWCONFIG
 380
 381 /* define to use L1 as initial stack */
 382 #define CONFIG_L1_INIT_RAM
 383 #define CONFIG_SYS_INIT_RAM_LOCK
 384 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 385 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 386 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 387 /* The assembler doesn't like typecast */
 388 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 389                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 390                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 391 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 392 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 393                                                 GENERATED_GBL_DATA_SIZE)
 394 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 395 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 396 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 397
 398 /*
 399  * Serial Port
 400  */
 401 #define CONFIG_SYS_NS16550_SERIAL
 402 #define CONFIG_SYS_NS16550_REG_SIZE     1
 403 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 404 #define CONFIG_SYS_BAUDRATE_TABLE       \
 405         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 406 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 407 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 408 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 409 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 410
 411 /*
 412  * I2C
 413  */
 414 #define CONFIG_SYS_I2C
 415 #define CONFIG_SYS_I2C_FSL
 416 #define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
 417 #define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
 418 #define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
 419 #define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
 420 #define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
 421 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
 422 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
 423 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
 424 #define CONFIG_SYS_FSL_I2C_SPEED   100000
 425 #define CONFIG_SYS_FSL_I2C2_SPEED  100000
 426 #define CONFIG_SYS_FSL_I2C3_SPEED  100000
 427 #define CONFIG_SYS_FSL_I2C4_SPEED  100000
 428 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 429 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 430 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 431 #define I2C_MUX_CH_DEFAULT      0x8
 432
 433 #define I2C_MUX_CH_VOL_MONITOR 0xa
 434
 435 /* Voltage monitor on channel 2*/
 436 #define I2C_VOL_MONITOR_ADDR           0x40
 437 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 438 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 439 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 440
 441 #define CONFIG_VID_FLS_ENV              "t208xqds_vdd_mv"
 442 #ifndef CONFIG_SPL_BUILD
 443 #define CONFIG_VID
 444 #endif
 445 #define CONFIG_VOL_MONITOR_IR36021_SET
 446 #define CONFIG_VOL_MONITOR_IR36021_READ
 447 /* The lowest and highest voltage allowed for T208xQDS */
 448 #define VDD_MV_MIN                      819
 449 #define VDD_MV_MAX                      1212
 450
 451 /*
 452  * RapidIO
 453  */
 454 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 455 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 456 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 457 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 458 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 459 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 460 /*
 461  * for slave u-boot IMAGE instored in master memory space,
 462  * PHYS must be aligned based on the SIZE
 463  */
 464 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 465 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 466 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 467 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 468 /*
 469  * for slave UCODE and ENV instored in master memory space,
 470  * PHYS must be aligned based on the SIZE
 471  */
 472 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 473 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 474 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 475
 476 /* slave core release by master*/
 477 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 478 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 479
 480 /*
 481  * SRIO_PCIE_BOOT - SLAVE
 482  */
 483 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 484 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 485 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 486                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 487 #endif
 488
 489 /*
 490  * eSPI - Enhanced SPI
 491  */
 492
 493 /*
 494  * General PCI
 495  * Memory space is mapped 1-1, but I/O space must start from 0.
 496  */
 497 #define CONFIG_PCIE1            /* PCIE controller 1 */
 498 #define CONFIG_PCIE2            /* PCIE controller 2 */
 499 #define CONFIG_PCIE3            /* PCIE controller 3 */
 500 #define CONFIG_PCIE4            /* PCIE controller 4 */
 501 #define CONFIG_FSL_PCIE_RESET   /* pcie reset fix link width 2x-4x*/
 502 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 503 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 504 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 505 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 506 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 507 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 508 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 509 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 510 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 511 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 512 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 513
 514 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 515 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 516 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 517 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 518 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000 /* 256M */
 519 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 520 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 521 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 522 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 523
 524 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 525 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 526 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 527 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 528 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 529 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 530 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 531 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 532 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 533
 534 /* controller 4, Base address 203000 */
 535 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 536 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 537 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 538 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 539 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 540 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 541 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 542
 543 #ifdef CONFIG_PCI
 544 #define CONFIG_PCI_INDIRECT_BRIDGE
 545 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 546 #endif
 547
 548 /* Qman/Bman */
 549 #ifndef CONFIG_NOBQFMAN
 550 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 551 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 552 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 553 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 554 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 555 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 556 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 557 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 558 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 559                                         CONFIG_SYS_BMAN_CENA_SIZE)
 560 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 561 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 562 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 563 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 564 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 565 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 566 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 567 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 568 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 569 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 570 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 571                                         CONFIG_SYS_QMAN_CENA_SIZE)
 572 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 573 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 574
 575 #define CONFIG_SYS_DPAA_FMAN
 576 #define CONFIG_SYS_DPAA_PME
 577 #define CONFIG_SYS_PMAN
 578 #define CONFIG_SYS_DPAA_DCE
 579 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 580 #define CONFIG_SYS_INTERLAKEN
 581
 582 /* Default address of microcode for the Linux Fman driver */
 583 #if defined(CONFIG_SPIFLASH)
 584 /*
 585  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 586  * env, so we got 0x110000.
 587  */
 588 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 589 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 590 #elif defined(CONFIG_SDCARD)
 591 /*
 592  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 593  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 594  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 595  */
 596 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 597 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 598 #elif defined(CONFIG_NAND)
 599 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 600 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 601 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 602 /*
 603  * Slave has no ucode locally, it can fetch this from remote. When implementing
 604  * in two corenet boards, slave's ucode could be stored in master's memory
 605  * space, the address can be mapped from slave TLB->slave LAW->
 606  * slave SRIO or PCIE outbound window->master inbound window->
 607  * master LAW->the ucode address in master's memory space.
 608  */
 609 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 610 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 611 #else
 612 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 613 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
 614 #endif
 615 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 616 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 617 #endif /* CONFIG_NOBQFMAN */
 618
 619 #ifdef CONFIG_SYS_DPAA_FMAN
 620 #define CONFIG_FMAN_ENET
 621 #define CONFIG_PHY_VITESSE
 622 #define CONFIG_PHY_REALTEK
 623 #define CONFIG_PHY_TERANETICS
 624 #define RGMII_PHY1_ADDR 0x1
 625 #define RGMII_PHY2_ADDR 0x2
 626 #define FM1_10GEC1_PHY_ADDR       0x3
 627 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 628 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 629 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 630 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 631 #endif
 632
 633 #ifdef CONFIG_FMAN_ENET
 634 #define CONFIG_ETHPRIME         "FM1@DTSEC3"
 635 #endif
 636
 637 /*
 638  * SATA
 639  */
 640 #ifdef CONFIG_FSL_SATA_V2
 641 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 642 #define CONFIG_SATA1
 643 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 644 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 645 #define CONFIG_SATA2
 646 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 647 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 648 #define CONFIG_LBA48
 649 #endif
 650
 651 /*
 652  * USB
 653  */
 654 #ifdef CONFIG_USB_EHCI_HCD
 655 #define CONFIG_USB_EHCI_FSL
 656 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 657 #define CONFIG_HAS_FSL_DR_USB
 658 #endif
 659
 660 /*
 661  * SDHC
 662  */
 663 #ifdef CONFIG_MMC
 664 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
 665 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 666 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 667 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 668 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT
 669 #endif
 670
 671 /*
 672  * Dynamic MTD Partition support with mtdparts
 673  */
 674
 675 /*
 676  * Environment
 677  */
 678 #define CONFIG_LOADS_ECHO       /* echo on for serial download */
 679 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 680
 681 /*
 682  * Miscellaneous configurable options
 683  */
 684 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
 685
 686 /*
 687  * For booting Linux, the board info and command line data
 688  * have to be in the first 64 MB of memory, since this is
 689  * the maximum mapped by the Linux kernel during initialization.
 690  */
 691 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 692 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 693
 694 #ifdef CONFIG_CMD_KGDB
 695 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 696 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 697 #endif
 698
 699 /*
 700  * Environment Configuration
 701  */
 702 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 703 #define CONFIG_BOOTFILE  "uImage"
 704 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 705
 706 /* default location for tftp and bootm */
 707 #define CONFIG_LOADADDR         1000000
 708 #define __USB_PHY_TYPE          utmi
 709
 710 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 711         "hwconfig=fsl_ddr:"                                     \
 712         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 713         "bank_intlv=auto;"                                      \
 714         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 715         "netdev=eth0\0"                                         \
 716         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 717         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 718         "tftpflash=tftpboot $loadaddr $uboot && "               \
 719         "protect off $ubootaddr +$filesize && "                 \
 720         "erase $ubootaddr +$filesize && "                       \
 721         "cp.b $loadaddr $ubootaddr $filesize && "               \
 722         "protect on $ubootaddr +$filesize && "                  \
 723         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 724         "consoledev=ttyS0\0"                                    \
 725         "ramdiskaddr=2000000\0"                                 \
 726         "ramdiskfile=t2080qds/ramdisk.uboot\0"                  \
 727         "fdtaddr=1e00000\0"                                     \
 728         "fdtfile=t2080qds/t2080qds.dtb\0"                       \
 729         "bdev=sda3\0"
 730
 731 /*
 732  * For emulation this causes u-boot to jump to the start of the
 733  * proof point app code automatically
 734  */
 735 #define CONFIG_PROOF_POINTS                             \
 736         "setenv bootargs root=/dev/$bdev rw "           \
 737         "console=$consoledev,$baudrate $othbootargs;"   \
 738         "cpu 1 release 0x29000000 - - -;"               \
 739         "cpu 2 release 0x29000000 - - -;"               \
 740         "cpu 3 release 0x29000000 - - -;"               \
 741         "cpu 4 release 0x29000000 - - -;"               \
 742         "cpu 5 release 0x29000000 - - -;"               \
 743         "cpu 6 release 0x29000000 - - -;"               \
 744         "cpu 7 release 0x29000000 - - -;"               \
 745         "go 0x29000000"
 746
 747 #define CONFIG_HVBOOT                           \
 748         "setenv bootargs config-addr=0x60000000; "      \
 749         "bootm 0x01000000 - 0x00f00000"
 750
 751 #define CONFIG_ALU                              \
 752         "setenv bootargs root=/dev/$bdev rw "           \
 753         "console=$consoledev,$baudrate $othbootargs;"   \
 754         "cpu 1 release 0x01000000 - - -;"               \
 755         "cpu 2 release 0x01000000 - - -;"               \
 756         "cpu 3 release 0x01000000 - - -;"               \
 757         "cpu 4 release 0x01000000 - - -;"               \
 758         "cpu 5 release 0x01000000 - - -;"               \
 759         "cpu 6 release 0x01000000 - - -;"               \
 760         "cpu 7 release 0x01000000 - - -;"               \
 761         "go 0x01000000"
 762
 763 #define CONFIG_LINUX                            \
 764         "setenv bootargs root=/dev/ram rw "             \
 765         "console=$consoledev,$baudrate $othbootargs;"   \
 766         "setenv ramdiskaddr 0x02000000;"                \
 767         "setenv fdtaddr 0x00c00000;"                    \
 768         "setenv loadaddr 0x1000000;"                    \
 769         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 770
 771 #define CONFIG_HDBOOT                                   \
 772         "setenv bootargs root=/dev/$bdev rw "           \
 773         "console=$consoledev,$baudrate $othbootargs;"   \
 774         "tftp $loadaddr $bootfile;"                     \
 775         "tftp $fdtaddr $fdtfile;"                       \
 776         "bootm $loadaddr - $fdtaddr"
 777
 778 #define CONFIG_NFSBOOTCOMMAND                   \
 779         "setenv bootargs root=/dev/nfs rw "     \
 780         "nfsroot=$serverip:$rootpath "          \
 781         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 782         "console=$consoledev,$baudrate $othbootargs;"   \
 783         "tftp $loadaddr $bootfile;"             \
 784         "tftp $fdtaddr $fdtfile;"               \
 785         "bootm $loadaddr - $fdtaddr"
 786
 787 #define CONFIG_RAMBOOTCOMMAND                           \
 788         "setenv bootargs root=/dev/ram rw "             \
 789         "console=$consoledev,$baudrate $othbootargs;"   \
 790         "tftp $ramdiskaddr $ramdiskfile;"               \
 791         "tftp $loadaddr $bootfile;"                     \
 792         "tftp $fdtaddr $fdtfile;"                       \
 793         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 794
 795 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 796
 797 #include <asm/fsl_secure_boot.h>
 798
 799 #endif  /* __T208xQDS_H */