include/configs/T208xQDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2013 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T2080/T2081 QDS board configuration file
   9  */
  10
  11 #ifndef __T208xQDS_H
  12 #define __T208xQDS_H
  13
  14 #include <linux/stringify.h>
  15
  16 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  17 #if defined(CONFIG_ARCH_T2080)
  18 #define CONFIG_SYS_SRIO         /* Enable Serial RapidIO Support */
  19 #define CONFIG_SRIO1            /* SRIO port 1 */
  20 #define CONFIG_SRIO2            /* SRIO port 2 */
  21 #endif
  22
  23 /* High Level Configuration Options */
  24 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
  25
  26 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  27 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  28
  29 #ifdef CONFIG_RAMBOOT_PBL
  30 #define RESET_VECTOR_OFFSET             0x27FFC
  31 #define BOOT_PAGE_OFFSET                0x27000
  32
  33 #ifdef CONFIG_MTD_RAW_NAND
  34 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  35 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  36 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  37 #endif
  38
  39 #ifdef CONFIG_SPIFLASH
  40 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  41 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  42 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
  43 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
  44 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  45 #endif
  46
  47 #ifdef CONFIG_SDCARD
  48 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  49 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  50 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
  51 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
  52 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  53 #endif
  54
  55 #endif /* CONFIG_RAMBOOT_PBL */
  56
  57 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  58 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  59 /* Set 1M boot space */
  60 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  61 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  62                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  63 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  64 #endif
  65
  66 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  67 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  68 #endif
  69
  70 /*
  71  * These can be toggled for performance analysis, otherwise use default.
  72  */
  73 #define CONFIG_SYS_CACHE_STASHING
  74 #ifdef CONFIG_DDR_ECC
  75 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  76 #endif
  77
  78 /*
  79  * Config the L3 Cache as L3 SRAM
  80  */
  81 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
  82 #define CONFIG_SYS_L3_SIZE              (512 << 10)
  83 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
  84
  85 #define CONFIG_SYS_DCSRBAR      0xf0000000
  86 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  87
  88 /* EEPROM */
  89 #define CONFIG_SYS_I2C_EEPROM_NXID
  90 #define CONFIG_SYS_EEPROM_BUS_NUM       0
  91
  92 /*
  93  * DDR Setup
  94  */
  95 #define CONFIG_VERY_BIG_RAM
  96 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  97 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  98 #define CONFIG_SYS_SPD_BUS_NUM  0
  99 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 100 #define SPD_EEPROM_ADDRESS1     0x51
 101 #define SPD_EEPROM_ADDRESS2     0x52
 102 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 103 #define CTRL_INTLV_PREFERED     cacheline
 104
 105 /*
 106  * IFC Definitions
 107  */
 108 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 109 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 110 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 111 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 112                                 + 0x8000000) | \
 113                                 CSPR_PORT_SIZE_16 | \
 114                                 CSPR_MSEL_NOR | \
 115                                 CSPR_V)
 116 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 117 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 118                                 CSPR_PORT_SIZE_16 | \
 119                                 CSPR_MSEL_NOR | \
 120                                 CSPR_V)
 121 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 122 /* NOR Flash Timing Params */
 123 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 124
 125 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 126                                 FTIM0_NOR_TEADC(0x5) | \
 127                                 FTIM0_NOR_TEAHC(0x5))
 128 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 129                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 130                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 131 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 132                                 FTIM2_NOR_TCH(0x4) | \
 133                                 FTIM2_NOR_TWPH(0x0E) | \
 134                                 FTIM2_NOR_TWP(0x1c))
 135 #define CONFIG_SYS_NOR_FTIM3    0x0
 136
 137 #define CONFIG_SYS_FLASH_QUIET_TEST
 138 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 139
 140 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 141 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 142 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 143
 144 #define CONFIG_SYS_FLASH_EMPTY_INFO
 145 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 146                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 147
 148 #define QIXIS_BASE                      0xffdf0000
 149 #define QIXIS_LBMAP_SWITCH              6
 150 #define QIXIS_LBMAP_MASK                0x0f
 151 #define QIXIS_LBMAP_SHIFT               0
 152 #define QIXIS_LBMAP_DFLTBANK            0x00
 153 #define QIXIS_LBMAP_ALTBANK             0x04
 154 #define QIXIS_LBMAP_NAND                0x09
 155 #define QIXIS_LBMAP_SD                  0x00
 156 #define QIXIS_RCW_SRC_NAND              0x104
 157 #define QIXIS_RCW_SRC_SD                0x040
 158 #define QIXIS_RST_CTL_RESET             0x83
 159 #define QIXIS_RST_FORCE_MEM             0x1
 160 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 161 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 162 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 163 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 164
 165 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 166 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 167                                 | CSPR_PORT_SIZE_8 \
 168                                 | CSPR_MSEL_GPCM \
 169                                 | CSPR_V)
 170 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 171 #define CONFIG_SYS_CSOR3        0x0
 172 /* QIXIS Timing parameters for IFC CS3 */
 173 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 174                                         FTIM0_GPCM_TEADC(0x0e) | \
 175                                         FTIM0_GPCM_TEAHC(0x0e))
 176 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 177                                         FTIM1_GPCM_TRAD(0x3f))
 178 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 179                                         FTIM2_GPCM_TCH(0x8) | \
 180                                         FTIM2_GPCM_TWP(0x1f))
 181 #define CONFIG_SYS_CS3_FTIM3            0x0
 182
 183 /* NAND Flash on IFC */
 184 #define CONFIG_SYS_NAND_BASE            0xff800000
 185 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 186
 187 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 188 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 189                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 190                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 191                                 | CSPR_V)
 192 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 193
 194 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 195                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 196                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 197                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 198                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 199                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 200                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 201
 202 /* ONFI NAND Flash mode0 Timing Params */
 203 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 204                                         FTIM0_NAND_TWP(0x18)    | \
 205                                         FTIM0_NAND_TWCHT(0x07)  | \
 206                                         FTIM0_NAND_TWH(0x0a))
 207 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 208                                         FTIM1_NAND_TWBE(0x39)   | \
 209                                         FTIM1_NAND_TRR(0x0e)    | \
 210                                         FTIM1_NAND_TRP(0x18))
 211 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 212                                         FTIM2_NAND_TREH(0x0a)   | \
 213                                         FTIM2_NAND_TWHRE(0x1e))
 214 #define CONFIG_SYS_NAND_FTIM3           0x0
 215
 216 #define CONFIG_SYS_NAND_DDR_LAW         11
 217 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 218 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 219
 220 #if defined(CONFIG_MTD_RAW_NAND)
 221 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 222 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 223 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 224 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 225 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 226 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 227 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 228 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 229 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 230 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 231 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 232 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 233 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 234 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 235 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 236 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 237 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 238 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 239 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 240 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 241 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 242 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 243 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 244 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 245 #else
 246 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 247 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 248 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 249 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 250 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 251 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 252 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 253 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 254 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 255 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 256 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 257 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 258 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 259 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 260 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 261 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 262 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 263 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 264 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 265 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 266 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 267 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 268 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 269 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 270 #endif
 271
 272 #if defined(CONFIG_RAMBOOT_PBL)
 273 #define CONFIG_SYS_RAMBOOT
 274 #endif
 275
 276 #define CONFIG_HWCONFIG
 277
 278 /* define to use L1 as initial stack */
 279 #define CONFIG_L1_INIT_RAM
 280 #define CONFIG_SYS_INIT_RAM_LOCK
 281 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 282 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 283 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 284 /* The assembler doesn't like typecast */
 285 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 286                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 287                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 288 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 289 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 290 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 291
 292 /*
 293  * Serial Port
 294  */
 295 #define CONFIG_SYS_NS16550_SERIAL
 296 #define CONFIG_SYS_NS16550_REG_SIZE     1
 297 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 298 #define CONFIG_SYS_BAUDRATE_TABLE       \
 299         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 300 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 301 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 302 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 303 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 304
 305 /*
 306  * I2C
 307  */
 308
 309 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 310 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 311 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 312 #define I2C_MUX_CH_DEFAULT      0x8
 313
 314 #define I2C_MUX_CH_VOL_MONITOR 0xa
 315
 316 /* Voltage monitor on channel 2*/
 317 #define I2C_VOL_MONITOR_ADDR           0x40
 318 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 319 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 320 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 321
 322 /* The lowest and highest voltage allowed for T208xQDS */
 323 #define VDD_MV_MIN                      819
 324 #define VDD_MV_MAX                      1212
 325
 326 /*
 327  * RapidIO
 328  */
 329 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 330 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 331 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 332 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 333 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 334 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 335 /*
 336  * for slave u-boot IMAGE instored in master memory space,
 337  * PHYS must be aligned based on the SIZE
 338  */
 339 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 340 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 341 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 342 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 343 /*
 344  * for slave UCODE and ENV instored in master memory space,
 345  * PHYS must be aligned based on the SIZE
 346  */
 347 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 348 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 349 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 350
 351 /* slave core release by master*/
 352 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 353 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 354
 355 /*
 356  * SRIO_PCIE_BOOT - SLAVE
 357  */
 358 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 359 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 360 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 361                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 362 #endif
 363
 364 /*
 365  * eSPI - Enhanced SPI
 366  */
 367
 368 /*
 369  * General PCI
 370  * Memory space is mapped 1-1, but I/O space must start from 0.
 371  */
 372 #define CONFIG_PCIE1            /* PCIE controller 1 */
 373 #define CONFIG_PCIE2            /* PCIE controller 2 */
 374 #define CONFIG_PCIE3            /* PCIE controller 3 */
 375 #define CONFIG_PCIE4            /* PCIE controller 4 */
 376 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 377 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 378 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 379 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 380 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 381
 382 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 383 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 384 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 385 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 386 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 387
 388 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 389 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 390 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 391 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 392 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 393
 394 /* controller 4, Base address 203000 */
 395 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 396 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 397 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 398
 399 #ifdef CONFIG_PCI
 400 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 401 #endif
 402
 403 /* Qman/Bman */
 404 #ifndef CONFIG_NOBQFMAN
 405 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 406 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 407 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 408 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 409 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 410 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 411 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 412 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 413 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 414                                         CONFIG_SYS_BMAN_CENA_SIZE)
 415 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 416 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 417 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 418 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 419 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 420 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 421 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 422 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 423 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 424 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 425 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 426                                         CONFIG_SYS_QMAN_CENA_SIZE)
 427 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 428 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 429
 430 #define CONFIG_SYS_DPAA_FMAN
 431 #define CONFIG_SYS_DPAA_PME
 432 #define CONFIG_SYS_PMAN
 433 #define CONFIG_SYS_DPAA_DCE
 434 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 435 #define CONFIG_SYS_INTERLAKEN
 436
 437 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 438 #endif /* CONFIG_NOBQFMAN */
 439
 440 #ifdef CONFIG_SYS_DPAA_FMAN
 441 #define RGMII_PHY1_ADDR 0x1
 442 #define RGMII_PHY2_ADDR 0x2
 443 #define FM1_10GEC1_PHY_ADDR       0x3
 444 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 445 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 446 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 447 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 448 #endif
 449
 450 /*
 451  * USB
 452  */
 453
 454 /*
 455  * SDHC
 456  */
 457 #ifdef CONFIG_MMC
 458 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 459 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 460 #endif
 461
 462 /*
 463  * Dynamic MTD Partition support with mtdparts
 464  */
 465
 466 /*
 467  * Environment
 468  */
 469 #define CONFIG_LOADS_ECHO       /* echo on for serial download */
 470 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 471
 472 /*
 473  * Miscellaneous configurable options
 474  */
 475
 476 /*
 477  * For booting Linux, the board info and command line data
 478  * have to be in the first 64 MB of memory, since this is
 479  * the maximum mapped by the Linux kernel during initialization.
 480  */
 481 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 482 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 483
 484 /*
 485  * Environment Configuration
 486  */
 487 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 488 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 489
 490 #define __USB_PHY_TYPE          utmi
 491
 492 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 493         "hwconfig=fsl_ddr:"                                     \
 494         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 495         "bank_intlv=auto;"                                      \
 496         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 497         "netdev=eth0\0"                                         \
 498         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 499         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 500         "tftpflash=tftpboot $loadaddr $uboot && "               \
 501         "protect off $ubootaddr +$filesize && "                 \
 502         "erase $ubootaddr +$filesize && "                       \
 503         "cp.b $loadaddr $ubootaddr $filesize && "               \
 504         "protect on $ubootaddr +$filesize && "                  \
 505         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 506         "consoledev=ttyS0\0"                                    \
 507         "ramdiskaddr=2000000\0"                                 \
 508         "ramdiskfile=t2080qds/ramdisk.uboot\0"                  \
 509         "fdtaddr=1e00000\0"                                     \
 510         "fdtfile=t2080qds/t2080qds.dtb\0"                       \
 511         "bdev=sda3\0"
 512
 513 /*
 514  * For emulation this causes u-boot to jump to the start of the
 515  * proof point app code automatically
 516  */
 517 #define PROOF_POINTS                            \
 518         "setenv bootargs root=/dev/$bdev rw "           \
 519         "console=$consoledev,$baudrate $othbootargs;"   \
 520         "cpu 1 release 0x29000000 - - -;"               \
 521         "cpu 2 release 0x29000000 - - -;"               \
 522         "cpu 3 release 0x29000000 - - -;"               \
 523         "cpu 4 release 0x29000000 - - -;"               \
 524         "cpu 5 release 0x29000000 - - -;"               \
 525         "cpu 6 release 0x29000000 - - -;"               \
 526         "cpu 7 release 0x29000000 - - -;"               \
 527         "go 0x29000000"
 528
 529 #define HVBOOT                          \
 530         "setenv bootargs config-addr=0x60000000; "      \
 531         "bootm 0x01000000 - 0x00f00000"
 532
 533 #define ALU                             \
 534         "setenv bootargs root=/dev/$bdev rw "           \
 535         "console=$consoledev,$baudrate $othbootargs;"   \
 536         "cpu 1 release 0x01000000 - - -;"               \
 537         "cpu 2 release 0x01000000 - - -;"               \
 538         "cpu 3 release 0x01000000 - - -;"               \
 539         "cpu 4 release 0x01000000 - - -;"               \
 540         "cpu 5 release 0x01000000 - - -;"               \
 541         "cpu 6 release 0x01000000 - - -;"               \
 542         "cpu 7 release 0x01000000 - - -;"               \
 543         "go 0x01000000"
 544
 545 #include <asm/fsl_secure_boot.h>
 546
 547 #endif  /* __T208xQDS_H */