2 * Copyright 2011-2013 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * T2080 QDS board configuration file
14 #define CONFIG_T2080QDS
15 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
17 #define CONFIG_SPI_FLASH
18 #define CONFIG_USB_EHCI
19 #define CONFIG_FSL_SATA_V2
20 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
21 #define CONFIG_SRIO1 /* SRIO port 1 */
22 #define CONFIG_SRIO2 /* SRIO port 2 */
24 /* High Level Configuration Options */
25 #define CONFIG_PHYS_64BIT
27 #define CONFIG_E500 /* BOOKE e500 family */
28 #define CONFIG_E500MC /* BOOKE e500mc family */
29 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
30 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
31 #define CONFIG_MP /* support multiple processors */
32 #define CONFIG_ENABLE_36BIT_PHYS
34 #ifdef CONFIG_PHYS_64BIT
35 #define CONFIG_ADDR_MAP 1
36 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
39 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
40 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
41 #define CONFIG_FSL_IFC /* Enable IFC Support */
42 #define CONFIG_FSL_LAW /* Use common FSL init code */
43 #define CONFIG_ENV_OVERWRITE
45 #ifdef CONFIG_RAMBOOT_PBL
46 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
47 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
48 #define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t2080qds/t2080_pbi.cfg
49 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t2080qds/t2080_rcw.cfg
52 #define CONFIG_SRIO_PCIE_BOOT_MASTER
53 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
54 /* Set 1M boot space */
55 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
56 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
57 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
58 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
59 #define CONFIG_SYS_NO_FLASH
62 #ifndef CONFIG_SYS_TEXT_BASE
63 #define CONFIG_SYS_TEXT_BASE 0xeff80000
66 #ifndef CONFIG_RESET_VECTOR_ADDRESS
67 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
71 * These can be toggled for performance analysis, otherwise use default.
73 #define CONFIG_SYS_CACHE_STASHING
74 #define CONFIG_BTB /* toggle branch predition */
75 #define CONFIG_DDR_ECC
77 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
78 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
81 #ifdef CONFIG_SYS_NO_FLASH
82 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
83 #define CONFIG_ENV_IS_NOWHERE
86 #define CONFIG_FLASH_CFI_DRIVER
87 #define CONFIG_SYS_FLASH_CFI
88 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
91 #if defined(CONFIG_SPIFLASH)
92 #define CONFIG_SYS_EXTRA_ENV_RELOC
93 #define CONFIG_ENV_IS_IN_SPI_FLASH
94 #define CONFIG_ENV_SPI_BUS 0
95 #define CONFIG_ENV_SPI_CS 0
96 #define CONFIG_ENV_SPI_MAX_HZ 10000000
97 #define CONFIG_ENV_SPI_MODE 0
98 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
99 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
100 #define CONFIG_ENV_SECT_SIZE 0x10000
101 #elif defined(CONFIG_SDCARD)
102 #define CONFIG_SYS_EXTRA_ENV_RELOC
103 #define CONFIG_ENV_IS_IN_MMC
104 #define CONFIG_SYS_MMC_ENV_DEV 0
105 #define CONFIG_ENV_SIZE 0x2000
106 #define CONFIG_ENV_OFFSET (512 * 1105)
107 #elif defined(CONFIG_NAND)
108 #define CONFIG_SYS_EXTRA_ENV_RELOC
109 #define CONFIG_ENV_IS_IN_NAND
110 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
111 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
112 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
113 #define CONFIG_ENV_IS_IN_REMOTE
114 #define CONFIG_ENV_ADDR 0xffe20000
115 #define CONFIG_ENV_SIZE 0x2000
116 #elif defined(CONFIG_ENV_IS_NOWHERE)
117 #define CONFIG_ENV_SIZE 0x2000
119 #define CONFIG_ENV_IS_IN_FLASH
120 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
121 #define CONFIG_ENV_SIZE 0x2000
122 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
126 unsigned long get_board_sys_clk(void);
127 unsigned long get_board_ddr_clk(void);
130 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
131 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
134 * Config the L3 Cache as L3 SRAM
136 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
138 #define CONFIG_SYS_DCSRBAR 0xf0000000
139 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
142 #define CONFIG_ID_EEPROM
143 #define CONFIG_SYS_I2C_EEPROM_NXID
144 #define CONFIG_SYS_EEPROM_BUS_NUM 0
145 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
146 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
151 #define CONFIG_VERY_BIG_RAM
152 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
153 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
154 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
155 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
156 #define CONFIG_DDR_SPD
157 #define CONFIG_SYS_FSL_DDR3
158 #undef CONFIG_FSL_DDR_INTERACTIVE
159 #define CONFIG_SYS_SPD_BUS_NUM 0
160 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
161 #define SPD_EEPROM_ADDRESS1 0x51
162 #define SPD_EEPROM_ADDRESS2 0x52
163 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
164 #define CTRL_INTLV_PREFERED cacheline
169 #define CONFIG_SYS_FLASH_BASE 0xe0000000
170 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
171 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
172 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
174 CSPR_PORT_SIZE_16 | \
177 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
178 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
179 CSPR_PORT_SIZE_16 | \
182 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
183 /* NOR Flash Timing Params */
184 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
186 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
187 FTIM0_NOR_TEADC(0x5) | \
188 FTIM0_NOR_TEAHC(0x5))
189 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
190 FTIM1_NOR_TRAD_NOR(0x1A) |\
191 FTIM1_NOR_TSEQRAD_NOR(0x13))
192 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
193 FTIM2_NOR_TCH(0x4) | \
194 FTIM2_NOR_TWPH(0x0E) | \
196 #define CONFIG_SYS_NOR_FTIM3 0x0
198 #define CONFIG_SYS_FLASH_QUIET_TEST
199 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
201 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
202 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
203 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
204 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
206 #define CONFIG_SYS_FLASH_EMPTY_INFO
207 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
208 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
210 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
211 #define QIXIS_BASE 0xffdf0000
212 #define QIXIS_LBMAP_SWITCH 6
213 #define QIXIS_LBMAP_MASK 0x0f
214 #define QIXIS_LBMAP_SHIFT 0
215 #define QIXIS_LBMAP_DFLTBANK 0x00
216 #define QIXIS_LBMAP_ALTBANK 0x04
217 #define QIXIS_RST_CTL_RESET 0x83
218 #define QIXIS_RST_FORCE_MEM 0x1
219 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
220 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
221 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
222 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
224 #define CONFIG_SYS_CSPR3_EXT (0xf)
225 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
229 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
230 #define CONFIG_SYS_CSOR3 0x0
231 /* QIXIS Timing parameters for IFC CS3 */
232 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
233 FTIM0_GPCM_TEADC(0x0e) | \
234 FTIM0_GPCM_TEAHC(0x0e))
235 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
236 FTIM1_GPCM_TRAD(0x3f))
237 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
238 FTIM2_GPCM_TCH(0x0) | \
239 FTIM2_GPCM_TWP(0x1f))
240 #define CONFIG_SYS_CS3_FTIM3 0x0
242 /* NAND Flash on IFC */
243 #define CONFIG_NAND_FSL_IFC
244 #define CONFIG_SYS_NAND_BASE 0xff800000
245 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
247 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
248 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
249 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
250 | CSPR_MSEL_NAND /* MSEL = NAND */ \
252 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
254 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
255 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
256 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
257 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
258 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
259 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
260 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
262 #define CONFIG_SYS_NAND_ONFI_DETECTION
264 /* ONFI NAND Flash mode0 Timing Params */
265 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
266 FTIM0_NAND_TWP(0x18) | \
267 FTIM0_NAND_TWCHT(0x07) | \
268 FTIM0_NAND_TWH(0x0a))
269 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
270 FTIM1_NAND_TWBE(0x39) | \
271 FTIM1_NAND_TRR(0x0e) | \
272 FTIM1_NAND_TRP(0x18))
273 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
274 FTIM2_NAND_TREH(0x0a) | \
275 FTIM2_NAND_TWHRE(0x1e))
276 #define CONFIG_SYS_NAND_FTIM3 0x0
278 #define CONFIG_SYS_NAND_DDR_LAW 11
279 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
280 #define CONFIG_SYS_MAX_NAND_DEVICE 1
281 #define CONFIG_MTD_NAND_VERIFY_WRITE
282 #define CONFIG_CMD_NAND
283 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
285 #if defined(CONFIG_NAND)
286 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
287 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
288 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
289 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
290 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
291 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
292 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
293 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
294 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
295 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
296 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
297 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
298 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
299 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
300 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
301 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
303 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
304 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
305 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
306 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
307 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
308 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
309 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
310 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
311 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
312 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
313 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
314 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
315 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
316 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
317 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
318 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
320 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
321 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
322 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
323 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
324 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
325 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
326 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
327 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
329 #if defined(CONFIG_RAMBOOT_PBL)
330 #define CONFIG_SYS_RAMBOOT
333 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
334 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
335 #define CONFIG_MISC_INIT_R
336 #define CONFIG_HWCONFIG
338 /* define to use L1 as initial stack */
339 #define CONFIG_L1_INIT_RAM
340 #define CONFIG_SYS_INIT_RAM_LOCK
341 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
342 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
343 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
344 /* The assembler doesn't like typecast */
345 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
346 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
347 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
348 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
349 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
350 GENERATED_GBL_DATA_SIZE)
351 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
352 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
353 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
358 #define CONFIG_CONS_INDEX 1
359 #define CONFIG_SYS_NS16550
360 #define CONFIG_SYS_NS16550_SERIAL
361 #define CONFIG_SYS_NS16550_REG_SIZE 1
362 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
363 #define CONFIG_SYS_BAUDRATE_TABLE \
364 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
365 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
366 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
367 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
368 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
370 /* Use the HUSH parser */
371 #define CONFIG_SYS_HUSH_PARSER
372 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
374 /* pass open firmware flat tree */
375 #define CONFIG_OF_LIBFDT
376 #define CONFIG_OF_BOARD_SETUP
377 #define CONFIG_OF_STDOUT_VIA_ALIAS
379 /* new uImage format support */
381 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
386 #define CONFIG_SYS_I2C
387 #define CONFIG_SYS_I2C_FSL
388 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
389 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
390 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
391 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
392 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
393 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
394 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
395 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
396 #define CONFIG_SYS_FSL_I2C_SPEED 100000
397 #define CONFIG_SYS_FSL_I2C2_SPEED 100000
398 #define CONFIG_SYS_FSL_I2C3_SPEED 100000
399 #define CONFIG_SYS_FSL_I2C4_SPEED 100000
400 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
401 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
402 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
403 #define I2C_MUX_CH_DEFAULT 0x8
409 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
410 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
411 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
412 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
413 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
414 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
416 * for slave u-boot IMAGE instored in master memory space,
417 * PHYS must be aligned based on the SIZE
419 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
420 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
421 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
422 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
424 * for slave UCODE and ENV instored in master memory space,
425 * PHYS must be aligned based on the SIZE
427 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
428 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
429 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
431 /* slave core release by master*/
432 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
433 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
436 * SRIO_PCIE_BOOT - SLAVE
438 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
439 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
440 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
441 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
445 * eSPI - Enhanced SPI
447 #ifdef CONFIG_SPI_FLASH
448 #define CONFIG_FSL_ESPI
449 #define CONFIG_SPI_FLASH_SST
450 #define CONFIG_SPI_FLASH_STMICRO
451 #define CONFIG_SPI_FLASH_SPANSION
452 #define CONFIG_CMD_SF
453 #define CONFIG_SF_DEFAULT_SPEED 10000000
454 #define CONFIG_SF_DEFAULT_MODE 0
459 * Memory space is mapped 1-1, but I/O space must start from 0.
461 #define CONFIG_PCI /* Enable PCI/PCIE */
462 #define CONFIG_PCIE1 /* PCIE controler 1 */
463 #define CONFIG_PCIE2 /* PCIE controler 2 */
464 #define CONFIG_PCIE3 /* PCIE controler 3 */
465 #define CONFIG_PCIE4 /* PCIE controler 4 */
466 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
467 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
468 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
469 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
470 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
471 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
472 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
473 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
474 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
475 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
476 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
478 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
479 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
480 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
481 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
482 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
483 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
484 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
485 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
486 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
488 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
489 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
490 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
491 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
492 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
493 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
494 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
495 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
496 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
498 /* controller 4, Base address 203000 */
499 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
500 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
501 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
502 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
503 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
504 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
505 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
508 #define CONFIG_PCI_INDIRECT_BRIDGE
509 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */
510 #define CONFIG_NET_MULTI
512 #define CONFIG_PCI_PNP /* do pci plug-and-play */
513 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
514 #define CONFIG_DOS_PARTITION
518 #ifndef CONFIG_NOBQFMAN
519 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
520 #define CONFIG_SYS_BMAN_NUM_PORTALS 18
521 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
522 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
523 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
524 #define CONFIG_SYS_QMAN_NUM_PORTALS 18
525 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
526 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
527 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
529 #define CONFIG_SYS_DPAA_FMAN
530 #define CONFIG_SYS_DPAA_PME
531 #define CONFIG_SYS_PMAN
532 #define CONFIG_SYS_DPAA_DCE
533 #define CONFIG_SYS_DPAA_RMAN /* RMan */
534 #define CONFIG_SYS_INTERLAKEN
536 /* Default address of microcode for the Linux Fman driver */
537 #if defined(CONFIG_SPIFLASH)
539 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
540 * env, so we got 0x110000.
542 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
543 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
544 #elif defined(CONFIG_SDCARD)
546 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
547 * about 545KB (1089 blocks), Env is stored after the image, and the env size is
548 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
550 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
551 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
552 #elif defined(CONFIG_NAND)
553 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
554 #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
555 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
557 * Slave has no ucode locally, it can fetch this from remote. When implementing
558 * in two corenet boards, slave's ucode could be stored in master's memory
559 * space, the address can be mapped from slave TLB->slave LAW->
560 * slave SRIO or PCIE outbound window->master inbound window->
561 * master LAW->the ucode address in master's memory space.
563 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
564 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
566 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
567 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
569 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
570 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
571 #endif /* CONFIG_NOBQFMAN */
573 #ifdef CONFIG_SYS_DPAA_FMAN
574 #define CONFIG_FMAN_ENET
575 #define CONFIG_PHYLIB_10G
576 #define CONFIG_PHY_VITESSE
577 #define CONFIG_PHY_REALTEK
578 #define CONFIG_PHY_TERANETICS
579 #define RGMII_PHY1_ADDR 0x1
580 #define RGMII_PHY2_ADDR 0x2
581 #define FM1_10GEC1_PHY_ADDR 0x3
582 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
583 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
584 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
585 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
588 #ifdef CONFIG_FMAN_ENET
589 #define CONFIG_MII /* MII PHY management */
590 #define CONFIG_ETHPRIME "FM1@DTSEC3"
591 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
597 #ifdef CONFIG_FSL_SATA_V2
598 #define CONFIG_LIBATA
599 #define CONFIG_FSL_SATA
600 #define CONFIG_SYS_SATA_MAX_DEVICE 2
602 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
603 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
605 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
606 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
608 #define CONFIG_CMD_SATA
609 #define CONFIG_DOS_PARTITION
610 #define CONFIG_CMD_EXT2
616 #ifdef CONFIG_USB_EHCI
617 #define CONFIG_CMD_USB
618 #define CONFIG_USB_STORAGE
619 #define CONFIG_USB_EHCI_FSL
620 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
621 #define CONFIG_CMD_EXT2
622 #define CONFIG_HAS_FSL_DR_USB
629 #define CONFIG_CMD_MMC
630 #define CONFIG_FSL_ESDHC
631 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
632 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
633 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
634 #define CONFIG_GENERIC_MMC
635 #define CONFIG_CMD_EXT2
636 #define CONFIG_CMD_FAT
637 #define CONFIG_DOS_PARTITION
643 #define CONFIG_LOADS_ECHO /* echo on for serial download */
644 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
647 * Command line configuration.
649 #include <config_cmd_default.h>
651 #define CONFIG_CMD_DHCP
652 #define CONFIG_CMD_ELF
653 #define CONFIG_CMD_ERRATA
654 #define CONFIG_CMD_GREPENV
655 #define CONFIG_CMD_IRQ
656 #define CONFIG_CMD_I2C
657 #define CONFIG_CMD_MII
658 #define CONFIG_CMD_PING
659 #define CONFIG_CMD_SETEXPR
660 #define CONFIG_CMD_REGINFO
661 #define CONFIG_CMD_BDI
664 #define CONFIG_CMD_PCI
665 #define CONFIG_CMD_NET
669 * Miscellaneous configurable options
671 #define CONFIG_SYS_LONGHELP /* undef to save memory */
672 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
673 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
674 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
675 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
676 #ifdef CONFIG_CMD_KGDB
677 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
679 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
681 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
682 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
683 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
684 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/
687 * For booting Linux, the board info and command line data
688 * have to be in the first 64 MB of memory, since this is
689 * the maximum mapped by the Linux kernel during initialization.
691 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
692 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
694 #ifdef CONFIG_CMD_KGDB
695 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
696 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
700 * Environment Configuration
702 #define CONFIG_ROOTPATH "/opt/nfsroot"
703 #define CONFIG_BOOTFILE "uImage"
704 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
706 /* default location for tftp and bootm */
707 #define CONFIG_LOADADDR 1000000
708 #define CONFIG_BAUDRATE 115200
709 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
710 #define __USB_PHY_TYPE utmi
712 #define CONFIG_EXTRA_ENV_SETTINGS \
713 "hwconfig=fsl_ddr:" \
714 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
716 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
718 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
719 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
720 "tftpflash=tftpboot $loadaddr $uboot && " \
721 "protect off $ubootaddr +$filesize && " \
722 "erase $ubootaddr +$filesize && " \
723 "cp.b $loadaddr $ubootaddr $filesize && " \
724 "protect on $ubootaddr +$filesize && " \
725 "cmp.b $loadaddr $ubootaddr $filesize\0" \
726 "consoledev=ttyS0\0" \
727 "ramdiskaddr=2000000\0" \
728 "ramdiskfile=t2080qds/ramdisk.uboot\0" \
730 "fdtfile=t2080qds/t2080qds.dtb\0" \
735 * For emulation this causes u-boot to jump to the start of the
736 * proof point app code automatically
738 #define CONFIG_PROOF_POINTS \
739 "setenv bootargs root=/dev/$bdev rw " \
740 "console=$consoledev,$baudrate $othbootargs;" \
741 "cpu 1 release 0x29000000 - - -;" \
742 "cpu 2 release 0x29000000 - - -;" \
743 "cpu 3 release 0x29000000 - - -;" \
744 "cpu 4 release 0x29000000 - - -;" \
745 "cpu 5 release 0x29000000 - - -;" \
746 "cpu 6 release 0x29000000 - - -;" \
747 "cpu 7 release 0x29000000 - - -;" \
750 #define CONFIG_HVBOOT \
751 "setenv bootargs config-addr=0x60000000; " \
752 "bootm 0x01000000 - 0x00f00000"
755 "setenv bootargs root=/dev/$bdev rw " \
756 "console=$consoledev,$baudrate $othbootargs;" \
757 "cpu 1 release 0x01000000 - - -;" \
758 "cpu 2 release 0x01000000 - - -;" \
759 "cpu 3 release 0x01000000 - - -;" \
760 "cpu 4 release 0x01000000 - - -;" \
761 "cpu 5 release 0x01000000 - - -;" \
762 "cpu 6 release 0x01000000 - - -;" \
763 "cpu 7 release 0x01000000 - - -;" \
766 #define CONFIG_LINUX \
767 "setenv bootargs root=/dev/ram rw " \
768 "console=$consoledev,$baudrate $othbootargs;" \
769 "setenv ramdiskaddr 0x02000000;" \
770 "setenv fdtaddr 0x00c00000;" \
771 "setenv loadaddr 0x1000000;" \
772 "bootm $loadaddr $ramdiskaddr $fdtaddr"
774 #define CONFIG_HDBOOT \
775 "setenv bootargs root=/dev/$bdev rw " \
776 "console=$consoledev,$baudrate $othbootargs;" \
777 "tftp $loadaddr $bootfile;" \
778 "tftp $fdtaddr $fdtfile;" \
779 "bootm $loadaddr - $fdtaddr"
781 #define CONFIG_NFSBOOTCOMMAND \
782 "setenv bootargs root=/dev/nfs rw " \
783 "nfsroot=$serverip:$rootpath " \
784 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
785 "console=$consoledev,$baudrate $othbootargs;" \
786 "tftp $loadaddr $bootfile;" \
787 "tftp $fdtaddr $fdtfile;" \
788 "bootm $loadaddr - $fdtaddr"
790 #define CONFIG_RAMBOOTCOMMAND \
791 "setenv bootargs root=/dev/ram rw " \
792 "console=$consoledev,$baudrate $othbootargs;" \
793 "tftp $ramdiskaddr $ramdiskfile;" \
794 "tftp $loadaddr $bootfile;" \
795 "tftp $fdtaddr $fdtfile;" \
796 "bootm $loadaddr $ramdiskaddr $fdtaddr"
798 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
800 #ifdef CONFIG_SECURE_BOOT
801 #include <asm/fsl_secure_boot.h>
802 #undef CONFIG_CMD_USB
805 #endif /* __T2080QDS_H */