1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
10 #include <linux/stringify.h>
13 * T104x RDB board configuration file
15 #include <asm/config_mpc85xx.h>
17 #ifdef CONFIG_RAMBOOT_PBL
19 #ifndef CONFIG_NXP_ESBC
20 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
22 #define CONFIG_SYS_FSL_PBL_PBI \
23 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg
26 #define CONFIG_SPL_FLUSH_IMAGE
27 #define CONFIG_SPL_PAD_TO 0x40000
28 #define CONFIG_SPL_MAX_SIZE 0x28000
29 #ifdef CONFIG_SPL_BUILD
30 #define CONFIG_SPL_SKIP_RELOCATE
31 #define CONFIG_SPL_COMMON_INIT_DDR
32 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
34 #define RESET_VECTOR_OFFSET 0x27FFC
35 #define BOOT_PAGE_OFFSET 0x27000
37 #ifdef CONFIG_MTD_RAW_NAND
38 #ifdef CONFIG_NXP_ESBC
39 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
41 * HDR would be appended at end of image and copied to DDR along
44 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \
45 CONFIG_U_BOOT_HDR_SIZE)
47 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
49 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
50 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
51 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
52 #ifdef CONFIG_TARGET_T1040RDB
53 #define CONFIG_SYS_FSL_PBL_RCW \
54 $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg
56 #ifdef CONFIG_TARGET_T1042RDB_PI
57 #define CONFIG_SYS_FSL_PBL_RCW \
58 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
60 #ifdef CONFIG_TARGET_T1042RDB
61 #define CONFIG_SYS_FSL_PBL_RCW \
62 $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg
64 #ifdef CONFIG_TARGET_T1040D4RDB
65 #define CONFIG_SYS_FSL_PBL_RCW \
66 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
68 #ifdef CONFIG_TARGET_T1042D4RDB
69 #define CONFIG_SYS_FSL_PBL_RCW \
70 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
74 #ifdef CONFIG_SPIFLASH
75 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
76 #define CONFIG_SPL_SPI_FLASH_MINIMAL
77 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
78 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
79 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
80 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
81 #ifndef CONFIG_SPL_BUILD
82 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
84 #ifdef CONFIG_TARGET_T1040RDB
85 #define CONFIG_SYS_FSL_PBL_RCW \
86 $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg
88 #ifdef CONFIG_TARGET_T1042RDB_PI
89 #define CONFIG_SYS_FSL_PBL_RCW \
90 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
92 #ifdef CONFIG_TARGET_T1042RDB
93 #define CONFIG_SYS_FSL_PBL_RCW \
94 $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg
96 #ifdef CONFIG_TARGET_T1040D4RDB
97 #define CONFIG_SYS_FSL_PBL_RCW \
98 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
100 #ifdef CONFIG_TARGET_T1042D4RDB
101 #define CONFIG_SYS_FSL_PBL_RCW \
102 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
107 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
108 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
109 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
110 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
111 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
112 #ifndef CONFIG_SPL_BUILD
113 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
115 #ifdef CONFIG_TARGET_T1040RDB
116 #define CONFIG_SYS_FSL_PBL_RCW \
117 $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg
119 #ifdef CONFIG_TARGET_T1042RDB_PI
120 #define CONFIG_SYS_FSL_PBL_RCW \
121 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
123 #ifdef CONFIG_TARGET_T1042RDB
124 #define CONFIG_SYS_FSL_PBL_RCW \
125 $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg
127 #ifdef CONFIG_TARGET_T1040D4RDB
128 #define CONFIG_SYS_FSL_PBL_RCW \
129 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
131 #ifdef CONFIG_TARGET_T1042D4RDB
132 #define CONFIG_SYS_FSL_PBL_RCW \
133 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
139 /* High Level Configuration Options */
140 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
142 /* support deep sleep */
143 #define CONFIG_DEEP_SLEEP
145 #ifndef CONFIG_RESET_VECTOR_ADDRESS
146 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
149 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
150 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
151 #define CONFIG_PCIE1 /* PCIE controller 1 */
152 #define CONFIG_PCIE2 /* PCIE controller 2 */
153 #define CONFIG_PCIE3 /* PCIE controller 3 */
154 #define CONFIG_PCIE4 /* PCIE controller 4 */
156 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
158 #if defined(CONFIG_SPIFLASH)
159 #elif defined(CONFIG_MTD_RAW_NAND)
160 #ifdef CONFIG_NXP_ESBC
161 #define CONFIG_RAMBOOT_NAND
162 #define CONFIG_BOOTSCRIPT_COPY_RAM
166 #define CONFIG_SYS_CLK_FREQ 100000000
169 * These can be toggled for performance analysis, otherwise use default.
171 #define CONFIG_SYS_CACHE_STASHING
172 #define CONFIG_BACKSIDE_L2_CACHE
173 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
174 #define CONFIG_BTB /* toggle branch predition */
175 #define CONFIG_DDR_ECC
176 #ifdef CONFIG_DDR_ECC
177 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
178 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
181 #define CONFIG_ENABLE_36BIT_PHYS
184 * Config the L3 Cache as L3 SRAM
186 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
188 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
189 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
190 * (CONFIG_SYS_INIT_L3_VADDR) will be different.
192 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000
193 #define CONFIG_SYS_L3_SIZE 256 << 10
194 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
195 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
196 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
197 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
198 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
200 #define CONFIG_SYS_DCSRBAR 0xf0000000
201 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
206 #define CONFIG_VERY_BIG_RAM
207 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
208 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
210 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
211 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
213 #define CONFIG_DDR_SPD
215 #define CONFIG_SYS_SPD_BUS_NUM 0
216 #define SPD_EEPROM_ADDRESS 0x51
218 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
223 #define CONFIG_SYS_FLASH_BASE 0xe8000000
224 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
226 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
227 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
228 CSPR_PORT_SIZE_16 | \
231 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
236 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
238 /* NOR Flash Timing Params */
239 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
240 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
241 FTIM0_NOR_TEADC(0x5) | \
242 FTIM0_NOR_TEAHC(0x5))
243 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
244 FTIM1_NOR_TRAD_NOR(0x1A) |\
245 FTIM1_NOR_TSEQRAD_NOR(0x13))
246 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
247 FTIM2_NOR_TCH(0x4) | \
248 FTIM2_NOR_TWPH(0x0E) | \
250 #define CONFIG_SYS_NOR_FTIM3 0x0
252 #define CONFIG_SYS_FLASH_QUIET_TEST
253 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
255 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
256 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
257 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
258 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
260 #define CONFIG_SYS_FLASH_EMPTY_INFO
261 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
264 #define CPLD_LBMAP_MASK 0x3F
265 #define CPLD_BANK_SEL_MASK 0x07
266 #define CPLD_BANK_OVERRIDE 0x40
267 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
268 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */
269 #define CPLD_LBMAP_RESET 0xFF
270 #define CPLD_LBMAP_SHIFT 0x03
272 #if defined(CONFIG_TARGET_T1042RDB_PI)
273 #define CPLD_DIU_SEL_DFP 0x80
274 #elif defined(CONFIG_TARGET_T1042D4RDB)
275 #define CPLD_DIU_SEL_DFP 0xc0
278 #if defined(CONFIG_TARGET_T1040D4RDB)
279 #define CPLD_INT_MASK_ALL 0xFF
280 #define CPLD_INT_MASK_THERM 0x80
281 #define CPLD_INT_MASK_DVI_DFP 0x40
282 #define CPLD_INT_MASK_QSGMII1 0x20
283 #define CPLD_INT_MASK_QSGMII2 0x10
284 #define CPLD_INT_MASK_SGMI1 0x08
285 #define CPLD_INT_MASK_SGMI2 0x04
286 #define CPLD_INT_MASK_TDMR1 0x02
287 #define CPLD_INT_MASK_TDMR2 0x01
290 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
291 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
292 #define CONFIG_SYS_CSPR2_EXT (0xf)
293 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
297 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
298 #define CONFIG_SYS_CSOR2 0x0
299 /* CPLD Timing parameters for IFC CS2 */
300 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
301 FTIM0_GPCM_TEADC(0x0e) | \
302 FTIM0_GPCM_TEAHC(0x0e))
303 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
304 FTIM1_GPCM_TRAD(0x1f))
305 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
306 FTIM2_GPCM_TCH(0x8) | \
307 FTIM2_GPCM_TWP(0x1f))
308 #define CONFIG_SYS_CS2_FTIM3 0x0
310 /* NAND Flash on IFC */
311 #define CONFIG_NAND_FSL_IFC
312 #define CONFIG_SYS_NAND_BASE 0xff800000
313 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
315 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
316 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
317 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
318 | CSPR_MSEL_NAND /* MSEL = NAND */ \
320 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
322 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
323 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
324 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
325 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
326 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
327 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
328 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
330 #define CONFIG_SYS_NAND_ONFI_DETECTION
332 /* ONFI NAND Flash mode0 Timing Params */
333 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
334 FTIM0_NAND_TWP(0x18) | \
335 FTIM0_NAND_TWCHT(0x07) | \
336 FTIM0_NAND_TWH(0x0a))
337 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
338 FTIM1_NAND_TWBE(0x39) | \
339 FTIM1_NAND_TRR(0x0e) | \
340 FTIM1_NAND_TRP(0x18))
341 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
342 FTIM2_NAND_TREH(0x0a) | \
343 FTIM2_NAND_TWHRE(0x1e))
344 #define CONFIG_SYS_NAND_FTIM3 0x0
346 #define CONFIG_SYS_NAND_DDR_LAW 11
347 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
348 #define CONFIG_SYS_MAX_NAND_DEVICE 1
350 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
352 #if defined(CONFIG_MTD_RAW_NAND)
353 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
354 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
355 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
356 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
357 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
358 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
359 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
360 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
361 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
362 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
363 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
364 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
365 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
366 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
367 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
368 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
370 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
371 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
372 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
373 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
374 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
375 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
376 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
377 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
378 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
379 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
380 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
381 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
382 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
383 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
384 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
385 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
388 #ifdef CONFIG_SPL_BUILD
389 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
391 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
394 #if defined(CONFIG_RAMBOOT_PBL)
395 #define CONFIG_SYS_RAMBOOT
398 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044
399 #if defined(CONFIG_MTD_RAW_NAND)
400 #define CONFIG_A008044_WORKAROUND
404 #define CONFIG_HWCONFIG
406 /* define to use L1 as initial stack */
407 #define CONFIG_L1_INIT_RAM
408 #define CONFIG_SYS_INIT_RAM_LOCK
409 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
410 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
411 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
412 /* The assembler doesn't like typecast */
413 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
414 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
415 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
416 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
418 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
419 GENERATED_GBL_DATA_SIZE)
420 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
422 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
423 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
425 /* Serial Port - controlled on board with jumper J8
429 #define CONFIG_SYS_NS16550_SERIAL
430 #define CONFIG_SYS_NS16550_REG_SIZE 1
431 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
433 #define CONFIG_SYS_BAUDRATE_TABLE \
434 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
436 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
437 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
438 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
439 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
441 #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB)
443 #define CONFIG_FSL_DIU_FB
445 #ifdef CONFIG_FSL_DIU_FB
446 #define CONFIG_FSL_DIU_CH7301
447 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
448 #define CONFIG_VIDEO_LOGO
449 #define CONFIG_VIDEO_BMP_LOGO
455 /* I2C bus multiplexer */
456 #define I2C_MUX_PCA_ADDR 0x70
457 #define I2C_MUX_CH_DEFAULT 0x8
459 #if defined(CONFIG_TARGET_T1042RDB_PI) || \
460 defined(CONFIG_TARGET_T1040D4RDB) || \
461 defined(CONFIG_TARGET_T1042D4RDB)
462 /* LDI/DVI Encoder for display */
463 #define CONFIG_SYS_I2C_LDI_ADDR 0x38
464 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
465 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0
471 #define CONFIG_RTC_DS1337 1
472 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
475 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
479 * eSPI - Enhanced SPI
484 * Memory space is mapped 1-1, but I/O space must start from 0.
488 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
490 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
491 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
492 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
493 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
496 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
498 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
499 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
500 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
501 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
504 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
506 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
507 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
508 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
509 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
512 /* controller 4, Base address 203000 */
514 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
515 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
516 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
517 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
520 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
521 #endif /* CONFIG_PCI */
524 #define CONFIG_FSL_SATA_V2
525 #ifdef CONFIG_FSL_SATA_V2
526 #define CONFIG_SYS_SATA_MAX_DEVICE 1
528 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
529 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
537 #define CONFIG_HAS_FSL_DR_USB
539 #ifdef CONFIG_HAS_FSL_DR_USB
540 #ifdef CONFIG_USB_EHCI_HCD
541 #define CONFIG_USB_EHCI_FSL
542 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
547 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
551 #ifndef CONFIG_NOBQFMAN
552 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
553 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
554 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
555 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
556 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
557 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
558 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
559 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
560 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
561 CONFIG_SYS_BMAN_CENA_SIZE)
562 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
563 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
564 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
565 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
566 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
567 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
568 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
569 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
570 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
571 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
572 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
573 CONFIG_SYS_QMAN_CENA_SIZE)
574 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
575 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
577 #define CONFIG_SYS_DPAA_FMAN
578 #define CONFIG_SYS_DPAA_PME
582 /* Default address of microcode for the Linux Fman driver */
583 #if defined(CONFIG_SPIFLASH)
585 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
586 * env, so we got 0x110000.
588 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
589 #elif defined(CONFIG_SDCARD)
591 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
592 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
593 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
595 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
596 #elif defined(CONFIG_MTD_RAW_NAND)
597 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
599 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
602 #if defined(CONFIG_SPIFLASH)
603 #define CONFIG_SYS_QE_FW_ADDR 0x130000
604 #elif defined(CONFIG_SDCARD)
605 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
606 #elif defined(CONFIG_MTD_RAW_NAND)
607 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
609 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
612 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
613 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
614 #endif /* CONFIG_NOBQFMAN */
616 #ifdef CONFIG_FMAN_ENET
617 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
618 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
619 #elif defined(CONFIG_TARGET_T1040D4RDB)
620 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01
621 #elif defined(CONFIG_TARGET_T1042D4RDB)
622 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02
623 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03
624 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01
627 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
628 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04
629 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05
631 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
632 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
635 /* Enable VSC9953 L2 Switch driver on T1040 SoC */
636 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
637 #define CONFIG_VSC9953
638 #ifdef CONFIG_TARGET_T1040RDB
639 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
640 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
642 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
643 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
647 #define CONFIG_ETHPRIME "FM1@DTSEC4"
653 #define CONFIG_LOADS_ECHO /* echo on for serial download */
654 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
657 * Miscellaneous configurable options
659 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
662 * For booting Linux, the board info and command line data
663 * have to be in the first 64 MB of memory, since this is
664 * the maximum mapped by the Linux kernel during initialization.
666 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
667 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
669 #ifdef CONFIG_CMD_KGDB
670 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
674 * Dynamic MTD Partition support with mtdparts
678 * Environment Configuration
680 #define CONFIG_ROOTPATH "/opt/nfsroot"
681 #define CONFIG_BOOTFILE "uImage"
682 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
684 /* default location for tftp and bootm */
685 #define CONFIG_LOADADDR 1000000
687 #define __USB_PHY_TYPE utmi
688 #define RAMDISKFILE "t104xrdb/ramdisk.uboot"
690 #ifdef CONFIG_TARGET_T1040RDB
691 #define FDTFILE "t1040rdb/t1040rdb.dtb"
692 #elif defined(CONFIG_TARGET_T1042RDB_PI)
693 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
694 #elif defined(CONFIG_TARGET_T1042RDB)
695 #define FDTFILE "t1042rdb/t1042rdb.dtb"
696 #elif defined(CONFIG_TARGET_T1040D4RDB)
697 #define FDTFILE "t1042rdb/t1040d4rdb.dtb"
698 #elif defined(CONFIG_TARGET_T1042D4RDB)
699 #define FDTFILE "t1042rdb/t1042d4rdb.dtb"
702 #ifdef CONFIG_FSL_DIU_FB
703 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
705 #define DIU_ENVIRONMENT
708 #define CONFIG_EXTRA_ENV_SETTINGS \
709 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
710 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
711 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
713 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \
714 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
715 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
716 "tftpflash=tftpboot $loadaddr $uboot && " \
717 "protect off $ubootaddr +$filesize && " \
718 "erase $ubootaddr +$filesize && " \
719 "cp.b $loadaddr $ubootaddr $filesize && " \
720 "protect on $ubootaddr +$filesize && " \
721 "cmp.b $loadaddr $ubootaddr $filesize\0" \
722 "consoledev=ttyS0\0" \
723 "ramdiskaddr=2000000\0" \
724 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
725 "fdtaddr=1e00000\0" \
726 "fdtfile=" __stringify(FDTFILE) "\0" \
729 #define LINUXBOOTCOMMAND \
730 "setenv bootargs root=/dev/ram rw " \
731 "console=$consoledev,$baudrate $othbootargs;" \
732 "setenv ramdiskaddr 0x02000000;" \
733 "setenv fdtaddr 0x00c00000;" \
734 "setenv loadaddr 0x1000000;" \
735 "bootm $loadaddr $ramdiskaddr $fdtaddr"
738 "setenv bootargs root=/dev/$bdev rw " \
739 "console=$consoledev,$baudrate $othbootargs;" \
740 "tftp $loadaddr $bootfile;" \
741 "tftp $fdtaddr $fdtfile;" \
742 "bootm $loadaddr - $fdtaddr"
744 #define NFSBOOTCOMMAND \
745 "setenv bootargs root=/dev/nfs rw " \
746 "nfsroot=$serverip:$rootpath " \
747 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
748 "console=$consoledev,$baudrate $othbootargs;" \
749 "tftp $loadaddr $bootfile;" \
750 "tftp $fdtaddr $fdtfile;" \
751 "bootm $loadaddr - $fdtaddr"
753 #define RAMBOOTCOMMAND \
754 "setenv bootargs root=/dev/ram rw " \
755 "console=$consoledev,$baudrate $othbootargs;" \
756 "tftp $ramdiskaddr $ramdiskfile;" \
757 "tftp $loadaddr $bootfile;" \
758 "tftp $fdtaddr $fdtfile;" \
759 "bootm $loadaddr $ramdiskaddr $fdtaddr"
761 #define CONFIG_BOOTCOMMAND LINUXBOOTCOMMAND
763 #include <asm/fsl_secure_boot.h>
765 #endif /* __CONFIG_H */