include/configs/T104xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #include <linux/stringify.h>
  11
  12 /*
  13  * T104x RDB board configuration file
  14  */
  15 #include <asm/config_mpc85xx.h>
  16
  17 #ifdef CONFIG_RAMBOOT_PBL
  18
  19 #ifndef CONFIG_NXP_ESBC
  20 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
  21 #else
  22 #define CONFIG_SYS_FSL_PBL_PBI \
  23                 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg
  24 #endif
  25
  26 #define CONFIG_SPL_FLUSH_IMAGE
  27 #define CONFIG_SPL_PAD_TO               0x40000
  28 #define CONFIG_SPL_MAX_SIZE             0x28000
  29 #ifdef CONFIG_SPL_BUILD
  30 #define CONFIG_SPL_SKIP_RELOCATE
  31 #define CONFIG_SPL_COMMON_INIT_DDR
  32 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  33 #undef CONFIG_DM_I2C
  34 #endif
  35 #define RESET_VECTOR_OFFSET             0x27FFC
  36 #define BOOT_PAGE_OFFSET                0x27000
  37
  38 #ifdef CONFIG_MTD_RAW_NAND
  39 #ifdef CONFIG_NXP_ESBC
  40 #define CONFIG_U_BOOT_HDR_SIZE          (16 << 10)
  41 /*
  42  * HDR would be appended at end of image and copied to DDR along
  43  * with U-Boot image.
  44  */
  45 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) + \
  46                                          CONFIG_U_BOOT_HDR_SIZE)
  47 #else
  48 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  49 #endif
  50 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  51 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  52 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  53 #ifdef CONFIG_TARGET_T1040RDB
  54 #define CONFIG_SYS_FSL_PBL_RCW \
  55 $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg
  56 #endif
  57 #ifdef CONFIG_TARGET_T1042RDB_PI
  58 #define CONFIG_SYS_FSL_PBL_RCW \
  59 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
  60 #endif
  61 #ifdef CONFIG_TARGET_T1042RDB
  62 #define CONFIG_SYS_FSL_PBL_RCW \
  63 $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg
  64 #endif
  65 #ifdef CONFIG_TARGET_T1040D4RDB
  66 #define CONFIG_SYS_FSL_PBL_RCW \
  67 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
  68 #endif
  69 #ifdef CONFIG_TARGET_T1042D4RDB
  70 #define CONFIG_SYS_FSL_PBL_RCW \
  71 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
  72 #endif
  73 #endif
  74
  75 #ifdef CONFIG_SPIFLASH
  76 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  77 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  78 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  79 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  80 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  81 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  82 #ifndef CONFIG_SPL_BUILD
  83 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  84 #endif
  85 #ifdef CONFIG_TARGET_T1040RDB
  86 #define CONFIG_SYS_FSL_PBL_RCW \
  87 $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg
  88 #endif
  89 #ifdef CONFIG_TARGET_T1042RDB_PI
  90 #define CONFIG_SYS_FSL_PBL_RCW \
  91 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
  92 #endif
  93 #ifdef CONFIG_TARGET_T1042RDB
  94 #define CONFIG_SYS_FSL_PBL_RCW \
  95 $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg
  96 #endif
  97 #ifdef CONFIG_TARGET_T1040D4RDB
  98 #define CONFIG_SYS_FSL_PBL_RCW \
  99 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
 100 #endif
 101 #ifdef CONFIG_TARGET_T1042D4RDB
 102 #define CONFIG_SYS_FSL_PBL_RCW \
 103 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
 104 #endif
 105 #endif
 106
 107 #ifdef CONFIG_SDCARD
 108 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
 109 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
 110 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
 111 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
 112 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
 113 #ifndef CONFIG_SPL_BUILD
 114 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 115 #endif
 116 #ifdef CONFIG_TARGET_T1040RDB
 117 #define CONFIG_SYS_FSL_PBL_RCW \
 118 $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg
 119 #endif
 120 #ifdef CONFIG_TARGET_T1042RDB_PI
 121 #define CONFIG_SYS_FSL_PBL_RCW \
 122 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
 123 #endif
 124 #ifdef CONFIG_TARGET_T1042RDB
 125 #define CONFIG_SYS_FSL_PBL_RCW \
 126 $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg
 127 #endif
 128 #ifdef CONFIG_TARGET_T1040D4RDB
 129 #define CONFIG_SYS_FSL_PBL_RCW \
 130 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
 131 #endif
 132 #ifdef CONFIG_TARGET_T1042D4RDB
 133 #define CONFIG_SYS_FSL_PBL_RCW \
 134 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
 135 #endif
 136 #endif
 137
 138 #endif
 139
 140 /* High Level Configuration Options */
 141 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
 142
 143 /* support deep sleep */
 144 #define CONFIG_DEEP_SLEEP
 145
 146 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 147 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 148 #endif
 149
 150 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
 151 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
 152 #define CONFIG_PCIE1                    /* PCIE controller 1 */
 153 #define CONFIG_PCIE2                    /* PCIE controller 2 */
 154 #define CONFIG_PCIE3                    /* PCIE controller 3 */
 155 #define CONFIG_PCIE4                    /* PCIE controller 4 */
 156
 157 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
 158
 159 #if defined(CONFIG_SPIFLASH)
 160 #elif defined(CONFIG_SDCARD)
 161 #define CONFIG_SYS_MMC_ENV_DEV          0
 162 #elif defined(CONFIG_MTD_RAW_NAND)
 163 #ifdef CONFIG_NXP_ESBC
 164 #define CONFIG_RAMBOOT_NAND
 165 #define CONFIG_BOOTSCRIPT_COPY_RAM
 166 #endif
 167 #endif
 168
 169 #define CONFIG_SYS_CLK_FREQ     100000000
 170 #define CONFIG_DDR_CLK_FREQ     66666666
 171
 172 /*
 173  * These can be toggled for performance analysis, otherwise use default.
 174  */
 175 #define CONFIG_SYS_CACHE_STASHING
 176 #define CONFIG_BACKSIDE_L2_CACHE
 177 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 178 #define CONFIG_BTB                      /* toggle branch predition */
 179 #define CONFIG_DDR_ECC
 180 #ifdef CONFIG_DDR_ECC
 181 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 182 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 183 #endif
 184
 185 #define CONFIG_ENABLE_36BIT_PHYS
 186
 187 /*
 188  *  Config the L3 Cache as L3 SRAM
 189  */
 190 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 191 /*
 192  * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
 193  * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
 194  * (CONFIG_SYS_INIT_L3_VADDR) will be different.
 195  */
 196 #define CONFIG_SYS_INIT_L3_VADDR        0xFFFC0000
 197 #define CONFIG_SYS_L3_SIZE              256 << 10
 198 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
 199 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
 200 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 201 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 202 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 203
 204 #define CONFIG_SYS_DCSRBAR              0xf0000000
 205 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 206
 207 /*
 208  * DDR Setup
 209  */
 210 #define CONFIG_VERY_BIG_RAM
 211 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 212 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 213
 214 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 215 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 216
 217 #define CONFIG_DDR_SPD
 218
 219 #define CONFIG_SYS_SPD_BUS_NUM  0
 220 #define SPD_EEPROM_ADDRESS      0x51
 221
 222 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 223
 224 /*
 225  * IFC Definitions
 226  */
 227 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 228 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 229
 230 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
 231 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
 232                                 CSPR_PORT_SIZE_16 | \
 233                                 CSPR_MSEL_NOR | \
 234                                 CSPR_V)
 235 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 236
 237 /*
 238  * TDM Definition
 239  */
 240 #define T1040_TDM_QUIRK_CCSR_BASE       0xfe000000
 241
 242 /* NOR Flash Timing Params */
 243 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 244 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 245                                 FTIM0_NOR_TEADC(0x5) | \
 246                                 FTIM0_NOR_TEAHC(0x5))
 247 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 248                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 249                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 250 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 251                                 FTIM2_NOR_TCH(0x4) | \
 252                                 FTIM2_NOR_TWPH(0x0E) | \
 253                                 FTIM2_NOR_TWP(0x1c))
 254 #define CONFIG_SYS_NOR_FTIM3    0x0
 255
 256 #define CONFIG_SYS_FLASH_QUIET_TEST
 257 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 258
 259 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 260 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 261 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 262 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 263
 264 #define CONFIG_SYS_FLASH_EMPTY_INFO
 265 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 266
 267 /* CPLD on IFC */
 268 #define CPLD_LBMAP_MASK                 0x3F
 269 #define CPLD_BANK_SEL_MASK              0x07
 270 #define CPLD_BANK_OVERRIDE              0x40
 271 #define CPLD_LBMAP_ALTBANK              0x44 /* BANK OR | BANK 4 */
 272 #define CPLD_LBMAP_DFLTBANK             0x40 /* BANK OR | BANK0 */
 273 #define CPLD_LBMAP_RESET                0xFF
 274 #define CPLD_LBMAP_SHIFT                0x03
 275
 276 #if defined(CONFIG_TARGET_T1042RDB_PI)
 277 #define CPLD_DIU_SEL_DFP                0x80
 278 #elif defined(CONFIG_TARGET_T1042D4RDB)
 279 #define CPLD_DIU_SEL_DFP                0xc0
 280 #endif
 281
 282 #if defined(CONFIG_TARGET_T1040D4RDB)
 283 #define CPLD_INT_MASK_ALL               0xFF
 284 #define CPLD_INT_MASK_THERM             0x80
 285 #define CPLD_INT_MASK_DVI_DFP           0x40
 286 #define CPLD_INT_MASK_QSGMII1           0x20
 287 #define CPLD_INT_MASK_QSGMII2           0x10
 288 #define CPLD_INT_MASK_SGMI1             0x08
 289 #define CPLD_INT_MASK_SGMI2             0x04
 290 #define CPLD_INT_MASK_TDMR1             0x02
 291 #define CPLD_INT_MASK_TDMR2             0x01
 292 #endif
 293
 294 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 295 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 296 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 297 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 298                                 | CSPR_PORT_SIZE_8 \
 299                                 | CSPR_MSEL_GPCM \
 300                                 | CSPR_V)
 301 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 302 #define CONFIG_SYS_CSOR2        0x0
 303 /* CPLD Timing parameters for IFC CS2 */
 304 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 305                                         FTIM0_GPCM_TEADC(0x0e) | \
 306                                         FTIM0_GPCM_TEAHC(0x0e))
 307 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 308                                         FTIM1_GPCM_TRAD(0x1f))
 309 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 310                                         FTIM2_GPCM_TCH(0x8) | \
 311                                         FTIM2_GPCM_TWP(0x1f))
 312 #define CONFIG_SYS_CS2_FTIM3            0x0
 313
 314 /* NAND Flash on IFC */
 315 #define CONFIG_NAND_FSL_IFC
 316 #define CONFIG_SYS_NAND_BASE            0xff800000
 317 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 318
 319 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 320 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 321                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 322                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 323                                 | CSPR_V)
 324 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 325
 326 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 327                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 328                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 329                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 330                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 331                                 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
 332                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 333
 334 #define CONFIG_SYS_NAND_ONFI_DETECTION
 335
 336 /* ONFI NAND Flash mode0 Timing Params */
 337 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 338                                         FTIM0_NAND_TWP(0x18)   | \
 339                                         FTIM0_NAND_TWCHT(0x07) | \
 340                                         FTIM0_NAND_TWH(0x0a))
 341 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 342                                         FTIM1_NAND_TWBE(0x39)  | \
 343                                         FTIM1_NAND_TRR(0x0e)   | \
 344                                         FTIM1_NAND_TRP(0x18))
 345 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 346                                         FTIM2_NAND_TREH(0x0a) | \
 347                                         FTIM2_NAND_TWHRE(0x1e))
 348 #define CONFIG_SYS_NAND_FTIM3           0x0
 349
 350 #define CONFIG_SYS_NAND_DDR_LAW         11
 351 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 352 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 353
 354 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 355
 356 #if defined(CONFIG_MTD_RAW_NAND)
 357 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 358 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 359 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 360 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 361 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 362 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 363 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 364 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 365 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR_CSPR_EXT
 366 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 367 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 368 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 369 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 370 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 371 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 372 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 373 #else
 374 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 375 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 376 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 377 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 378 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 379 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 380 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 381 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 382 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 383 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 384 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 385 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 386 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 387 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 388 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 389 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 390 #endif
 391
 392 #ifdef CONFIG_SPL_BUILD
 393 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 394 #else
 395 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 396 #endif
 397
 398 #if defined(CONFIG_RAMBOOT_PBL)
 399 #define CONFIG_SYS_RAMBOOT
 400 #endif
 401
 402 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044
 403 #if defined(CONFIG_MTD_RAW_NAND)
 404 #define CONFIG_A008044_WORKAROUND
 405 #endif
 406 #endif
 407
 408 #define CONFIG_HWCONFIG
 409
 410 /* define to use L1 as initial stack */
 411 #define CONFIG_L1_INIT_RAM
 412 #define CONFIG_SYS_INIT_RAM_LOCK
 413 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 414 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 415 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 416 /* The assembler doesn't like typecast */
 417 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 418         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 419           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 420 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 421
 422 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 423                                         GENERATED_GBL_DATA_SIZE)
 424 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 425
 426 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 427 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 428
 429 /* Serial Port - controlled on board with jumper J8
 430  * open - index 2
 431  * shorted - index 1
 432  */
 433 #define CONFIG_SYS_NS16550_SERIAL
 434 #define CONFIG_SYS_NS16550_REG_SIZE     1
 435 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 436
 437 #define CONFIG_SYS_BAUDRATE_TABLE       \
 438         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 439
 440 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 441 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 442 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 443 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 444
 445 #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB)
 446 /* Video */
 447 #define CONFIG_FSL_DIU_FB
 448
 449 #ifdef CONFIG_FSL_DIU_FB
 450 #define CONFIG_FSL_DIU_CH7301
 451 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 452 #define CONFIG_VIDEO_LOGO
 453 #define CONFIG_VIDEO_BMP_LOGO
 454 #endif
 455 #endif
 456
 457 /* I2C */
 458 #ifndef CONFIG_DM_I2C
 459 #define CONFIG_SYS_I2C
 460 #define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C speed in Hz */
 461 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 462 #define CONFIG_SYS_FSL_I2C3_SPEED       400000
 463 #define CONFIG_SYS_FSL_I2C4_SPEED       400000
 464 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 465 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 466 #define CONFIG_SYS_FSL_I2C3_SLAVE       0x7F
 467 #define CONFIG_SYS_FSL_I2C4_SLAVE       0x7F
 468 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 469 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 470 #define CONFIG_SYS_FSL_I2C3_OFFSET      0x119000
 471 #define CONFIG_SYS_FSL_I2C4_OFFSET      0x119100
 472 #else
 473 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
 474 #define CONFIG_I2C_DEFAULT_BUS_NUMBER   0
 475 #endif
 476
 477 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 478 /* I2C bus multiplexer */
 479 #define I2C_MUX_PCA_ADDR                0x70
 480 #define I2C_MUX_CH_DEFAULT      0x8
 481
 482 #if defined(CONFIG_TARGET_T1042RDB_PI)  || \
 483         defined(CONFIG_TARGET_T1040D4RDB)       || \
 484         defined(CONFIG_TARGET_T1042D4RDB)
 485 /* LDI/DVI Encoder for display */
 486 #define CONFIG_SYS_I2C_LDI_ADDR         0x38
 487 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 488 #define CONFIG_SYS_I2C_DVI_BUS_NUM      0
 489
 490 /*
 491  * RTC configuration
 492  */
 493 #define RTC
 494 #define CONFIG_RTC_DS1337               1
 495 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 496
 497 /*DVI encoder*/
 498 #define CONFIG_HDMI_ENCODER_I2C_ADDR  0x75
 499 #endif
 500
 501 /*
 502  * eSPI - Enhanced SPI
 503  */
 504
 505 /*
 506  * General PCI
 507  * Memory space is mapped 1-1, but I/O space must start from 0.
 508  */
 509
 510 #ifdef CONFIG_PCI
 511 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 512 #ifdef CONFIG_PCIE1
 513 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 514 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 515 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 516 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 517 #endif
 518
 519 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 520 #ifdef CONFIG_PCIE2
 521 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 522 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 523 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 524 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 525 #endif
 526
 527 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 528 #ifdef CONFIG_PCIE3
 529 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 530 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 531 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 532 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 533 #endif
 534
 535 /* controller 4, Base address 203000 */
 536 #ifdef CONFIG_PCIE4
 537 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
 538 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
 539 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
 540 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 541 #endif
 542
 543 #if !defined(CONFIG_DM_PCI)
 544 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 545 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 546 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 547 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 548 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 549 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 550 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 551 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 552 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 553 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 554 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 555 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 556 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 557 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 558 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 559 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 560 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 561 #define CONFIG_PCI_INDIRECT_BRIDGE
 562 #endif
 563 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 564 #endif  /* CONFIG_PCI */
 565
 566 /* SATA */
 567 #define CONFIG_FSL_SATA_V2
 568 #ifdef CONFIG_FSL_SATA_V2
 569 #define CONFIG_SYS_SATA_MAX_DEVICE      1
 570 #define CONFIG_SATA1
 571 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 572 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 573
 574 #define CONFIG_LBA48
 575 #endif
 576
 577 /*
 578 * USB
 579 */
 580 #define CONFIG_HAS_FSL_DR_USB
 581
 582 #ifdef CONFIG_HAS_FSL_DR_USB
 583 #ifdef CONFIG_USB_EHCI_HCD
 584 #define CONFIG_USB_EHCI_FSL
 585 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 586 #endif
 587 #endif
 588
 589 #ifdef CONFIG_MMC
 590 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 591 #endif
 592
 593 /* Qman/Bman */
 594 #ifndef CONFIG_NOBQFMAN
 595 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 596 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 597 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 598 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 599 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 600 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 601 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 602 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 603 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 604                                         CONFIG_SYS_BMAN_CENA_SIZE)
 605 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 606 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 607 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 608 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 609 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 610 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 611 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 612 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 613 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 614 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 615 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 616                                         CONFIG_SYS_QMAN_CENA_SIZE)
 617 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 618 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 619
 620 #define CONFIG_SYS_DPAA_FMAN
 621 #define CONFIG_SYS_DPAA_PME
 622
 623 #define CONFIG_U_QE
 624
 625 /* Default address of microcode for the Linux Fman driver */
 626 #if defined(CONFIG_SPIFLASH)
 627 /*
 628  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 629  * env, so we got 0x110000.
 630  */
 631 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 632 #elif defined(CONFIG_SDCARD)
 633 /*
 634  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 635  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 636  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 637  */
 638 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 639 #elif defined(CONFIG_MTD_RAW_NAND)
 640 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
 641 #else
 642 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 643 #endif
 644
 645 #if defined(CONFIG_SPIFLASH)
 646 #define CONFIG_SYS_QE_FW_ADDR           0x130000
 647 #elif defined(CONFIG_SDCARD)
 648 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 649 #elif defined(CONFIG_MTD_RAW_NAND)
 650 #define CONFIG_SYS_QE_FW_ADDR           (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 651 #else
 652 #define CONFIG_SYS_QE_FW_ADDR           0xEFF10000
 653 #endif
 654
 655 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 656 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 657 #endif /* CONFIG_NOBQFMAN */
 658
 659 #ifdef CONFIG_FMAN_ENET
 660 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
 661 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x03
 662 #elif defined(CONFIG_TARGET_T1040D4RDB)
 663 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x01
 664 #elif defined(CONFIG_TARGET_T1042D4RDB)
 665 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x02
 666 #define CONFIG_SYS_SGMII2_PHY_ADDR             0x03
 667 #define CONFIG_SYS_SGMII3_PHY_ADDR             0x01
 668 #endif
 669
 670 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
 671 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x04
 672 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x05
 673 #else
 674 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x01
 675 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x02
 676 #endif
 677
 678 /* Enable VSC9953 L2 Switch driver on T1040 SoC */
 679 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
 680 #define CONFIG_VSC9953
 681 #ifdef CONFIG_TARGET_T1040RDB
 682 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x04
 683 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x08
 684 #else
 685 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x08
 686 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x0c
 687 #endif
 688 #endif
 689
 690 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 691 #endif
 692
 693 /*
 694  * Environment
 695  */
 696 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 697 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 698
 699 /*
 700  * Miscellaneous configurable options
 701  */
 702 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 703
 704 /*
 705  * For booting Linux, the board info and command line data
 706  * have to be in the first 64 MB of memory, since this is
 707  * the maximum mapped by the Linux kernel during initialization.
 708  */
 709 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 710 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 711
 712 #ifdef CONFIG_CMD_KGDB
 713 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 714 #endif
 715
 716 /*
 717  * Dynamic MTD Partition support with mtdparts
 718  */
 719
 720 /*
 721  * Environment Configuration
 722  */
 723 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 724 #define CONFIG_BOOTFILE         "uImage"
 725 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 726
 727 /* default location for tftp and bootm */
 728 #define CONFIG_LOADADDR         1000000
 729
 730 #define __USB_PHY_TYPE  utmi
 731 #define RAMDISKFILE     "t104xrdb/ramdisk.uboot"
 732
 733 #ifdef CONFIG_TARGET_T1040RDB
 734 #define FDTFILE         "t1040rdb/t1040rdb.dtb"
 735 #elif defined(CONFIG_TARGET_T1042RDB_PI)
 736 #define FDTFILE         "t1042rdb_pi/t1042rdb_pi.dtb"
 737 #elif defined(CONFIG_TARGET_T1042RDB)
 738 #define FDTFILE         "t1042rdb/t1042rdb.dtb"
 739 #elif defined(CONFIG_TARGET_T1040D4RDB)
 740 #define FDTFILE         "t1042rdb/t1040d4rdb.dtb"
 741 #elif defined(CONFIG_TARGET_T1042D4RDB)
 742 #define FDTFILE         "t1042rdb/t1042d4rdb.dtb"
 743 #endif
 744
 745 #ifdef CONFIG_FSL_DIU_FB
 746 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
 747 #else
 748 #define DIU_ENVIRONMENT
 749 #endif
 750
 751 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 752         "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;"                  \
 753         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 754         "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 755         "netdev=eth0\0"                                         \
 756         "video-mode=" __stringify(DIU_ENVIRONMENT) "\0"         \
 757         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 758         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 759         "tftpflash=tftpboot $loadaddr $uboot && "               \
 760         "protect off $ubootaddr +$filesize && "                 \
 761         "erase $ubootaddr +$filesize && "                       \
 762         "cp.b $loadaddr $ubootaddr $filesize && "               \
 763         "protect on $ubootaddr +$filesize && "                  \
 764         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 765         "consoledev=ttyS0\0"                                    \
 766         "ramdiskaddr=2000000\0"                                 \
 767         "ramdiskfile=" __stringify(RAMDISKFILE) "\0"            \
 768         "fdtaddr=1e00000\0"                                     \
 769         "fdtfile=" __stringify(FDTFILE) "\0"                    \
 770         "bdev=sda3\0"
 771
 772 #define CONFIG_LINUX                       \
 773         "setenv bootargs root=/dev/ram rw "            \
 774         "console=$consoledev,$baudrate $othbootargs;"  \
 775         "setenv ramdiskaddr 0x02000000;"               \
 776         "setenv fdtaddr 0x00c00000;"                   \
 777         "setenv loadaddr 0x1000000;"                   \
 778         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 779
 780 #define CONFIG_HDBOOT                                   \
 781         "setenv bootargs root=/dev/$bdev rw "           \
 782         "console=$consoledev,$baudrate $othbootargs;"   \
 783         "tftp $loadaddr $bootfile;"                     \
 784         "tftp $fdtaddr $fdtfile;"                       \
 785         "bootm $loadaddr - $fdtaddr"
 786
 787 #define CONFIG_NFSBOOTCOMMAND                   \
 788         "setenv bootargs root=/dev/nfs rw "     \
 789         "nfsroot=$serverip:$rootpath "          \
 790         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 791         "console=$consoledev,$baudrate $othbootargs;"   \
 792         "tftp $loadaddr $bootfile;"             \
 793         "tftp $fdtaddr $fdtfile;"               \
 794         "bootm $loadaddr - $fdtaddr"
 795
 796 #define CONFIG_RAMBOOTCOMMAND                           \
 797         "setenv bootargs root=/dev/ram rw "             \
 798         "console=$consoledev,$baudrate $othbootargs;"   \
 799         "tftp $ramdiskaddr $ramdiskfile;"               \
 800         "tftp $loadaddr $bootfile;"                     \
 801         "tftp $fdtaddr $fdtfile;"                       \
 802         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 803
 804 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 805
 806 #include <asm/fsl_secure_boot.h>
 807
 808 #endif  /* __CONFIG_H */