include/configs/T104xRDB.h

   1 /*
   2 + * Copyright 2014 Freescale Semiconductor, Inc.
   3 + *
   4 + * SPDX-License-Identifier:     GPL-2.0+
   5 + */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 /*
  11  * T104x RDB board configuration file
  12  */
  13 #define CONFIG_T104xRDB
  14
  15 #define CONFIG_E500                     /* BOOKE e500 family */
  16 #include <asm/config_mpc85xx.h>
  17
  18 #ifdef CONFIG_RAMBOOT_PBL
  19
  20 #ifndef CONFIG_SECURE_BOOT
  21 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
  22 #else
  23 #define CONFIG_SYS_FSL_PBL_PBI \
  24                 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg
  25 #endif
  26
  27 #ifdef CONFIG_T1040RDB
  28 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg
  29 #endif
  30 #ifdef CONFIG_T1042RDB_PI
  31 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_rcw.cfg
  32 #endif
  33 #ifdef CONFIG_T1042RDB
  34 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg
  35 #endif
  36 #ifdef CONFIG_T1040D4RDB
  37 #define CONFIG_SYS_FSL_PBL_RCW \
  38 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_rcw.cfg
  39 #endif
  40 #ifdef CONFIG_T1042D4RDB
  41 #define CONFIG_SYS_FSL_PBL_RCW \
  42 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
  43 #endif
  44
  45 #define CONFIG_SPL_FLUSH_IMAGE
  46 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  47 #define CONFIG_FSL_LAW                 /* Use common FSL init code */
  48 #define CONFIG_SYS_TEXT_BASE            0x30001000
  49 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  50 #define CONFIG_SPL_PAD_TO               0x40000
  51 #define CONFIG_SPL_MAX_SIZE             0x28000
  52 #ifdef CONFIG_SPL_BUILD
  53 #define CONFIG_SPL_SKIP_RELOCATE
  54 #define CONFIG_SPL_COMMON_INIT_DDR
  55 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  56 #define CONFIG_SYS_NO_FLASH
  57 #endif
  58 #define RESET_VECTOR_OFFSET             0x27FFC
  59 #define BOOT_PAGE_OFFSET                0x27000
  60
  61 #ifdef CONFIG_NAND
  62 #ifdef CONFIG_SECURE_BOOT
  63 #define CONFIG_U_BOOT_HDR_SIZE          (16 << 10)
  64 /*
  65  * HDR would be appended at end of image and copied to DDR along
  66  * with U-Boot image.
  67  */
  68 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) + \
  69                                          CONFIG_U_BOOT_HDR_SIZE)
  70 #else
  71 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  72 #endif
  73 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  74 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  75 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  76 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  77 #define CONFIG_SPL_NAND_BOOT
  78 #endif
  79
  80 #ifdef CONFIG_SPIFLASH
  81 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  82 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  83 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  84 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  85 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  86 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  87 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  88 #ifndef CONFIG_SPL_BUILD
  89 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  90 #endif
  91 #define CONFIG_SPL_SPI_BOOT
  92 #endif
  93
  94 #ifdef CONFIG_SDCARD
  95 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  96 #define CONFIG_SPL_MMC_MINIMAL
  97 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  98 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
  99 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
 100 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
 101 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
 102 #ifndef CONFIG_SPL_BUILD
 103 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 104 #endif
 105 #define CONFIG_SPL_MMC_BOOT
 106 #endif
 107
 108 #endif
 109
 110 /* High Level Configuration Options */
 111 #define CONFIG_BOOKE
 112 #define CONFIG_E500MC                   /* BOOKE e500mc family */
 113 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
 114 #define CONFIG_MP                       /* support multiple processors */
 115
 116 /* support deep sleep */
 117 #define CONFIG_DEEP_SLEEP
 118 #if defined(CONFIG_DEEP_SLEEP)
 119 #define CONFIG_BOARD_EARLY_INIT_F
 120 #define CONFIG_SILENT_CONSOLE
 121 #endif
 122
 123 #ifndef CONFIG_SYS_TEXT_BASE
 124 #define CONFIG_SYS_TEXT_BASE    0xeff40000
 125 #endif
 126
 127 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 128 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 129 #endif
 130
 131 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
 132 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
 133 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
 134 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
 135 #define CONFIG_PCI                      /* Enable PCI/PCIE */
 136 #define CONFIG_PCI_INDIRECT_BRIDGE
 137 #define CONFIG_PCIE1                    /* PCIE controller 1 */
 138 #define CONFIG_PCIE2                    /* PCIE controller 2 */
 139 #define CONFIG_PCIE3                    /* PCIE controller 3 */
 140 #define CONFIG_PCIE4                    /* PCIE controller 4 */
 141
 142 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
 143 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
 144
 145 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
 146
 147 #define CONFIG_ENV_OVERWRITE
 148
 149 #ifndef CONFIG_SYS_NO_FLASH
 150 #define CONFIG_FLASH_CFI_DRIVER
 151 #define CONFIG_SYS_FLASH_CFI
 152 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 153 #endif
 154
 155 #if defined(CONFIG_SPIFLASH)
 156 #define CONFIG_SYS_EXTRA_ENV_RELOC
 157 #define CONFIG_ENV_IS_IN_SPI_FLASH
 158 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 159 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 160 #define CONFIG_ENV_SECT_SIZE            0x10000
 161 #elif defined(CONFIG_SDCARD)
 162 #define CONFIG_SYS_EXTRA_ENV_RELOC
 163 #define CONFIG_ENV_IS_IN_MMC
 164 #define CONFIG_SYS_MMC_ENV_DEV          0
 165 #define CONFIG_ENV_SIZE                 0x2000
 166 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 167 #elif defined(CONFIG_NAND)
 168 #ifdef CONFIG_SECURE_BOOT
 169 #define CONFIG_RAMBOOT_NAND
 170 #define CONFIG_BOOTSCRIPT_COPY_RAM
 171 #endif
 172 #define CONFIG_SYS_EXTRA_ENV_RELOC
 173 #define CONFIG_ENV_IS_IN_NAND
 174 #define CONFIG_ENV_SIZE                 0x2000
 175 #define CONFIG_ENV_OFFSET               (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 176 #else
 177 #define CONFIG_ENV_IS_IN_FLASH
 178 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 179 #define CONFIG_ENV_SIZE         0x2000
 180 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 181 #endif
 182
 183 #define CONFIG_SYS_CLK_FREQ     100000000
 184 #define CONFIG_DDR_CLK_FREQ     66666666
 185
 186 /*
 187  * These can be toggled for performance analysis, otherwise use default.
 188  */
 189 #define CONFIG_SYS_CACHE_STASHING
 190 #define CONFIG_BACKSIDE_L2_CACHE
 191 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 192 #define CONFIG_BTB                      /* toggle branch predition */
 193 #define CONFIG_DDR_ECC
 194 #ifdef CONFIG_DDR_ECC
 195 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 196 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 197 #endif
 198
 199 #define CONFIG_ENABLE_36BIT_PHYS
 200
 201 #define CONFIG_ADDR_MAP
 202 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 203
 204 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 205 #define CONFIG_SYS_MEMTEST_END          0x00400000
 206 #define CONFIG_SYS_ALT_MEMTEST
 207 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 208
 209 /*
 210  *  Config the L3 Cache as L3 SRAM
 211  */
 212 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 213 /*
 214  * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
 215  * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
 216  * (CONFIG_SYS_INIT_L3_VADDR) will be different.
 217  */
 218 #define CONFIG_SYS_INIT_L3_VADDR        0xFFFC0000
 219 #define CONFIG_SYS_L3_SIZE              256 << 10
 220 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
 221 #ifdef CONFIG_RAMBOOT_PBL
 222 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 223 #endif
 224 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 225 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 226 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 227 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 228
 229 #define CONFIG_SYS_DCSRBAR              0xf0000000
 230 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 231
 232 /*
 233  * DDR Setup
 234  */
 235 #define CONFIG_VERY_BIG_RAM
 236 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 237 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 238
 239 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
 240 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 241 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 242
 243 #define CONFIG_DDR_SPD
 244 #ifndef CONFIG_SYS_FSL_DDR4
 245 #define CONFIG_SYS_FSL_DDR3
 246 #endif
 247
 248 #define CONFIG_SYS_SPD_BUS_NUM  0
 249 #define SPD_EEPROM_ADDRESS      0x51
 250
 251 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 252
 253 /*
 254  * IFC Definitions
 255  */
 256 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 257 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 258
 259 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
 260 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
 261                                 CSPR_PORT_SIZE_16 | \
 262                                 CSPR_MSEL_NOR | \
 263                                 CSPR_V)
 264 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 265
 266 /*
 267  * TDM Definition
 268  */
 269 #define T1040_TDM_QUIRK_CCSR_BASE       0xfe000000
 270
 271 /* NOR Flash Timing Params */
 272 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 273 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 274                                 FTIM0_NOR_TEADC(0x5) | \
 275                                 FTIM0_NOR_TEAHC(0x5))
 276 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 277                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 278                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 279 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 280                                 FTIM2_NOR_TCH(0x4) | \
 281                                 FTIM2_NOR_TWPH(0x0E) | \
 282                                 FTIM2_NOR_TWP(0x1c))
 283 #define CONFIG_SYS_NOR_FTIM3    0x0
 284
 285 #define CONFIG_SYS_FLASH_QUIET_TEST
 286 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 287
 288 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 289 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 290 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 291 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 292
 293 #define CONFIG_SYS_FLASH_EMPTY_INFO
 294 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 295
 296 /* CPLD on IFC */
 297 #define CPLD_LBMAP_MASK                 0x3F
 298 #define CPLD_BANK_SEL_MASK              0x07
 299 #define CPLD_BANK_OVERRIDE              0x40
 300 #define CPLD_LBMAP_ALTBANK              0x44 /* BANK OR | BANK 4 */
 301 #define CPLD_LBMAP_DFLTBANK             0x40 /* BANK OR | BANK0 */
 302 #define CPLD_LBMAP_RESET                0xFF
 303 #define CPLD_LBMAP_SHIFT                0x03
 304
 305 #if defined(CONFIG_T1042RDB_PI)
 306 #define CPLD_DIU_SEL_DFP                0x80
 307 #elif defined(CONFIG_T1042D4RDB)
 308 #define CPLD_DIU_SEL_DFP                0xc0
 309 #endif
 310
 311 #if defined(CONFIG_T1040D4RDB)
 312 #define CPLD_INT_MASK_ALL               0xFF
 313 #define CPLD_INT_MASK_THERM             0x80
 314 #define CPLD_INT_MASK_DVI_DFP           0x40
 315 #define CPLD_INT_MASK_QSGMII1           0x20
 316 #define CPLD_INT_MASK_QSGMII2           0x10
 317 #define CPLD_INT_MASK_SGMI1             0x08
 318 #define CPLD_INT_MASK_SGMI2             0x04
 319 #define CPLD_INT_MASK_TDMR1             0x02
 320 #define CPLD_INT_MASK_TDMR2             0x01
 321 #endif
 322
 323 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 324 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 325 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 326 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 327                                 | CSPR_PORT_SIZE_8 \
 328                                 | CSPR_MSEL_GPCM \
 329                                 | CSPR_V)
 330 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 331 #define CONFIG_SYS_CSOR2        0x0
 332 /* CPLD Timing parameters for IFC CS2 */
 333 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 334                                         FTIM0_GPCM_TEADC(0x0e) | \
 335                                         FTIM0_GPCM_TEAHC(0x0e))
 336 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 337                                         FTIM1_GPCM_TRAD(0x1f))
 338 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 339                                         FTIM2_GPCM_TCH(0x8) | \
 340                                         FTIM2_GPCM_TWP(0x1f))
 341 #define CONFIG_SYS_CS2_FTIM3            0x0
 342
 343 /* NAND Flash on IFC */
 344 #define CONFIG_NAND_FSL_IFC
 345 #define CONFIG_SYS_NAND_BASE            0xff800000
 346 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 347
 348 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 349 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 350                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 351                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 352                                 | CSPR_V)
 353 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 354
 355 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 356                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 357                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 358                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 359                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 360                                 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
 361                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 362
 363 #define CONFIG_SYS_NAND_ONFI_DETECTION
 364
 365 /* ONFI NAND Flash mode0 Timing Params */
 366 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 367                                         FTIM0_NAND_TWP(0x18)   | \
 368                                         FTIM0_NAND_TWCHT(0x07) | \
 369                                         FTIM0_NAND_TWH(0x0a))
 370 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 371                                         FTIM1_NAND_TWBE(0x39)  | \
 372                                         FTIM1_NAND_TRR(0x0e)   | \
 373                                         FTIM1_NAND_TRP(0x18))
 374 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 375                                         FTIM2_NAND_TREH(0x0a) | \
 376                                         FTIM2_NAND_TWHRE(0x1e))
 377 #define CONFIG_SYS_NAND_FTIM3           0x0
 378
 379 #define CONFIG_SYS_NAND_DDR_LAW         11
 380 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 381 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 382 #define CONFIG_CMD_NAND
 383
 384 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 385
 386 #if defined(CONFIG_NAND)
 387 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 388 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 389 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 390 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 391 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 392 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 393 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 394 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 395 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR_CSPR_EXT
 396 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 397 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 398 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 399 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 400 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 401 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 402 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 403 #else
 404 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 405 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 406 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 407 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 408 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 409 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 410 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 411 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 412 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 413 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 414 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 415 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 416 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 417 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 418 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 419 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 420 #endif
 421
 422 #ifdef CONFIG_SPL_BUILD
 423 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 424 #else
 425 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 426 #endif
 427
 428 #if defined(CONFIG_RAMBOOT_PBL)
 429 #define CONFIG_SYS_RAMBOOT
 430 #endif
 431
 432 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044
 433 #if defined(CONFIG_NAND)
 434 #define CONFIG_A008044_WORKAROUND
 435 #endif
 436 #endif
 437
 438 #define CONFIG_BOARD_EARLY_INIT_R
 439 #define CONFIG_MISC_INIT_R
 440
 441 #define CONFIG_HWCONFIG
 442
 443 /* define to use L1 as initial stack */
 444 #define CONFIG_L1_INIT_RAM
 445 #define CONFIG_SYS_INIT_RAM_LOCK
 446 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 447 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 448 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 449 /* The assembler doesn't like typecast */
 450 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 451         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 452           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 453 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 454
 455 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 456                                         GENERATED_GBL_DATA_SIZE)
 457 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 458
 459 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 460 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 461
 462 /* Serial Port - controlled on board with jumper J8
 463  * open - index 2
 464  * shorted - index 1
 465  */
 466 #define CONFIG_CONS_INDEX       1
 467 #define CONFIG_SYS_NS16550_SERIAL
 468 #define CONFIG_SYS_NS16550_REG_SIZE     1
 469 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 470
 471 #define CONFIG_SYS_BAUDRATE_TABLE       \
 472         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 473
 474 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 475 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 476 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 477 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 478 #ifndef CONFIG_SPL_BUILD
 479 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
 480 #endif
 481
 482 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T1042D4RDB)
 483 /* Video */
 484 #define CONFIG_FSL_DIU_FB
 485
 486 #ifdef CONFIG_FSL_DIU_FB
 487 #define CONFIG_FSL_DIU_CH7301
 488 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 489 #define CONFIG_VIDEO
 490 #define CONFIG_CMD_BMP
 491 #define CONFIG_CFB_CONSOLE
 492 #define CONFIG_CFB_CONSOLE_ANSI
 493 #define CONFIG_VIDEO_SW_CURSOR
 494 #define CONFIG_VGA_AS_SINGLE_DEVICE
 495 #define CONFIG_VIDEO_LOGO
 496 #define CONFIG_VIDEO_BMP_LOGO
 497 #endif
 498 #endif
 499
 500 /* I2C */
 501 #define CONFIG_SYS_I2C
 502 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 503 #define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C speed in Hz */
 504 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 505 #define CONFIG_SYS_FSL_I2C3_SPEED       400000
 506 #define CONFIG_SYS_FSL_I2C4_SPEED       400000
 507 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 508 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 509 #define CONFIG_SYS_FSL_I2C3_SLAVE       0x7F
 510 #define CONFIG_SYS_FSL_I2C4_SLAVE       0x7F
 511 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 512 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 513 #define CONFIG_SYS_FSL_I2C3_OFFSET      0x119000
 514 #define CONFIG_SYS_FSL_I2C4_OFFSET      0x119100
 515
 516 /* I2C bus multiplexer */
 517 #define I2C_MUX_PCA_ADDR                0x70
 518 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
 519 #define I2C_MUX_CH_DEFAULT      0x8
 520 #endif
 521
 522 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB)
 523 /* LDI/DVI Encoder for display */
 524 #define CONFIG_SYS_I2C_LDI_ADDR         0x38
 525 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 526
 527 /*
 528  * RTC configuration
 529  */
 530 #define RTC
 531 #define CONFIG_RTC_DS1337               1
 532 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 533
 534 /*DVI encoder*/
 535 #define CONFIG_HDMI_ENCODER_I2C_ADDR  0x75
 536 #endif
 537
 538 /*
 539  * eSPI - Enhanced SPI
 540  */
 541 #define CONFIG_SPI_FLASH_BAR
 542 #define CONFIG_SF_DEFAULT_SPEED         10000000
 543 #define CONFIG_SF_DEFAULT_MODE          0
 544 #define CONFIG_ENV_SPI_BUS              0
 545 #define CONFIG_ENV_SPI_CS               0
 546 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 547 #define CONFIG_ENV_SPI_MODE             0
 548
 549 /*
 550  * General PCI
 551  * Memory space is mapped 1-1, but I/O space must start from 0.
 552  */
 553
 554 #ifdef CONFIG_PCI
 555 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 556 #ifdef CONFIG_PCIE1
 557 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 558 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 559 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 560 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 561 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 562 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 563 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 564 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 565 #endif
 566
 567 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 568 #ifdef CONFIG_PCIE2
 569 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 570 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 571 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 572 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 573 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 574 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 575 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 576 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 577 #endif
 578
 579 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 580 #ifdef CONFIG_PCIE3
 581 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 582 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 583 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 584 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 585 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 586 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 587 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 588 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 589 #endif
 590
 591 /* controller 4, Base address 203000 */
 592 #ifdef CONFIG_PCIE4
 593 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
 594 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 595 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
 596 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 597 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
 598 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 599 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 600 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 601 #endif
 602
 603 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 604
 605 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 606 #define CONFIG_DOS_PARTITION
 607 #endif  /* CONFIG_PCI */
 608
 609 /* SATA */
 610 #define CONFIG_FSL_SATA_V2
 611 #ifdef CONFIG_FSL_SATA_V2
 612 #define CONFIG_LIBATA
 613 #define CONFIG_FSL_SATA
 614
 615 #define CONFIG_SYS_SATA_MAX_DEVICE      1
 616 #define CONFIG_SATA1
 617 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 618 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 619
 620 #define CONFIG_LBA48
 621 #define CONFIG_CMD_SATA
 622 #define CONFIG_DOS_PARTITION
 623 #endif
 624
 625 /*
 626 * USB
 627 */
 628 #define CONFIG_HAS_FSL_DR_USB
 629
 630 #ifdef CONFIG_HAS_FSL_DR_USB
 631 #define CONFIG_USB_EHCI
 632
 633 #ifdef CONFIG_USB_EHCI
 634 #define CONFIG_USB_EHCI_FSL
 635 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 636 #endif
 637 #endif
 638
 639 #define CONFIG_MMC
 640
 641 #ifdef CONFIG_MMC
 642 #define CONFIG_FSL_ESDHC
 643 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 644 #define CONFIG_GENERIC_MMC
 645 #define CONFIG_DOS_PARTITION
 646 #endif
 647
 648 /* Qman/Bman */
 649 #ifndef CONFIG_NOBQFMAN
 650 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 651 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 652 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 653 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 654 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 655 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 656 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 657 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 658 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 659 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 660                                         CONFIG_SYS_BMAN_CENA_SIZE)
 661 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 662 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 663 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 664 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 665 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 666 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 667 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 668 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 669 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 670 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 671 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 672                                         CONFIG_SYS_QMAN_CENA_SIZE)
 673 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 674 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 675
 676 #define CONFIG_SYS_DPAA_FMAN
 677 #define CONFIG_SYS_DPAA_PME
 678
 679 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
 680 #define CONFIG_QE
 681 #define CONFIG_U_QE
 682 #endif
 683
 684 /* Default address of microcode for the Linux Fman driver */
 685 #if defined(CONFIG_SPIFLASH)
 686 /*
 687  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 688  * env, so we got 0x110000.
 689  */
 690 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 691 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 692 #elif defined(CONFIG_SDCARD)
 693 /*
 694  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 695  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 696  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 697  */
 698 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 699 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 700 #elif defined(CONFIG_NAND)
 701 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 702 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
 703 #else
 704 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 705 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 706 #endif
 707
 708 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
 709 #if defined(CONFIG_SPIFLASH)
 710 #define CONFIG_SYS_QE_FW_ADDR           0x130000
 711 #elif defined(CONFIG_SDCARD)
 712 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 713 #elif defined(CONFIG_NAND)
 714 #define CONFIG_SYS_QE_FW_ADDR           (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 715 #else
 716 #define CONFIG_SYS_QE_FW_ADDR           0xEFF10000
 717 #endif
 718 #endif
 719
 720 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 721 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 722 #endif /* CONFIG_NOBQFMAN */
 723
 724 #ifdef CONFIG_SYS_DPAA_FMAN
 725 #define CONFIG_FMAN_ENET
 726 #define CONFIG_PHY_VITESSE
 727 #define CONFIG_PHY_REALTEK
 728 #endif
 729
 730 #ifdef CONFIG_FMAN_ENET
 731 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
 732 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x03
 733 #elif defined(CONFIG_T1040D4RDB)
 734 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x01
 735 #elif defined(CONFIG_T1042D4RDB)
 736 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x02
 737 #define CONFIG_SYS_SGMII2_PHY_ADDR             0x03
 738 #define CONFIG_SYS_SGMII3_PHY_ADDR             0x01
 739 #endif
 740
 741 #ifdef CONFIG_T104XD4RDB
 742 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x04
 743 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x05
 744 #else
 745 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x01
 746 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x02
 747 #endif
 748
 749 /* Enable VSC9953 L2 Switch driver on T1040 SoC */
 750 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB)
 751 #define CONFIG_VSC9953
 752 #define CONFIG_CMD_ETHSW
 753 #ifdef CONFIG_T1040RDB
 754 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x04
 755 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x08
 756 #else
 757 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x08
 758 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x0c
 759 #endif
 760 #endif
 761
 762 #define CONFIG_MII              /* MII PHY management */
 763 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 764 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 765 #endif
 766
 767 /*
 768  * Environment
 769  */
 770 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 771 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 772
 773 /*
 774  * Command line configuration.
 775  */
 776 #ifdef CONFIG_T1042RDB_PI
 777 #define CONFIG_CMD_DATE
 778 #endif
 779 #define CONFIG_CMD_ERRATA
 780 #define CONFIG_CMD_IRQ
 781 #define CONFIG_CMD_REGINFO
 782
 783 #ifdef CONFIG_PCI
 784 #define CONFIG_CMD_PCI
 785 #endif
 786
 787 /* Hash command with SHA acceleration supported in hardware */
 788 #ifdef CONFIG_FSL_CAAM
 789 #define CONFIG_CMD_HASH
 790 #define CONFIG_SHA_HW_ACCEL
 791 #endif
 792
 793 /*
 794  * Miscellaneous configurable options
 795  */
 796 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 797 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 798 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 799 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 800 #ifdef CONFIG_CMD_KGDB
 801 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 802 #else
 803 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 804 #endif
 805 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 806 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 807 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 808
 809 /*
 810  * For booting Linux, the board info and command line data
 811  * have to be in the first 64 MB of memory, since this is
 812  * the maximum mapped by the Linux kernel during initialization.
 813  */
 814 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 815 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 816
 817 #ifdef CONFIG_CMD_KGDB
 818 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 819 #endif
 820
 821 /*
 822  * Dynamic MTD Partition support with mtdparts
 823  */
 824 #ifndef CONFIG_SYS_NO_FLASH
 825 #define CONFIG_MTD_DEVICE
 826 #define CONFIG_MTD_PARTITIONS
 827 #define CONFIG_CMD_MTDPARTS
 828 #define CONFIG_FLASH_CFI_MTD
 829 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
 830                         "spi0=spife110000.0"
 831 #define MTDPARTS_DEFAULT        "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
 832                                 "128k(dtb),96m(fs),-(user);"\
 833                                 "fff800000.flash:2m(uboot),9m(kernel),"\
 834                                 "128k(dtb),96m(fs),-(user);spife110000.0:" \
 835                                 "2m(uboot),9m(kernel),128k(dtb),-(user)"
 836 #endif
 837
 838 /*
 839  * Environment Configuration
 840  */
 841 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 842 #define CONFIG_BOOTFILE         "uImage"
 843 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 844
 845 /* default location for tftp and bootm */
 846 #define CONFIG_LOADADDR         1000000
 847
 848
 849 #define CONFIG_BAUDRATE 115200
 850
 851 #define __USB_PHY_TYPE  utmi
 852 #define RAMDISKFILE     "t104xrdb/ramdisk.uboot"
 853
 854 #ifdef CONFIG_T1040RDB
 855 #define FDTFILE         "t1040rdb/t1040rdb.dtb"
 856 #elif defined(CONFIG_T1042RDB_PI)
 857 #define FDTFILE         "t1042rdb_pi/t1042rdb_pi.dtb"
 858 #elif defined(CONFIG_T1042RDB)
 859 #define FDTFILE         "t1042rdb/t1042rdb.dtb"
 860 #elif defined(CONFIG_T1040D4RDB)
 861 #define FDTFILE         "t1042rdb/t1040d4rdb.dtb"
 862 #elif defined(CONFIG_T1042D4RDB)
 863 #define FDTFILE         "t1042rdb/t1042d4rdb.dtb"
 864 #endif
 865
 866 #ifdef CONFIG_FSL_DIU_FB
 867 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
 868 #else
 869 #define DIU_ENVIRONMENT
 870 #endif
 871
 872 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 873         "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;"                  \
 874         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 875         "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 876         "netdev=eth0\0"                                         \
 877         "video-mode=" __stringify(DIU_ENVIRONMENT) "\0"         \
 878         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 879         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 880         "tftpflash=tftpboot $loadaddr $uboot && "               \
 881         "protect off $ubootaddr +$filesize && "                 \
 882         "erase $ubootaddr +$filesize && "                       \
 883         "cp.b $loadaddr $ubootaddr $filesize && "               \
 884         "protect on $ubootaddr +$filesize && "                  \
 885         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 886         "consoledev=ttyS0\0"                                    \
 887         "ramdiskaddr=2000000\0"                                 \
 888         "ramdiskfile=" __stringify(RAMDISKFILE) "\0"            \
 889         "fdtaddr=1e00000\0"                                     \
 890         "fdtfile=" __stringify(FDTFILE) "\0"                    \
 891         "bdev=sda3\0"
 892
 893 #define CONFIG_LINUX                       \
 894         "setenv bootargs root=/dev/ram rw "            \
 895         "console=$consoledev,$baudrate $othbootargs;"  \
 896         "setenv ramdiskaddr 0x02000000;"               \
 897         "setenv fdtaddr 0x00c00000;"                   \
 898         "setenv loadaddr 0x1000000;"                   \
 899         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 900
 901 #define CONFIG_HDBOOT                                   \
 902         "setenv bootargs root=/dev/$bdev rw "           \
 903         "console=$consoledev,$baudrate $othbootargs;"   \
 904         "tftp $loadaddr $bootfile;"                     \
 905         "tftp $fdtaddr $fdtfile;"                       \
 906         "bootm $loadaddr - $fdtaddr"
 907
 908 #define CONFIG_NFSBOOTCOMMAND                   \
 909         "setenv bootargs root=/dev/nfs rw "     \
 910         "nfsroot=$serverip:$rootpath "          \
 911         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 912         "console=$consoledev,$baudrate $othbootargs;"   \
 913         "tftp $loadaddr $bootfile;"             \
 914         "tftp $fdtaddr $fdtfile;"               \
 915         "bootm $loadaddr - $fdtaddr"
 916
 917 #define CONFIG_RAMBOOTCOMMAND                           \
 918         "setenv bootargs root=/dev/ram rw "             \
 919         "console=$consoledev,$baudrate $othbootargs;"   \
 920         "tftp $ramdiskaddr $ramdiskfile;"               \
 921         "tftp $loadaddr $bootfile;"                     \
 922         "tftp $fdtaddr $fdtfile;"                       \
 923         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 924
 925 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 926
 927 #include <asm/fsl_secure_boot.h>
 928
 929 #endif  /* __CONFIG_H */