include/configs/T104xRDB.h

   1 /*
   2 + * Copyright 2014 Freescale Semiconductor, Inc.
   3 + *
   4 + * SPDX-License-Identifier:     GPL-2.0+
   5 + */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 /*
  11  * T104x RDB board configuration file
  12  */
  13 #define CONFIG_T104xRDB
  14 #define CONFIG_DISPLAY_BOARDINFO
  15
  16 #define CONFIG_E500                     /* BOOKE e500 family */
  17 #include <asm/config_mpc85xx.h>
  18
  19 #ifdef CONFIG_RAMBOOT_PBL
  20
  21 #ifndef CONFIG_SECURE_BOOT
  22 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
  23 #else
  24 #define CONFIG_SYS_FSL_PBL_PBI \
  25                 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg
  26 #endif
  27
  28 #ifdef CONFIG_T1040RDB
  29 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg
  30 #endif
  31 #ifdef CONFIG_T1042RDB_PI
  32 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_rcw.cfg
  33 #endif
  34 #ifdef CONFIG_T1042RDB
  35 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg
  36 #endif
  37 #ifdef CONFIG_T1040D4RDB
  38 #define CONFIG_SYS_FSL_PBL_RCW \
  39 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_rcw.cfg
  40 #endif
  41 #ifdef CONFIG_T1042D4RDB
  42 #define CONFIG_SYS_FSL_PBL_RCW \
  43 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
  44 #endif
  45
  46 #define CONFIG_SPL_FLUSH_IMAGE
  47 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  48 #define CONFIG_FSL_LAW                 /* Use common FSL init code */
  49 #define CONFIG_SYS_TEXT_BASE            0x30001000
  50 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  51 #define CONFIG_SPL_PAD_TO               0x40000
  52 #define CONFIG_SPL_MAX_SIZE             0x28000
  53 #ifdef CONFIG_SPL_BUILD
  54 #define CONFIG_SPL_SKIP_RELOCATE
  55 #define CONFIG_SPL_COMMON_INIT_DDR
  56 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  57 #define CONFIG_SYS_NO_FLASH
  58 #endif
  59 #define RESET_VECTOR_OFFSET             0x27FFC
  60 #define BOOT_PAGE_OFFSET                0x27000
  61
  62 #ifdef CONFIG_NAND
  63 #ifdef CONFIG_SECURE_BOOT
  64 #define CONFIG_U_BOOT_HDR_SIZE          (16 << 10)
  65 /*
  66  * HDR would be appended at end of image and copied to DDR along
  67  * with U-Boot image.
  68  */
  69 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) + \
  70                                          CONFIG_U_BOOT_HDR_SIZE)
  71 #else
  72 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  73 #endif
  74 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  75 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  76 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  77 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  78 #define CONFIG_SPL_NAND_BOOT
  79 #endif
  80
  81 #ifdef CONFIG_SPIFLASH
  82 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  83 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  84 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  85 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  86 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  87 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  88 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  89 #ifndef CONFIG_SPL_BUILD
  90 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  91 #endif
  92 #define CONFIG_SPL_SPI_BOOT
  93 #endif
  94
  95 #ifdef CONFIG_SDCARD
  96 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  97 #define CONFIG_SPL_MMC_MINIMAL
  98 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  99 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
 100 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
 101 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
 102 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
 103 #ifndef CONFIG_SPL_BUILD
 104 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 105 #endif
 106 #define CONFIG_SPL_MMC_BOOT
 107 #endif
 108
 109 #endif
 110
 111 /* High Level Configuration Options */
 112 #define CONFIG_BOOKE
 113 #define CONFIG_E500MC                   /* BOOKE e500mc family */
 114 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
 115 #define CONFIG_MP                       /* support multiple processors */
 116
 117 /* support deep sleep */
 118 #define CONFIG_DEEP_SLEEP
 119 #if defined(CONFIG_DEEP_SLEEP)
 120 #define CONFIG_BOARD_EARLY_INIT_F
 121 #define CONFIG_SILENT_CONSOLE
 122 #endif
 123
 124 #ifndef CONFIG_SYS_TEXT_BASE
 125 #define CONFIG_SYS_TEXT_BASE    0xeff40000
 126 #endif
 127
 128 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 129 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 130 #endif
 131
 132 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
 133 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
 134 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
 135 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
 136 #define CONFIG_PCI                      /* Enable PCI/PCIE */
 137 #define CONFIG_PCI_INDIRECT_BRIDGE
 138 #define CONFIG_PCIE1                    /* PCIE controller 1 */
 139 #define CONFIG_PCIE2                    /* PCIE controller 2 */
 140 #define CONFIG_PCIE3                    /* PCIE controller 3 */
 141 #define CONFIG_PCIE4                    /* PCIE controller 4 */
 142
 143 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
 144 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
 145
 146 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
 147
 148 #define CONFIG_ENV_OVERWRITE
 149
 150 #ifndef CONFIG_SYS_NO_FLASH
 151 #define CONFIG_FLASH_CFI_DRIVER
 152 #define CONFIG_SYS_FLASH_CFI
 153 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 154 #endif
 155
 156 #if defined(CONFIG_SPIFLASH)
 157 #define CONFIG_SYS_EXTRA_ENV_RELOC
 158 #define CONFIG_ENV_IS_IN_SPI_FLASH
 159 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 160 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 161 #define CONFIG_ENV_SECT_SIZE            0x10000
 162 #elif defined(CONFIG_SDCARD)
 163 #define CONFIG_SYS_EXTRA_ENV_RELOC
 164 #define CONFIG_ENV_IS_IN_MMC
 165 #define CONFIG_SYS_MMC_ENV_DEV          0
 166 #define CONFIG_ENV_SIZE                 0x2000
 167 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 168 #elif defined(CONFIG_NAND)
 169 #ifdef CONFIG_SECURE_BOOT
 170 #define CONFIG_RAMBOOT_NAND
 171 #define CONFIG_BOOTSCRIPT_COPY_RAM
 172 #endif
 173 #define CONFIG_SYS_EXTRA_ENV_RELOC
 174 #define CONFIG_ENV_IS_IN_NAND
 175 #define CONFIG_ENV_SIZE                 0x2000
 176 #define CONFIG_ENV_OFFSET               (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 177 #else
 178 #define CONFIG_ENV_IS_IN_FLASH
 179 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 180 #define CONFIG_ENV_SIZE         0x2000
 181 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 182 #endif
 183
 184 #define CONFIG_SYS_CLK_FREQ     100000000
 185 #define CONFIG_DDR_CLK_FREQ     66666666
 186
 187 /*
 188  * These can be toggled for performance analysis, otherwise use default.
 189  */
 190 #define CONFIG_SYS_CACHE_STASHING
 191 #define CONFIG_BACKSIDE_L2_CACHE
 192 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 193 #define CONFIG_BTB                      /* toggle branch predition */
 194 #define CONFIG_DDR_ECC
 195 #ifdef CONFIG_DDR_ECC
 196 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 197 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 198 #endif
 199
 200 #define CONFIG_ENABLE_36BIT_PHYS
 201
 202 #define CONFIG_ADDR_MAP
 203 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 204
 205 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 206 #define CONFIG_SYS_MEMTEST_END          0x00400000
 207 #define CONFIG_SYS_ALT_MEMTEST
 208 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 209
 210 /*
 211  *  Config the L3 Cache as L3 SRAM
 212  */
 213 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 214 /*
 215  * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
 216  * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
 217  * (CONFIG_SYS_INIT_L3_VADDR) will be different.
 218  */
 219 #define CONFIG_SYS_INIT_L3_VADDR        0xFFFC0000
 220 #define CONFIG_SYS_L3_SIZE              256 << 10
 221 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
 222 #ifdef CONFIG_RAMBOOT_PBL
 223 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 224 #endif
 225 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 226 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 227 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 228 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 229
 230 #define CONFIG_SYS_DCSRBAR              0xf0000000
 231 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 232
 233 /*
 234  * DDR Setup
 235  */
 236 #define CONFIG_VERY_BIG_RAM
 237 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 238 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 239
 240 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
 241 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 242 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 243
 244 #define CONFIG_DDR_SPD
 245 #ifndef CONFIG_SYS_FSL_DDR4
 246 #define CONFIG_SYS_FSL_DDR3
 247 #endif
 248
 249 #define CONFIG_SYS_SPD_BUS_NUM  0
 250 #define SPD_EEPROM_ADDRESS      0x51
 251
 252 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 253
 254 /*
 255  * IFC Definitions
 256  */
 257 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 258 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 259
 260 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
 261 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
 262                                 CSPR_PORT_SIZE_16 | \
 263                                 CSPR_MSEL_NOR | \
 264                                 CSPR_V)
 265 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 266
 267 /*
 268  * TDM Definition
 269  */
 270 #define T1040_TDM_QUIRK_CCSR_BASE       0xfe000000
 271
 272 /* NOR Flash Timing Params */
 273 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 274 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 275                                 FTIM0_NOR_TEADC(0x5) | \
 276                                 FTIM0_NOR_TEAHC(0x5))
 277 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 278                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 279                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 280 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 281                                 FTIM2_NOR_TCH(0x4) | \
 282                                 FTIM2_NOR_TWPH(0x0E) | \
 283                                 FTIM2_NOR_TWP(0x1c))
 284 #define CONFIG_SYS_NOR_FTIM3    0x0
 285
 286 #define CONFIG_SYS_FLASH_QUIET_TEST
 287 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 288
 289 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 290 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 291 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 292 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 293
 294 #define CONFIG_SYS_FLASH_EMPTY_INFO
 295 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 296
 297 /* CPLD on IFC */
 298 #define CPLD_LBMAP_MASK                 0x3F
 299 #define CPLD_BANK_SEL_MASK              0x07
 300 #define CPLD_BANK_OVERRIDE              0x40
 301 #define CPLD_LBMAP_ALTBANK              0x44 /* BANK OR | BANK 4 */
 302 #define CPLD_LBMAP_DFLTBANK             0x40 /* BANK OR | BANK0 */
 303 #define CPLD_LBMAP_RESET                0xFF
 304 #define CPLD_LBMAP_SHIFT                0x03
 305
 306 #if defined(CONFIG_T1042RDB_PI)
 307 #define CPLD_DIU_SEL_DFP                0x80
 308 #elif defined(CONFIG_T1042D4RDB)
 309 #define CPLD_DIU_SEL_DFP                0xc0
 310 #endif
 311
 312 #if defined(CONFIG_T1040D4RDB)
 313 #define CPLD_INT_MASK_ALL               0xFF
 314 #define CPLD_INT_MASK_THERM             0x80
 315 #define CPLD_INT_MASK_DVI_DFP           0x40
 316 #define CPLD_INT_MASK_QSGMII1           0x20
 317 #define CPLD_INT_MASK_QSGMII2           0x10
 318 #define CPLD_INT_MASK_SGMI1             0x08
 319 #define CPLD_INT_MASK_SGMI2             0x04
 320 #define CPLD_INT_MASK_TDMR1             0x02
 321 #define CPLD_INT_MASK_TDMR2             0x01
 322 #endif
 323
 324 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 325 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 326 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 327 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 328                                 | CSPR_PORT_SIZE_8 \
 329                                 | CSPR_MSEL_GPCM \
 330                                 | CSPR_V)
 331 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 332 #define CONFIG_SYS_CSOR2        0x0
 333 /* CPLD Timing parameters for IFC CS2 */
 334 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 335                                         FTIM0_GPCM_TEADC(0x0e) | \
 336                                         FTIM0_GPCM_TEAHC(0x0e))
 337 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 338                                         FTIM1_GPCM_TRAD(0x1f))
 339 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 340                                         FTIM2_GPCM_TCH(0x8) | \
 341                                         FTIM2_GPCM_TWP(0x1f))
 342 #define CONFIG_SYS_CS2_FTIM3            0x0
 343
 344 /* NAND Flash on IFC */
 345 #define CONFIG_NAND_FSL_IFC
 346 #define CONFIG_SYS_NAND_BASE            0xff800000
 347 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 348
 349 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 350 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 351                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 352                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 353                                 | CSPR_V)
 354 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 355
 356 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 357                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 358                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 359                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 360                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 361                                 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
 362                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 363
 364 #define CONFIG_SYS_NAND_ONFI_DETECTION
 365
 366 /* ONFI NAND Flash mode0 Timing Params */
 367 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 368                                         FTIM0_NAND_TWP(0x18)   | \
 369                                         FTIM0_NAND_TWCHT(0x07) | \
 370                                         FTIM0_NAND_TWH(0x0a))
 371 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 372                                         FTIM1_NAND_TWBE(0x39)  | \
 373                                         FTIM1_NAND_TRR(0x0e)   | \
 374                                         FTIM1_NAND_TRP(0x18))
 375 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 376                                         FTIM2_NAND_TREH(0x0a) | \
 377                                         FTIM2_NAND_TWHRE(0x1e))
 378 #define CONFIG_SYS_NAND_FTIM3           0x0
 379
 380 #define CONFIG_SYS_NAND_DDR_LAW         11
 381 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 382 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 383 #define CONFIG_CMD_NAND
 384
 385 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 386
 387 #if defined(CONFIG_NAND)
 388 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 389 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 390 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 391 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 392 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 393 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 394 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 395 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 396 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR_CSPR_EXT
 397 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 398 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 399 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 400 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 401 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 402 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 403 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 404 #else
 405 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 406 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 407 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 408 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 409 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 410 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 411 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 412 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 413 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 414 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 415 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 416 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 417 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 418 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 419 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 420 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 421 #endif
 422
 423 #ifdef CONFIG_SPL_BUILD
 424 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 425 #else
 426 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 427 #endif
 428
 429 #if defined(CONFIG_RAMBOOT_PBL)
 430 #define CONFIG_SYS_RAMBOOT
 431 #endif
 432
 433 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044
 434 #if defined(CONFIG_NAND)
 435 #define CONFIG_A008044_WORKAROUND
 436 #endif
 437 #endif
 438
 439 #define CONFIG_BOARD_EARLY_INIT_R
 440 #define CONFIG_MISC_INIT_R
 441
 442 #define CONFIG_HWCONFIG
 443
 444 /* define to use L1 as initial stack */
 445 #define CONFIG_L1_INIT_RAM
 446 #define CONFIG_SYS_INIT_RAM_LOCK
 447 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 448 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 449 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 450 /* The assembler doesn't like typecast */
 451 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 452         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 453           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 454 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 455
 456 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 457                                         GENERATED_GBL_DATA_SIZE)
 458 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 459
 460 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 461 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 462
 463 /* Serial Port - controlled on board with jumper J8
 464  * open - index 2
 465  * shorted - index 1
 466  */
 467 #define CONFIG_CONS_INDEX       1
 468 #define CONFIG_SYS_NS16550_SERIAL
 469 #define CONFIG_SYS_NS16550_REG_SIZE     1
 470 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 471
 472 #define CONFIG_SYS_BAUDRATE_TABLE       \
 473         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 474
 475 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 476 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 477 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 478 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 479 #ifndef CONFIG_SPL_BUILD
 480 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
 481 #endif
 482
 483 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T1042D4RDB)
 484 /* Video */
 485 #define CONFIG_FSL_DIU_FB
 486
 487 #ifdef CONFIG_FSL_DIU_FB
 488 #define CONFIG_FSL_DIU_CH7301
 489 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 490 #define CONFIG_VIDEO
 491 #define CONFIG_CMD_BMP
 492 #define CONFIG_CFB_CONSOLE
 493 #define CONFIG_CFB_CONSOLE_ANSI
 494 #define CONFIG_VIDEO_SW_CURSOR
 495 #define CONFIG_VGA_AS_SINGLE_DEVICE
 496 #define CONFIG_VIDEO_LOGO
 497 #define CONFIG_VIDEO_BMP_LOGO
 498 #endif
 499 #endif
 500
 501 /* I2C */
 502 #define CONFIG_SYS_I2C
 503 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 504 #define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C speed in Hz */
 505 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 506 #define CONFIG_SYS_FSL_I2C3_SPEED       400000
 507 #define CONFIG_SYS_FSL_I2C4_SPEED       400000
 508 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 509 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 510 #define CONFIG_SYS_FSL_I2C3_SLAVE       0x7F
 511 #define CONFIG_SYS_FSL_I2C4_SLAVE       0x7F
 512 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 513 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 514 #define CONFIG_SYS_FSL_I2C3_OFFSET      0x119000
 515 #define CONFIG_SYS_FSL_I2C4_OFFSET      0x119100
 516
 517 /* I2C bus multiplexer */
 518 #define I2C_MUX_PCA_ADDR                0x70
 519 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
 520 #define I2C_MUX_CH_DEFAULT      0x8
 521 #endif
 522
 523 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB)
 524 /* LDI/DVI Encoder for display */
 525 #define CONFIG_SYS_I2C_LDI_ADDR         0x38
 526 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 527
 528 /*
 529  * RTC configuration
 530  */
 531 #define RTC
 532 #define CONFIG_RTC_DS1337               1
 533 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 534
 535 /*DVI encoder*/
 536 #define CONFIG_HDMI_ENCODER_I2C_ADDR  0x75
 537 #endif
 538
 539 /*
 540  * eSPI - Enhanced SPI
 541  */
 542 #define CONFIG_SPI_FLASH_BAR
 543 #define CONFIG_SF_DEFAULT_SPEED         10000000
 544 #define CONFIG_SF_DEFAULT_MODE          0
 545 #define CONFIG_ENV_SPI_BUS              0
 546 #define CONFIG_ENV_SPI_CS               0
 547 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 548 #define CONFIG_ENV_SPI_MODE             0
 549
 550 /*
 551  * General PCI
 552  * Memory space is mapped 1-1, but I/O space must start from 0.
 553  */
 554
 555 #ifdef CONFIG_PCI
 556 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 557 #ifdef CONFIG_PCIE1
 558 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 559 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 560 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 561 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 562 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 563 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 564 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 565 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 566 #endif
 567
 568 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 569 #ifdef CONFIG_PCIE2
 570 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 571 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 572 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 573 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 574 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 575 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 576 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 577 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 578 #endif
 579
 580 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 581 #ifdef CONFIG_PCIE3
 582 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 583 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 584 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 585 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 586 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 587 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 588 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 589 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 590 #endif
 591
 592 /* controller 4, Base address 203000 */
 593 #ifdef CONFIG_PCIE4
 594 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
 595 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 596 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
 597 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 598 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
 599 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 600 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 601 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 602 #endif
 603
 604 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 605
 606 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 607 #define CONFIG_DOS_PARTITION
 608 #endif  /* CONFIG_PCI */
 609
 610 /* SATA */
 611 #define CONFIG_FSL_SATA_V2
 612 #ifdef CONFIG_FSL_SATA_V2
 613 #define CONFIG_LIBATA
 614 #define CONFIG_FSL_SATA
 615
 616 #define CONFIG_SYS_SATA_MAX_DEVICE      1
 617 #define CONFIG_SATA1
 618 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 619 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 620
 621 #define CONFIG_LBA48
 622 #define CONFIG_CMD_SATA
 623 #define CONFIG_DOS_PARTITION
 624 #endif
 625
 626 /*
 627 * USB
 628 */
 629 #define CONFIG_HAS_FSL_DR_USB
 630
 631 #ifdef CONFIG_HAS_FSL_DR_USB
 632 #define CONFIG_USB_EHCI
 633
 634 #ifdef CONFIG_USB_EHCI
 635 #define CONFIG_USB_EHCI_FSL
 636 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 637 #endif
 638 #endif
 639
 640 #define CONFIG_MMC
 641
 642 #ifdef CONFIG_MMC
 643 #define CONFIG_FSL_ESDHC
 644 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 645 #define CONFIG_GENERIC_MMC
 646 #define CONFIG_DOS_PARTITION
 647 #endif
 648
 649 /* Qman/Bman */
 650 #ifndef CONFIG_NOBQFMAN
 651 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 652 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 653 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 654 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 655 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 656 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 657 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 658 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 659 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 660 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 661                                         CONFIG_SYS_BMAN_CENA_SIZE)
 662 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 663 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 664 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 665 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 666 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 667 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 668 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 669 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 670 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 671 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 672 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 673                                         CONFIG_SYS_QMAN_CENA_SIZE)
 674 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 675 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 676
 677 #define CONFIG_SYS_DPAA_FMAN
 678 #define CONFIG_SYS_DPAA_PME
 679
 680 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
 681 #define CONFIG_QE
 682 #define CONFIG_U_QE
 683 #endif
 684
 685 /* Default address of microcode for the Linux Fman driver */
 686 #if defined(CONFIG_SPIFLASH)
 687 /*
 688  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 689  * env, so we got 0x110000.
 690  */
 691 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 692 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 693 #elif defined(CONFIG_SDCARD)
 694 /*
 695  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 696  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 697  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 698  */
 699 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 700 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 701 #elif defined(CONFIG_NAND)
 702 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 703 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
 704 #else
 705 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 706 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 707 #endif
 708
 709 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
 710 #if defined(CONFIG_SPIFLASH)
 711 #define CONFIG_SYS_QE_FW_ADDR           0x130000
 712 #elif defined(CONFIG_SDCARD)
 713 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 714 #elif defined(CONFIG_NAND)
 715 #define CONFIG_SYS_QE_FW_ADDR           (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 716 #else
 717 #define CONFIG_SYS_QE_FW_ADDR           0xEFF10000
 718 #endif
 719 #endif
 720
 721 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 722 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 723 #endif /* CONFIG_NOBQFMAN */
 724
 725 #ifdef CONFIG_SYS_DPAA_FMAN
 726 #define CONFIG_FMAN_ENET
 727 #define CONFIG_PHY_VITESSE
 728 #define CONFIG_PHY_REALTEK
 729 #endif
 730
 731 #ifdef CONFIG_FMAN_ENET
 732 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
 733 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x03
 734 #elif defined(CONFIG_T1040D4RDB)
 735 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x01
 736 #elif defined(CONFIG_T1042D4RDB)
 737 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x02
 738 #define CONFIG_SYS_SGMII2_PHY_ADDR             0x03
 739 #define CONFIG_SYS_SGMII3_PHY_ADDR             0x01
 740 #endif
 741
 742 #ifdef CONFIG_T104XD4RDB
 743 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x04
 744 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x05
 745 #else
 746 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x01
 747 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x02
 748 #endif
 749
 750 /* Enable VSC9953 L2 Switch driver on T1040 SoC */
 751 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB)
 752 #define CONFIG_VSC9953
 753 #define CONFIG_CMD_ETHSW
 754 #ifdef CONFIG_T1040RDB
 755 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x04
 756 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x08
 757 #else
 758 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x08
 759 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x0c
 760 #endif
 761 #endif
 762
 763 #define CONFIG_MII              /* MII PHY management */
 764 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 765 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 766 #endif
 767
 768 /*
 769  * Environment
 770  */
 771 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 772 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 773
 774 /*
 775  * Command line configuration.
 776  */
 777 #ifdef CONFIG_T1042RDB_PI
 778 #define CONFIG_CMD_DATE
 779 #endif
 780 #define CONFIG_CMD_ERRATA
 781 #define CONFIG_CMD_IRQ
 782 #define CONFIG_CMD_REGINFO
 783
 784 #ifdef CONFIG_PCI
 785 #define CONFIG_CMD_PCI
 786 #endif
 787
 788 /* Hash command with SHA acceleration supported in hardware */
 789 #ifdef CONFIG_FSL_CAAM
 790 #define CONFIG_CMD_HASH
 791 #define CONFIG_SHA_HW_ACCEL
 792 #endif
 793
 794 /*
 795  * Miscellaneous configurable options
 796  */
 797 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 798 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 799 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 800 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 801 #ifdef CONFIG_CMD_KGDB
 802 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 803 #else
 804 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 805 #endif
 806 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 807 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 808 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 809
 810 /*
 811  * For booting Linux, the board info and command line data
 812  * have to be in the first 64 MB of memory, since this is
 813  * the maximum mapped by the Linux kernel during initialization.
 814  */
 815 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 816 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 817
 818 #ifdef CONFIG_CMD_KGDB
 819 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 820 #endif
 821
 822 /*
 823  * Dynamic MTD Partition support with mtdparts
 824  */
 825 #ifndef CONFIG_SYS_NO_FLASH
 826 #define CONFIG_MTD_DEVICE
 827 #define CONFIG_MTD_PARTITIONS
 828 #define CONFIG_CMD_MTDPARTS
 829 #define CONFIG_FLASH_CFI_MTD
 830 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
 831                         "spi0=spife110000.0"
 832 #define MTDPARTS_DEFAULT        "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
 833                                 "128k(dtb),96m(fs),-(user);"\
 834                                 "fff800000.flash:2m(uboot),9m(kernel),"\
 835                                 "128k(dtb),96m(fs),-(user);spife110000.0:" \
 836                                 "2m(uboot),9m(kernel),128k(dtb),-(user)"
 837 #endif
 838
 839 /*
 840  * Environment Configuration
 841  */
 842 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 843 #define CONFIG_BOOTFILE         "uImage"
 844 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 845
 846 /* default location for tftp and bootm */
 847 #define CONFIG_LOADADDR         1000000
 848
 849
 850 #define CONFIG_BAUDRATE 115200
 851
 852 #define __USB_PHY_TYPE  utmi
 853 #define RAMDISKFILE     "t104xrdb/ramdisk.uboot"
 854
 855 #ifdef CONFIG_T1040RDB
 856 #define FDTFILE         "t1040rdb/t1040rdb.dtb"
 857 #elif defined(CONFIG_T1042RDB_PI)
 858 #define FDTFILE         "t1042rdb_pi/t1042rdb_pi.dtb"
 859 #elif defined(CONFIG_T1042RDB)
 860 #define FDTFILE         "t1042rdb/t1042rdb.dtb"
 861 #elif defined(CONFIG_T1040D4RDB)
 862 #define FDTFILE         "t1042rdb/t1040d4rdb.dtb"
 863 #elif defined(CONFIG_T1042D4RDB)
 864 #define FDTFILE         "t1042rdb/t1042d4rdb.dtb"
 865 #endif
 866
 867 #ifdef CONFIG_FSL_DIU_FB
 868 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
 869 #else
 870 #define DIU_ENVIRONMENT
 871 #endif
 872
 873 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 874         "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;"                  \
 875         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 876         "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 877         "netdev=eth0\0"                                         \
 878         "video-mode=" __stringify(DIU_ENVIRONMENT) "\0"         \
 879         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 880         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 881         "tftpflash=tftpboot $loadaddr $uboot && "               \
 882         "protect off $ubootaddr +$filesize && "                 \
 883         "erase $ubootaddr +$filesize && "                       \
 884         "cp.b $loadaddr $ubootaddr $filesize && "               \
 885         "protect on $ubootaddr +$filesize && "                  \
 886         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 887         "consoledev=ttyS0\0"                                    \
 888         "ramdiskaddr=2000000\0"                                 \
 889         "ramdiskfile=" __stringify(RAMDISKFILE) "\0"            \
 890         "fdtaddr=1e00000\0"                                     \
 891         "fdtfile=" __stringify(FDTFILE) "\0"                    \
 892         "bdev=sda3\0"
 893
 894 #define CONFIG_LINUX                       \
 895         "setenv bootargs root=/dev/ram rw "            \
 896         "console=$consoledev,$baudrate $othbootargs;"  \
 897         "setenv ramdiskaddr 0x02000000;"               \
 898         "setenv fdtaddr 0x00c00000;"                   \
 899         "setenv loadaddr 0x1000000;"                   \
 900         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 901
 902 #define CONFIG_HDBOOT                                   \
 903         "setenv bootargs root=/dev/$bdev rw "           \
 904         "console=$consoledev,$baudrate $othbootargs;"   \
 905         "tftp $loadaddr $bootfile;"                     \
 906         "tftp $fdtaddr $fdtfile;"                       \
 907         "bootm $loadaddr - $fdtaddr"
 908
 909 #define CONFIG_NFSBOOTCOMMAND                   \
 910         "setenv bootargs root=/dev/nfs rw "     \
 911         "nfsroot=$serverip:$rootpath "          \
 912         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 913         "console=$consoledev,$baudrate $othbootargs;"   \
 914         "tftp $loadaddr $bootfile;"             \
 915         "tftp $fdtaddr $fdtfile;"               \
 916         "bootm $loadaddr - $fdtaddr"
 917
 918 #define CONFIG_RAMBOOTCOMMAND                           \
 919         "setenv bootargs root=/dev/ram rw "             \
 920         "console=$consoledev,$baudrate $othbootargs;"   \
 921         "tftp $ramdiskaddr $ramdiskfile;"               \
 922         "tftp $loadaddr $bootfile;"                     \
 923         "tftp $fdtaddr $fdtfile;"                       \
 924         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 925
 926 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 927
 928 #include <asm/fsl_secure_boot.h>
 929
 930 #endif  /* __CONFIG_H */