1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
10 #include <linux/stringify.h>
13 * T104x RDB board configuration file
15 #include <asm/config_mpc85xx.h>
17 #ifdef CONFIG_RAMBOOT_PBL
18 #define RESET_VECTOR_OFFSET 0x27FFC
19 #define BOOT_PAGE_OFFSET 0x27000
21 #ifdef CONFIG_MTD_RAW_NAND
22 #ifdef CONFIG_NXP_ESBC
23 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
25 * HDR would be appended at end of image and copied to DDR along
28 #define CFG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \
29 CONFIG_U_BOOT_HDR_SIZE)
31 #define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10)
33 #define CFG_SYS_NAND_U_BOOT_DST 0x30000000
34 #define CFG_SYS_NAND_U_BOOT_START 0x30000000
37 #ifdef CONFIG_SPIFLASH
38 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
39 #define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
40 #define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
41 #define CFG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
42 #define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
46 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
47 #define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
48 #define CFG_SYS_MMC_U_BOOT_DST (0x30000000)
49 #define CFG_SYS_MMC_U_BOOT_START (0x30000000)
50 #define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10)
55 /* High Level Configuration Options */
57 #ifndef CONFIG_RESET_VECTOR_ADDRESS
58 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
61 #define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
64 * These can be toggled for performance analysis, otherwise use default.
66 #define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E
69 * Config the L3 Cache as L3 SRAM
71 #define CFG_SYS_INIT_L3_ADDR 0xFFFC0000
73 * For Secure Boot CFG_SYS_INIT_L3_ADDR will be redefined and hence
74 * Physical address (CFG_SYS_INIT_L3_ADDR) and virtual address
75 * (CFG_SYS_INIT_L3_VADDR) will be different.
77 #define CFG_SYS_INIT_L3_VADDR 0xFFFC0000
78 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
80 #define CFG_SYS_DCSRBAR 0xf0000000
81 #define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
86 #define CFG_SYS_DDR_SDRAM_BASE 0x00000000
87 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
89 #define SPD_EEPROM_ADDRESS 0x51
91 #define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
96 #define CFG_SYS_FLASH_BASE 0xe8000000
97 #define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
99 #define CFG_SYS_NOR_CSPR_EXT (0xf)
100 #define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE) | \
101 CSPR_PORT_SIZE_16 | \
104 #define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
109 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
111 /* NOR Flash Timing Params */
112 #define CFG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
113 #define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
114 FTIM0_NOR_TEADC(0x5) | \
115 FTIM0_NOR_TEAHC(0x5))
116 #define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
117 FTIM1_NOR_TRAD_NOR(0x1A) |\
118 FTIM1_NOR_TSEQRAD_NOR(0x13))
119 #define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
120 FTIM2_NOR_TCH(0x4) | \
121 FTIM2_NOR_TWPH(0x0E) | \
123 #define CFG_SYS_NOR_FTIM3 0x0
125 #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS}
128 #define CPLD_LBMAP_MASK 0x3F
129 #define CPLD_BANK_SEL_MASK 0x07
130 #define CPLD_BANK_OVERRIDE 0x40
131 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
132 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */
133 #define CPLD_LBMAP_RESET 0xFF
134 #define CPLD_LBMAP_SHIFT 0x03
136 #if defined(CONFIG_TARGET_T1042RDB_PI)
137 #define CPLD_DIU_SEL_DFP 0x80
138 #elif defined(CONFIG_TARGET_T1042D4RDB)
139 #define CPLD_DIU_SEL_DFP 0xc0
142 #if defined(CONFIG_TARGET_T1040D4RDB)
143 #define CPLD_INT_MASK_ALL 0xFF
144 #define CPLD_INT_MASK_THERM 0x80
145 #define CPLD_INT_MASK_DVI_DFP 0x40
146 #define CPLD_INT_MASK_QSGMII1 0x20
147 #define CPLD_INT_MASK_QSGMII2 0x10
148 #define CPLD_INT_MASK_SGMI1 0x08
149 #define CPLD_INT_MASK_SGMI2 0x04
150 #define CPLD_INT_MASK_TDMR1 0x02
151 #define CPLD_INT_MASK_TDMR2 0x01
154 #define CFG_SYS_CPLD_BASE 0xffdf0000
155 #define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE)
156 #define CFG_SYS_CSPR2_EXT (0xf)
157 #define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \
161 #define CFG_SYS_AMASK2 IFC_AMASK(64*1024)
162 #define CFG_SYS_CSOR2 0x0
163 /* CPLD Timing parameters for IFC CS2 */
164 #define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
165 FTIM0_GPCM_TEADC(0x0e) | \
166 FTIM0_GPCM_TEAHC(0x0e))
167 #define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
168 FTIM1_GPCM_TRAD(0x1f))
169 #define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
170 FTIM2_GPCM_TCH(0x8) | \
171 FTIM2_GPCM_TWP(0x1f))
172 #define CFG_SYS_CS2_FTIM3 0x0
174 /* NAND Flash on IFC */
175 #define CFG_SYS_NAND_BASE 0xff800000
176 #define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE)
178 #define CFG_SYS_NAND_CSPR_EXT (0xf)
179 #define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
180 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
181 | CSPR_MSEL_NAND /* MSEL = NAND */ \
183 #define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
185 #define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
186 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
187 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
188 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
189 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
190 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
191 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
193 /* ONFI NAND Flash mode0 Timing Params */
194 #define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
195 FTIM0_NAND_TWP(0x18) | \
196 FTIM0_NAND_TWCHT(0x07) | \
197 FTIM0_NAND_TWH(0x0a))
198 #define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
199 FTIM1_NAND_TWBE(0x39) | \
200 FTIM1_NAND_TRR(0x0e) | \
201 FTIM1_NAND_TRP(0x18))
202 #define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
203 FTIM2_NAND_TREH(0x0a) | \
204 FTIM2_NAND_TWHRE(0x1e))
205 #define CFG_SYS_NAND_FTIM3 0x0
207 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
209 #if defined(CONFIG_MTD_RAW_NAND)
210 #define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
211 #define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
212 #define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
213 #define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
214 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
215 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
216 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
217 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
218 #define CFG_SYS_CSPR1_EXT CFG_SYS_NOR_CSPR_EXT
219 #define CFG_SYS_CSPR1 CFG_SYS_NOR_CSPR
220 #define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
221 #define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
222 #define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
223 #define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
224 #define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
225 #define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
227 #define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT
228 #define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR
229 #define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
230 #define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
231 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
232 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
233 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
234 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
235 #define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
236 #define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
237 #define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
238 #define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
239 #define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
240 #define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
241 #define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
242 #define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
245 /* define to use L1 as initial stack */
246 #define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
247 #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
248 #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
249 /* The assembler doesn't like typecast */
250 #define CFG_SYS_INIT_RAM_ADDR_PHYS \
251 ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
252 CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
253 #define CFG_SYS_INIT_RAM_SIZE 0x00004000
255 #define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
257 /* Serial Port - controlled on board with jumper J8
261 #define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
263 #define CFG_SYS_BAUDRATE_TABLE \
264 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
266 #define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
267 #define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600)
268 #define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500)
269 #define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
271 /* I2C bus multiplexer */
272 #define I2C_MUX_PCA_ADDR 0x70
273 #define I2C_MUX_CH_DEFAULT 0x8
275 #if defined(CONFIG_TARGET_T1042RDB_PI) || \
276 defined(CONFIG_TARGET_T1040D4RDB) || \
277 defined(CONFIG_TARGET_T1042D4RDB)
281 #define CFG_SYS_I2C_RTC_ADDR 0x68
286 * eSPI - Enhanced SPI
291 * Memory space is mapped 1-1, but I/O space must start from 0.
295 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
297 #define CFG_SYS_PCIE1_MEM_VIRT 0x80000000
298 #define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
299 #define CFG_SYS_PCIE1_IO_VIRT 0xf8000000
300 #define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull
303 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
305 #define CFG_SYS_PCIE2_MEM_VIRT 0x90000000
306 #define CFG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
307 #define CFG_SYS_PCIE2_IO_VIRT 0xf8010000
308 #define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull
311 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
313 #define CFG_SYS_PCIE3_MEM_VIRT 0xa0000000
314 #define CFG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
317 /* controller 4, Base address 203000 */
319 #define CFG_SYS_PCIE4_MEM_VIRT 0xb0000000
320 #define CFG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
322 #endif /* CONFIG_PCI */
329 #define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
333 #ifndef CONFIG_NOBQFMAN
334 #define CFG_SYS_BMAN_NUM_PORTALS 10
335 #define CFG_SYS_BMAN_MEM_BASE 0xf4000000
336 #define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull
337 #define CFG_SYS_BMAN_MEM_SIZE 0x02000000
338 #define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000
339 #define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000
340 #define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE
341 #define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
342 #define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \
343 CFG_SYS_BMAN_CENA_SIZE)
344 #define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
345 #define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08
346 #define CFG_SYS_QMAN_NUM_PORTALS 10
347 #define CFG_SYS_QMAN_MEM_BASE 0xf6000000
348 #define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull
349 #define CFG_SYS_QMAN_MEM_SIZE 0x02000000
350 #define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000
351 #define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
352 #define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \
353 CFG_SYS_QMAN_CENA_SIZE)
354 #define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
355 #define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08
356 #endif /* CONFIG_NOBQFMAN */
358 #ifdef CONFIG_FMAN_ENET
359 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
360 #define CFG_SYS_SGMII1_PHY_ADDR 0x03
361 #elif defined(CONFIG_TARGET_T1040D4RDB)
362 #define CFG_SYS_SGMII1_PHY_ADDR 0x01
363 #elif defined(CONFIG_TARGET_T1042D4RDB)
364 #define CFG_SYS_SGMII1_PHY_ADDR 0x02
365 #define CFG_SYS_SGMII2_PHY_ADDR 0x03
366 #define CFG_SYS_SGMII3_PHY_ADDR 0x01
369 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
370 #define CFG_SYS_RGMII1_PHY_ADDR 0x04
371 #define CFG_SYS_RGMII2_PHY_ADDR 0x05
373 #define CFG_SYS_RGMII1_PHY_ADDR 0x01
374 #define CFG_SYS_RGMII2_PHY_ADDR 0x02
377 /* Enable VSC9953 L2 Switch driver on T1040 SoC */
378 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
379 #ifdef CONFIG_TARGET_T1040RDB
380 #define CFG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
381 #define CFG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
383 #define CFG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
384 #define CFG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
390 * Miscellaneous configurable options
394 * For booting Linux, the board info and command line data
395 * have to be in the first 64 MB of memory, since this is
396 * the maximum mapped by the Linux kernel during initialization.
398 #define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
401 * Dynamic MTD Partition support with mtdparts
405 * Environment Configuration
408 #define __USB_PHY_TYPE utmi
409 #define RAMDISKFILE "t104xrdb/ramdisk.uboot"
411 #ifdef CONFIG_TARGET_T1040RDB
412 #define FDTFILE "t1040rdb/t1040rdb.dtb"
413 #elif defined(CONFIG_TARGET_T1042RDB_PI)
414 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
415 #elif defined(CONFIG_TARGET_T1042RDB)
416 #define FDTFILE "t1042rdb/t1042rdb.dtb"
417 #elif defined(CONFIG_TARGET_T1040D4RDB)
418 #define FDTFILE "t1042rdb/t1040d4rdb.dtb"
419 #elif defined(CONFIG_TARGET_T1042D4RDB)
420 #define FDTFILE "t1042rdb/t1042d4rdb.dtb"
423 #define CONFIG_EXTRA_ENV_SETTINGS \
424 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
425 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
426 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
428 "uboot=" CONFIG_UBOOTPATH "\0" \
429 "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
430 "tftpflash=tftpboot $loadaddr $uboot && " \
431 "protect off $ubootaddr +$filesize && " \
432 "erase $ubootaddr +$filesize && " \
433 "cp.b $loadaddr $ubootaddr $filesize && " \
434 "protect on $ubootaddr +$filesize && " \
435 "cmp.b $loadaddr $ubootaddr $filesize\0" \
436 "consoledev=ttyS0\0" \
437 "ramdiskaddr=2000000\0" \
438 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
439 "fdtaddr=1e00000\0" \
440 "fdtfile=" __stringify(FDTFILE) "\0" \
443 #include <asm/fsl_secure_boot.h>
445 #endif /* __CONFIG_H */