2 + * Copyright 2014 Freescale Semiconductor, Inc.
4 + * SPDX-License-Identifier: GPL-2.0+
11 * T104x RDB board configuration file
13 #define CONFIG_T104xRDB
14 #define CONFIG_PHYS_64BIT
16 #ifdef CONFIG_RAMBOOT_PBL
17 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
18 #ifdef CONFIG_T1040RDB
19 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg
21 #ifdef CONFIG_T1042RDB_PI
22 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg
25 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
26 #define CONFIG_SPL_ENV_SUPPORT
27 #define CONFIG_SPL_SERIAL_SUPPORT
28 #define CONFIG_SPL_FLUSH_IMAGE
29 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
30 #define CONFIG_SPL_LIBGENERIC_SUPPORT
31 #define CONFIG_SPL_LIBCOMMON_SUPPORT
32 #define CONFIG_SPL_I2C_SUPPORT
33 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
34 #define CONFIG_FSL_LAW /* Use common FSL init code */
35 #define CONFIG_SYS_TEXT_BASE 0x30001000
36 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
37 #define CONFIG_SPL_PAD_TO 0x40000
38 #define CONFIG_SPL_MAX_SIZE 0x28000
39 #ifdef CONFIG_SPL_BUILD
40 #define CONFIG_SPL_SKIP_RELOCATE
41 #define CONFIG_SPL_COMMON_INIT_DDR
42 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
43 #define CONFIG_SYS_NO_FLASH
45 #define RESET_VECTOR_OFFSET 0x27FFC
46 #define BOOT_PAGE_OFFSET 0x27000
49 #define CONFIG_SPL_NAND_SUPPORT
50 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
51 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
52 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
53 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
54 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
55 #define CONFIG_SPL_NAND_BOOT
58 #ifdef CONFIG_SPIFLASH
59 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
60 #define CONFIG_SPL_SPI_SUPPORT
61 #define CONFIG_SPL_SPI_FLASH_SUPPORT
62 #define CONFIG_SPL_SPI_FLASH_MINIMAL
63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
67 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
68 #ifndef CONFIG_SPL_BUILD
69 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
71 #define CONFIG_SPL_SPI_BOOT
75 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
76 #define CONFIG_SPL_MMC_SUPPORT
77 #define CONFIG_SPL_MMC_MINIMAL
78 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
79 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
80 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
81 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
82 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
83 #ifndef CONFIG_SPL_BUILD
84 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
86 #define CONFIG_SPL_MMC_BOOT
91 /* High Level Configuration Options */
93 #define CONFIG_E500 /* BOOKE e500 family */
94 #define CONFIG_E500MC /* BOOKE e500mc family */
95 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
96 #define CONFIG_MP /* support multiple processors */
98 /* support deep sleep */
99 #define CONFIG_DEEP_SLEEP
100 #define CONFIG_SILENT_CONSOLE
102 #ifndef CONFIG_SYS_TEXT_BASE
103 #define CONFIG_SYS_TEXT_BASE 0xeff40000
106 #ifndef CONFIG_RESET_VECTOR_ADDRESS
107 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
110 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
111 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
112 #define CONFIG_FSL_IFC /* Enable IFC Support */
113 #define CONFIG_PCI /* Enable PCI/PCIE */
114 #define CONFIG_PCI_INDIRECT_BRIDGE
115 #define CONFIG_PCIE1 /* PCIE controler 1 */
116 #define CONFIG_PCIE2 /* PCIE controler 2 */
117 #define CONFIG_PCIE3 /* PCIE controler 3 */
118 #define CONFIG_PCIE4 /* PCIE controler 4 */
120 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
121 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
123 #define CONFIG_FSL_LAW /* Use common FSL init code */
125 #define CONFIG_ENV_OVERWRITE
127 #ifndef CONFIG_SYS_NO_FLASH
128 #define CONFIG_FLASH_CFI_DRIVER
129 #define CONFIG_SYS_FLASH_CFI
130 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
133 #if defined(CONFIG_SPIFLASH)
134 #define CONFIG_SYS_EXTRA_ENV_RELOC
135 #define CONFIG_ENV_IS_IN_SPI_FLASH
136 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
137 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
138 #define CONFIG_ENV_SECT_SIZE 0x10000
139 #elif defined(CONFIG_SDCARD)
140 #define CONFIG_SYS_EXTRA_ENV_RELOC
141 #define CONFIG_ENV_IS_IN_MMC
142 #define CONFIG_SYS_MMC_ENV_DEV 0
143 #define CONFIG_ENV_SIZE 0x2000
144 #define CONFIG_ENV_OFFSET (512 * 0x800)
145 #elif defined(CONFIG_NAND)
146 #define CONFIG_SYS_EXTRA_ENV_RELOC
147 #define CONFIG_ENV_IS_IN_NAND
148 #define CONFIG_ENV_SIZE 0x2000
149 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
151 #define CONFIG_ENV_IS_IN_FLASH
152 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
153 #define CONFIG_ENV_SIZE 0x2000
154 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
157 #define CONFIG_SYS_CLK_FREQ 100000000
158 #define CONFIG_DDR_CLK_FREQ 66666666
161 * These can be toggled for performance analysis, otherwise use default.
163 #define CONFIG_SYS_CACHE_STASHING
164 #define CONFIG_BACKSIDE_L2_CACHE
165 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
166 #define CONFIG_BTB /* toggle branch predition */
167 #define CONFIG_DDR_ECC
168 #ifdef CONFIG_DDR_ECC
169 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
170 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
173 #define CONFIG_ENABLE_36BIT_PHYS
175 #define CONFIG_ADDR_MAP
176 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
178 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
179 #define CONFIG_SYS_MEMTEST_END 0x00400000
180 #define CONFIG_SYS_ALT_MEMTEST
181 #define CONFIG_PANIC_HANG /* do not reset board on panic */
184 * Config the L3 Cache as L3 SRAM
186 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
187 #define CONFIG_SYS_L3_SIZE 256 << 10
188 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
189 #ifdef CONFIG_RAMBOOT_PBL
190 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
192 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
193 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
194 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
195 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
197 #define CONFIG_SYS_DCSRBAR 0xf0000000
198 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
203 #define CONFIG_VERY_BIG_RAM
204 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
205 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
207 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
208 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
209 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
211 #define CONFIG_DDR_SPD
212 #define CONFIG_SYS_DDR_RAW_TIMING
213 #define CONFIG_SYS_FSL_DDR3
215 #define CONFIG_SYS_SPD_BUS_NUM 0
216 #define SPD_EEPROM_ADDRESS 0x51
218 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
223 #define CONFIG_SYS_FLASH_BASE 0xe8000000
224 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
226 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
227 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
228 CSPR_PORT_SIZE_16 | \
231 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
236 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
238 /* NOR Flash Timing Params */
239 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
240 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
241 FTIM0_NOR_TEADC(0x5) | \
242 FTIM0_NOR_TEAHC(0x5))
243 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
244 FTIM1_NOR_TRAD_NOR(0x1A) |\
245 FTIM1_NOR_TSEQRAD_NOR(0x13))
246 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
247 FTIM2_NOR_TCH(0x4) | \
248 FTIM2_NOR_TWPH(0x0E) | \
250 #define CONFIG_SYS_NOR_FTIM3 0x0
252 #define CONFIG_SYS_FLASH_QUIET_TEST
253 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
255 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
256 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
257 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
258 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
260 #define CONFIG_SYS_FLASH_EMPTY_INFO
261 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
264 #define CPLD_LBMAP_MASK 0x3F
265 #define CPLD_BANK_SEL_MASK 0x07
266 #define CPLD_BANK_OVERRIDE 0x40
267 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
268 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */
269 #define CPLD_LBMAP_RESET 0xFF
270 #define CPLD_LBMAP_SHIFT 0x03
271 #ifdef CONFIG_T1042RDB_PI
272 #define CPLD_DIU_SEL_DFP 0x80
275 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
276 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
277 #define CONFIG_SYS_CSPR2_EXT (0xf)
278 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
282 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
283 #define CONFIG_SYS_CSOR2 0x0
284 /* CPLD Timing parameters for IFC CS2 */
285 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
286 FTIM0_GPCM_TEADC(0x0e) | \
287 FTIM0_GPCM_TEAHC(0x0e))
288 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
289 FTIM1_GPCM_TRAD(0x1f))
290 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
291 FTIM2_GPCM_TCH(0x8) | \
292 FTIM2_GPCM_TWP(0x1f))
293 #define CONFIG_SYS_CS2_FTIM3 0x0
295 /* NAND Flash on IFC */
296 #define CONFIG_NAND_FSL_IFC
297 #define CONFIG_SYS_NAND_BASE 0xff800000
298 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
300 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
301 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
302 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
303 | CSPR_MSEL_NAND /* MSEL = NAND */ \
305 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
307 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
308 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
309 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
310 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
311 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
312 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
313 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
315 #define CONFIG_SYS_NAND_ONFI_DETECTION
317 /* ONFI NAND Flash mode0 Timing Params */
318 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
319 FTIM0_NAND_TWP(0x18) | \
320 FTIM0_NAND_TWCHT(0x07) | \
321 FTIM0_NAND_TWH(0x0a))
322 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
323 FTIM1_NAND_TWBE(0x39) | \
324 FTIM1_NAND_TRR(0x0e) | \
325 FTIM1_NAND_TRP(0x18))
326 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
327 FTIM2_NAND_TREH(0x0a) | \
328 FTIM2_NAND_TWHRE(0x1e))
329 #define CONFIG_SYS_NAND_FTIM3 0x0
331 #define CONFIG_SYS_NAND_DDR_LAW 11
332 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
333 #define CONFIG_SYS_MAX_NAND_DEVICE 1
334 #define CONFIG_MTD_NAND_VERIFY_WRITE
335 #define CONFIG_CMD_NAND
337 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
339 #if defined(CONFIG_NAND)
340 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
341 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
342 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
343 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
344 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
345 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
346 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
347 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
348 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
349 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
350 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
351 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
352 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
353 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
354 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
355 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
357 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
358 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
359 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
360 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
361 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
362 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
363 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
364 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
365 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
366 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
367 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
368 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
369 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
370 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
371 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
372 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
375 #ifdef CONFIG_SPL_BUILD
376 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
378 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
381 #if defined(CONFIG_RAMBOOT_PBL)
382 #define CONFIG_SYS_RAMBOOT
385 #define CONFIG_BOARD_EARLY_INIT_R
386 #define CONFIG_MISC_INIT_R
388 #define CONFIG_HWCONFIG
390 /* define to use L1 as initial stack */
391 #define CONFIG_L1_INIT_RAM
392 #define CONFIG_SYS_INIT_RAM_LOCK
393 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
394 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
395 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
396 /* The assembler doesn't like typecast */
397 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
398 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
399 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
400 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
402 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
403 GENERATED_GBL_DATA_SIZE)
404 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
406 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
407 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
409 /* Serial Port - controlled on board with jumper J8
413 #define CONFIG_CONS_INDEX 1
414 #define CONFIG_SYS_NS16550
415 #define CONFIG_SYS_NS16550_SERIAL
416 #define CONFIG_SYS_NS16550_REG_SIZE 1
417 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
419 #define CONFIG_SYS_BAUDRATE_TABLE \
420 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
422 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
423 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
424 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
425 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
426 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */
427 #ifndef CONFIG_SPL_BUILD
428 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
431 /* Use the HUSH parser */
432 #define CONFIG_SYS_HUSH_PARSER
433 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
435 #ifdef CONFIG_T1042RDB_PI
437 #define CONFIG_FSL_DIU_FB
439 #ifdef CONFIG_FSL_DIU_FB
440 #define CONFIG_FSL_DIU_CH7301
441 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
443 #define CONFIG_CMD_BMP
444 #define CONFIG_CFB_CONSOLE
445 #define CONFIG_CFB_CONSOLE_ANSI
446 #define CONFIG_VIDEO_SW_CURSOR
447 #define CONFIG_VGA_AS_SINGLE_DEVICE
448 #define CONFIG_VIDEO_LOGO
449 #define CONFIG_VIDEO_BMP_LOGO
453 /* pass open firmware flat tree */
454 #define CONFIG_OF_LIBFDT
455 #define CONFIG_OF_BOARD_SETUP
456 #define CONFIG_OF_STDOUT_VIA_ALIAS
458 /* new uImage format support */
460 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
463 #define CONFIG_SYS_I2C
464 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
465 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
466 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
467 #define CONFIG_SYS_FSL_I2C3_SPEED 400000
468 #define CONFIG_SYS_FSL_I2C4_SPEED 400000
469 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
470 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
471 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
472 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
473 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
474 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
475 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
476 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
478 /* I2C bus multiplexer */
479 #define I2C_MUX_PCA_ADDR 0x70
480 #ifdef CONFIG_T1040RDB
481 #define I2C_MUX_CH_DEFAULT 0x8
484 #ifdef CONFIG_T1042RDB_PI
485 /* LDI/DVI Encoder for display */
486 #define CONFIG_SYS_I2C_LDI_ADDR 0x38
487 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
493 #define CONFIG_RTC_DS1337 1
494 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
497 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
501 * eSPI - Enhanced SPI
503 #define CONFIG_FSL_ESPI
504 #define CONFIG_SPI_FLASH
505 #define CONFIG_SPI_FLASH_STMICRO
506 #define CONFIG_CMD_SF
507 #define CONFIG_SF_DEFAULT_SPEED 10000000
508 #define CONFIG_SF_DEFAULT_MODE 0
509 #define CONFIG_ENV_SPI_BUS 0
510 #define CONFIG_ENV_SPI_CS 0
511 #define CONFIG_ENV_SPI_MAX_HZ 10000000
512 #define CONFIG_ENV_SPI_MODE 0
516 * Memory space is mapped 1-1, but I/O space must start from 0.
520 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
522 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
523 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
524 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
525 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
526 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
527 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
528 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
529 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
532 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
534 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
535 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
536 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
537 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
538 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
539 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
540 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
541 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
544 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
546 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
547 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
548 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
549 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
550 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
551 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
552 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
553 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
556 /* controller 4, Base address 203000 */
558 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
559 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
560 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
561 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
562 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
563 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
564 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
565 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
568 #define CONFIG_PCI_PNP /* do pci plug-and-play */
571 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
572 #define CONFIG_DOS_PARTITION
573 #endif /* CONFIG_PCI */
576 #define CONFIG_FSL_SATA_V2
577 #ifdef CONFIG_FSL_SATA_V2
578 #define CONFIG_LIBATA
579 #define CONFIG_FSL_SATA
581 #define CONFIG_SYS_SATA_MAX_DEVICE 1
583 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
584 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
587 #define CONFIG_CMD_SATA
588 #define CONFIG_DOS_PARTITION
589 #define CONFIG_CMD_EXT2
595 #define CONFIG_HAS_FSL_DR_USB
597 #ifdef CONFIG_HAS_FSL_DR_USB
598 #define CONFIG_USB_EHCI
600 #ifdef CONFIG_USB_EHCI
601 #define CONFIG_CMD_USB
602 #define CONFIG_USB_STORAGE
603 #define CONFIG_USB_EHCI_FSL
604 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
605 #define CONFIG_CMD_EXT2
612 #define CONFIG_FSL_ESDHC
613 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
614 #define CONFIG_CMD_MMC
615 #define CONFIG_GENERIC_MMC
616 #define CONFIG_CMD_EXT2
617 #define CONFIG_CMD_FAT
618 #define CONFIG_DOS_PARTITION
622 #ifndef CONFIG_NOBQFMAN
623 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
624 #define CONFIG_SYS_BMAN_NUM_PORTALS 25
625 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
626 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
627 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
628 #define CONFIG_SYS_QMAN_NUM_PORTALS 25
629 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
630 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
631 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
633 #define CONFIG_SYS_DPAA_FMAN
634 #define CONFIG_SYS_DPAA_PME
636 #ifdef CONFIG_T1040RDB
641 /* Default address of microcode for the Linux Fman driver */
642 #if defined(CONFIG_SPIFLASH)
644 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
645 * env, so we got 0x110000.
647 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
648 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
649 #elif defined(CONFIG_SDCARD)
651 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
652 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
653 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
655 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
656 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
657 #elif defined(CONFIG_NAND)
658 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
659 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
661 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
662 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
665 #ifdef CONFIG_T1040RDB
666 #if defined(CONFIG_SPIFLASH)
667 #define CONFIG_SYS_QE_FW_ADDR 0x130000
668 #elif defined(CONFIG_SDCARD)
669 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
670 #elif defined(CONFIG_NAND)
671 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
673 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
678 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
679 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
680 #endif /* CONFIG_NOBQFMAN */
682 #ifdef CONFIG_SYS_DPAA_FMAN
683 #define CONFIG_FMAN_ENET
684 #define CONFIG_PHY_VITESSE
685 #define CONFIG_PHY_REALTEK
688 #ifdef CONFIG_FMAN_ENET
689 #ifdef CONFIG_T1040RDB
690 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
692 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
693 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
695 #define CONFIG_MII /* MII PHY management */
696 #define CONFIG_ETHPRIME "FM1@DTSEC4"
697 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
703 #define CONFIG_LOADS_ECHO /* echo on for serial download */
704 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
707 * Command line configuration.
709 #include <config_cmd_default.h>
711 #ifdef CONFIG_T1042RDB_PI
712 #define CONFIG_CMD_DATE
714 #define CONFIG_CMD_DHCP
715 #define CONFIG_CMD_ELF
716 #define CONFIG_CMD_ERRATA
717 #define CONFIG_CMD_GREPENV
718 #define CONFIG_CMD_IRQ
719 #define CONFIG_CMD_I2C
720 #define CONFIG_CMD_MII
721 #define CONFIG_CMD_PING
722 #define CONFIG_CMD_REGINFO
723 #define CONFIG_CMD_SETEXPR
726 #define CONFIG_CMD_PCI
727 #define CONFIG_CMD_NET
731 * Miscellaneous configurable options
733 #define CONFIG_SYS_LONGHELP /* undef to save memory */
734 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
735 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
736 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
737 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
738 #ifdef CONFIG_CMD_KGDB
739 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
741 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
743 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
744 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
745 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
748 * For booting Linux, the board info and command line data
749 * have to be in the first 64 MB of memory, since this is
750 * the maximum mapped by the Linux kernel during initialization.
752 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
753 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
755 #ifdef CONFIG_CMD_KGDB
756 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
760 * Dynamic MTD Partition support with mtdparts
762 #ifndef CONFIG_SYS_NO_FLASH
763 #define CONFIG_MTD_DEVICE
764 #define CONFIG_MTD_PARTITIONS
765 #define CONFIG_CMD_MTDPARTS
766 #define CONFIG_FLASH_CFI_MTD
767 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
769 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
770 "128k(dtb),96m(fs),-(user);"\
771 "fff800000.flash:2m(uboot),9m(kernel),"\
772 "128k(dtb),96m(fs),-(user);spife110000.0:" \
773 "2m(uboot),9m(kernel),128k(dtb),-(user)"
777 * Environment Configuration
779 #define CONFIG_ROOTPATH "/opt/nfsroot"
780 #define CONFIG_BOOTFILE "uImage"
781 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
783 /* default location for tftp and bootm */
784 #define CONFIG_LOADADDR 1000000
786 #define CONFIG_BOOTDELAY 10 /*-1 disables auto-boot*/
788 #define CONFIG_BAUDRATE 115200
790 #define __USB_PHY_TYPE utmi
792 #ifdef CONFIG_T1040RDB
793 #define FDTFILE "t1040rdb/t1040rdb.dtb"
794 #define RAMDISKFILE "t1040rdb/ramdisk.uboot"
795 #elif CONFIG_T1042RDB_PI
796 #define FDTFILE "t1040rdb_pi/t1040rdb_pi.dtb"
797 #define RAMDISKFILE "t1040rdb_pi/ramdisk.uboot"
800 #ifdef CONFIG_FSL_DIU_FB
801 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
803 #define DIU_ENVIRONMENT
806 #define CONFIG_EXTRA_ENV_SETTINGS \
807 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
808 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
809 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
811 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \
812 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
813 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
814 "tftpflash=tftpboot $loadaddr $uboot && " \
815 "protect off $ubootaddr +$filesize && " \
816 "erase $ubootaddr +$filesize && " \
817 "cp.b $loadaddr $ubootaddr $filesize && " \
818 "protect on $ubootaddr +$filesize && " \
819 "cmp.b $loadaddr $ubootaddr $filesize\0" \
820 "consoledev=ttyS0\0" \
821 "ramdiskaddr=2000000\0" \
822 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
824 "fdtfile=" __stringify(FDTFILE) "\0" \
827 #define CONFIG_LINUX \
828 "setenv bootargs root=/dev/ram rw " \
829 "console=$consoledev,$baudrate $othbootargs;" \
830 "setenv ramdiskaddr 0x02000000;" \
831 "setenv fdtaddr 0x00c00000;" \
832 "setenv loadaddr 0x1000000;" \
833 "bootm $loadaddr $ramdiskaddr $fdtaddr"
835 #define CONFIG_HDBOOT \
836 "setenv bootargs root=/dev/$bdev rw " \
837 "console=$consoledev,$baudrate $othbootargs;" \
838 "tftp $loadaddr $bootfile;" \
839 "tftp $fdtaddr $fdtfile;" \
840 "bootm $loadaddr - $fdtaddr"
842 #define CONFIG_NFSBOOTCOMMAND \
843 "setenv bootargs root=/dev/nfs rw " \
844 "nfsroot=$serverip:$rootpath " \
845 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
846 "console=$consoledev,$baudrate $othbootargs;" \
847 "tftp $loadaddr $bootfile;" \
848 "tftp $fdtaddr $fdtfile;" \
849 "bootm $loadaddr - $fdtaddr"
851 #define CONFIG_RAMBOOTCOMMAND \
852 "setenv bootargs root=/dev/ram rw " \
853 "console=$consoledev,$baudrate $othbootargs;" \
854 "tftp $ramdiskaddr $ramdiskfile;" \
855 "tftp $loadaddr $bootfile;" \
856 "tftp $fdtaddr $fdtfile;" \
857 "bootm $loadaddr $ramdiskaddr $fdtaddr"
859 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
861 #ifdef CONFIG_SECURE_BOOT
862 #include <asm/fsl_secure_boot.h>
865 #endif /* __CONFIG_H */