include/configs/T104xRDB.h

   1 /*
   2 + * Copyright 2014 Freescale Semiconductor, Inc.
   3 + *
   4 + * SPDX-License-Identifier:     GPL-2.0+
   5 + */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 /*
  11  * T104x RDB board configuration file
  12  */
  13 #define CONFIG_E500                     /* BOOKE e500 family */
  14 #include <asm/config_mpc85xx.h>
  15
  16 #ifdef CONFIG_RAMBOOT_PBL
  17
  18 #ifndef CONFIG_SECURE_BOOT
  19 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
  20 #else
  21 #define CONFIG_SYS_FSL_PBL_PBI \
  22                 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg
  23 #endif
  24
  25 #define CONFIG_SPL_FLUSH_IMAGE
  26 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  27 #define CONFIG_FSL_LAW                 /* Use common FSL init code */
  28 #define CONFIG_SYS_TEXT_BASE            0x30001000
  29 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  30 #define CONFIG_SPL_PAD_TO               0x40000
  31 #define CONFIG_SPL_MAX_SIZE             0x28000
  32 #ifdef CONFIG_SPL_BUILD
  33 #define CONFIG_SPL_SKIP_RELOCATE
  34 #define CONFIG_SPL_COMMON_INIT_DDR
  35 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  36 #define CONFIG_SYS_NO_FLASH
  37 #endif
  38 #define RESET_VECTOR_OFFSET             0x27FFC
  39 #define BOOT_PAGE_OFFSET                0x27000
  40
  41 #ifdef CONFIG_NAND
  42 #ifdef CONFIG_SECURE_BOOT
  43 #define CONFIG_U_BOOT_HDR_SIZE          (16 << 10)
  44 /*
  45  * HDR would be appended at end of image and copied to DDR along
  46  * with U-Boot image.
  47  */
  48 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) + \
  49                                          CONFIG_U_BOOT_HDR_SIZE)
  50 #else
  51 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  52 #endif
  53 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  54 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  55 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  56 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  57 #ifdef CONFIG_TARGET_T1040RDB
  58 #define CONFIG_SYS_FSL_PBL_RCW \
  59 $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg
  60 #endif
  61 #ifdef CONFIG_TARGET_T1042RDB_PI
  62 #define CONFIG_SYS_FSL_PBL_RCW \
  63 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
  64 #endif
  65 #ifdef CONFIG_TARGET_T1042RDB
  66 #define CONFIG_SYS_FSL_PBL_RCW \
  67 $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg
  68 #endif
  69 #ifdef CONFIG_TARGET_T1040D4RDB
  70 #define CONFIG_SYS_FSL_PBL_RCW \
  71 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
  72 #endif
  73 #ifdef CONFIG_TARGET_T1042D4RDB
  74 #define CONFIG_SYS_FSL_PBL_RCW \
  75 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
  76 #endif
  77 #define CONFIG_SPL_NAND_BOOT
  78 #endif
  79
  80 #ifdef CONFIG_SPIFLASH
  81 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  82 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  83 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  84 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  85 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  86 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  87 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  88 #ifndef CONFIG_SPL_BUILD
  89 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  90 #endif
  91 #ifdef CONFIG_TARGET_T1040RDB
  92 #define CONFIG_SYS_FSL_PBL_RCW \
  93 $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg
  94 #endif
  95 #ifdef CONFIG_TARGET_T1042RDB_PI
  96 #define CONFIG_SYS_FSL_PBL_RCW \
  97 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
  98 #endif
  99 #ifdef CONFIG_TARGET_T1042RDB
 100 #define CONFIG_SYS_FSL_PBL_RCW \
 101 $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg
 102 #endif
 103 #ifdef CONFIG_TARGET_T1040D4RDB
 104 #define CONFIG_SYS_FSL_PBL_RCW \
 105 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
 106 #endif
 107 #ifdef CONFIG_TARGET_T1042D4RDB
 108 #define CONFIG_SYS_FSL_PBL_RCW \
 109 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
 110 #endif
 111 #define CONFIG_SPL_SPI_BOOT
 112 #endif
 113
 114 #ifdef CONFIG_SDCARD
 115 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
 116 #define CONFIG_SPL_MMC_MINIMAL
 117 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
 118 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
 119 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
 120 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
 121 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
 122 #ifndef CONFIG_SPL_BUILD
 123 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 124 #endif
 125 #ifdef CONFIG_TARGET_T1040RDB
 126 #define CONFIG_SYS_FSL_PBL_RCW \
 127 $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg
 128 #endif
 129 #ifdef CONFIG_TARGET_T1042RDB_PI
 130 #define CONFIG_SYS_FSL_PBL_RCW \
 131 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
 132 #endif
 133 #ifdef CONFIG_TARGET_T1042RDB
 134 #define CONFIG_SYS_FSL_PBL_RCW \
 135 $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg
 136 #endif
 137 #ifdef CONFIG_TARGET_T1040D4RDB
 138 #define CONFIG_SYS_FSL_PBL_RCW \
 139 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
 140 #endif
 141 #ifdef CONFIG_TARGET_T1042D4RDB
 142 #define CONFIG_SYS_FSL_PBL_RCW \
 143 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
 144 #endif
 145 #define CONFIG_SPL_MMC_BOOT
 146 #endif
 147
 148 #endif
 149
 150 /* High Level Configuration Options */
 151 #define CONFIG_BOOKE
 152 #define CONFIG_E500MC                   /* BOOKE e500mc family */
 153 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
 154 #define CONFIG_MP                       /* support multiple processors */
 155
 156 /* support deep sleep */
 157 #define CONFIG_DEEP_SLEEP
 158 #if defined(CONFIG_DEEP_SLEEP)
 159 #define CONFIG_BOARD_EARLY_INIT_F
 160 #endif
 161
 162 #ifndef CONFIG_SYS_TEXT_BASE
 163 #define CONFIG_SYS_TEXT_BASE    0xeff40000
 164 #endif
 165
 166 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 167 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 168 #endif
 169
 170 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
 171 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
 172 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
 173 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
 174 #define CONFIG_PCI_INDIRECT_BRIDGE
 175 #define CONFIG_PCIE1                    /* PCIE controller 1 */
 176 #define CONFIG_PCIE2                    /* PCIE controller 2 */
 177 #define CONFIG_PCIE3                    /* PCIE controller 3 */
 178 #define CONFIG_PCIE4                    /* PCIE controller 4 */
 179
 180 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
 181 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
 182
 183 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
 184
 185 #define CONFIG_ENV_OVERWRITE
 186
 187 #ifndef CONFIG_SYS_NO_FLASH
 188 #define CONFIG_FLASH_CFI_DRIVER
 189 #define CONFIG_SYS_FLASH_CFI
 190 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 191 #endif
 192
 193 #if defined(CONFIG_SPIFLASH)
 194 #define CONFIG_SYS_EXTRA_ENV_RELOC
 195 #define CONFIG_ENV_IS_IN_SPI_FLASH
 196 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 197 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 198 #define CONFIG_ENV_SECT_SIZE            0x10000
 199 #elif defined(CONFIG_SDCARD)
 200 #define CONFIG_SYS_EXTRA_ENV_RELOC
 201 #define CONFIG_ENV_IS_IN_MMC
 202 #define CONFIG_SYS_MMC_ENV_DEV          0
 203 #define CONFIG_ENV_SIZE                 0x2000
 204 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 205 #elif defined(CONFIG_NAND)
 206 #ifdef CONFIG_SECURE_BOOT
 207 #define CONFIG_RAMBOOT_NAND
 208 #define CONFIG_BOOTSCRIPT_COPY_RAM
 209 #endif
 210 #define CONFIG_SYS_EXTRA_ENV_RELOC
 211 #define CONFIG_ENV_IS_IN_NAND
 212 #define CONFIG_ENV_SIZE                 0x2000
 213 #define CONFIG_ENV_OFFSET               (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 214 #else
 215 #define CONFIG_ENV_IS_IN_FLASH
 216 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 217 #define CONFIG_ENV_SIZE         0x2000
 218 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 219 #endif
 220
 221 #define CONFIG_SYS_CLK_FREQ     100000000
 222 #define CONFIG_DDR_CLK_FREQ     66666666
 223
 224 /*
 225  * These can be toggled for performance analysis, otherwise use default.
 226  */
 227 #define CONFIG_SYS_CACHE_STASHING
 228 #define CONFIG_BACKSIDE_L2_CACHE
 229 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 230 #define CONFIG_BTB                      /* toggle branch predition */
 231 #define CONFIG_DDR_ECC
 232 #ifdef CONFIG_DDR_ECC
 233 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 234 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 235 #endif
 236
 237 #define CONFIG_ENABLE_36BIT_PHYS
 238
 239 #define CONFIG_ADDR_MAP
 240 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 241
 242 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 243 #define CONFIG_SYS_MEMTEST_END          0x00400000
 244 #define CONFIG_SYS_ALT_MEMTEST
 245 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 246
 247 /*
 248  *  Config the L3 Cache as L3 SRAM
 249  */
 250 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 251 /*
 252  * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
 253  * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
 254  * (CONFIG_SYS_INIT_L3_VADDR) will be different.
 255  */
 256 #define CONFIG_SYS_INIT_L3_VADDR        0xFFFC0000
 257 #define CONFIG_SYS_L3_SIZE              256 << 10
 258 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
 259 #ifdef CONFIG_RAMBOOT_PBL
 260 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 261 #endif
 262 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 263 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 264 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 265 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 266
 267 #define CONFIG_SYS_DCSRBAR              0xf0000000
 268 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 269
 270 /*
 271  * DDR Setup
 272  */
 273 #define CONFIG_VERY_BIG_RAM
 274 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 275 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 276
 277 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
 278 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 279 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 280
 281 #define CONFIG_DDR_SPD
 282 #ifndef CONFIG_SYS_FSL_DDR4
 283 #define CONFIG_SYS_FSL_DDR3
 284 #endif
 285
 286 #define CONFIG_SYS_SPD_BUS_NUM  0
 287 #define SPD_EEPROM_ADDRESS      0x51
 288
 289 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 290
 291 /*
 292  * IFC Definitions
 293  */
 294 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 295 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 296
 297 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
 298 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
 299                                 CSPR_PORT_SIZE_16 | \
 300                                 CSPR_MSEL_NOR | \
 301                                 CSPR_V)
 302 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 303
 304 /*
 305  * TDM Definition
 306  */
 307 #define T1040_TDM_QUIRK_CCSR_BASE       0xfe000000
 308
 309 /* NOR Flash Timing Params */
 310 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 311 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 312                                 FTIM0_NOR_TEADC(0x5) | \
 313                                 FTIM0_NOR_TEAHC(0x5))
 314 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 315                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 316                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 317 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 318                                 FTIM2_NOR_TCH(0x4) | \
 319                                 FTIM2_NOR_TWPH(0x0E) | \
 320                                 FTIM2_NOR_TWP(0x1c))
 321 #define CONFIG_SYS_NOR_FTIM3    0x0
 322
 323 #define CONFIG_SYS_FLASH_QUIET_TEST
 324 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 325
 326 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 327 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 328 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 329 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 330
 331 #define CONFIG_SYS_FLASH_EMPTY_INFO
 332 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 333
 334 /* CPLD on IFC */
 335 #define CPLD_LBMAP_MASK                 0x3F
 336 #define CPLD_BANK_SEL_MASK              0x07
 337 #define CPLD_BANK_OVERRIDE              0x40
 338 #define CPLD_LBMAP_ALTBANK              0x44 /* BANK OR | BANK 4 */
 339 #define CPLD_LBMAP_DFLTBANK             0x40 /* BANK OR | BANK0 */
 340 #define CPLD_LBMAP_RESET                0xFF
 341 #define CPLD_LBMAP_SHIFT                0x03
 342
 343 #if defined(CONFIG_TARGET_T1042RDB_PI)
 344 #define CPLD_DIU_SEL_DFP                0x80
 345 #elif defined(CONFIG_TARGET_T1042D4RDB)
 346 #define CPLD_DIU_SEL_DFP                0xc0
 347 #endif
 348
 349 #if defined(CONFIG_TARGET_T1040D4RDB)
 350 #define CPLD_INT_MASK_ALL               0xFF
 351 #define CPLD_INT_MASK_THERM             0x80
 352 #define CPLD_INT_MASK_DVI_DFP           0x40
 353 #define CPLD_INT_MASK_QSGMII1           0x20
 354 #define CPLD_INT_MASK_QSGMII2           0x10
 355 #define CPLD_INT_MASK_SGMI1             0x08
 356 #define CPLD_INT_MASK_SGMI2             0x04
 357 #define CPLD_INT_MASK_TDMR1             0x02
 358 #define CPLD_INT_MASK_TDMR2             0x01
 359 #endif
 360
 361 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 362 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 363 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 364 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 365                                 | CSPR_PORT_SIZE_8 \
 366                                 | CSPR_MSEL_GPCM \
 367                                 | CSPR_V)
 368 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 369 #define CONFIG_SYS_CSOR2        0x0
 370 /* CPLD Timing parameters for IFC CS2 */
 371 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 372                                         FTIM0_GPCM_TEADC(0x0e) | \
 373                                         FTIM0_GPCM_TEAHC(0x0e))
 374 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 375                                         FTIM1_GPCM_TRAD(0x1f))
 376 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 377                                         FTIM2_GPCM_TCH(0x8) | \
 378                                         FTIM2_GPCM_TWP(0x1f))
 379 #define CONFIG_SYS_CS2_FTIM3            0x0
 380
 381 /* NAND Flash on IFC */
 382 #define CONFIG_NAND_FSL_IFC
 383 #define CONFIG_SYS_NAND_BASE            0xff800000
 384 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 385
 386 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 387 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 388                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 389                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 390                                 | CSPR_V)
 391 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 392
 393 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 394                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 395                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 396                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 397                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 398                                 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
 399                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 400
 401 #define CONFIG_SYS_NAND_ONFI_DETECTION
 402
 403 /* ONFI NAND Flash mode0 Timing Params */
 404 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 405                                         FTIM0_NAND_TWP(0x18)   | \
 406                                         FTIM0_NAND_TWCHT(0x07) | \
 407                                         FTIM0_NAND_TWH(0x0a))
 408 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 409                                         FTIM1_NAND_TWBE(0x39)  | \
 410                                         FTIM1_NAND_TRR(0x0e)   | \
 411                                         FTIM1_NAND_TRP(0x18))
 412 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 413                                         FTIM2_NAND_TREH(0x0a) | \
 414                                         FTIM2_NAND_TWHRE(0x1e))
 415 #define CONFIG_SYS_NAND_FTIM3           0x0
 416
 417 #define CONFIG_SYS_NAND_DDR_LAW         11
 418 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 419 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 420 #define CONFIG_CMD_NAND
 421
 422 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 423
 424 #if defined(CONFIG_NAND)
 425 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 426 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 427 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 428 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 429 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 430 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 431 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 432 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 433 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR_CSPR_EXT
 434 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 435 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 436 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 437 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 438 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 439 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 440 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 441 #else
 442 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 443 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 444 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 445 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 446 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 447 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 448 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 449 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 450 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 451 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 452 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 453 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 454 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 455 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 456 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 457 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 458 #endif
 459
 460 #ifdef CONFIG_SPL_BUILD
 461 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 462 #else
 463 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 464 #endif
 465
 466 #if defined(CONFIG_RAMBOOT_PBL)
 467 #define CONFIG_SYS_RAMBOOT
 468 #endif
 469
 470 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044
 471 #if defined(CONFIG_NAND)
 472 #define CONFIG_A008044_WORKAROUND
 473 #endif
 474 #endif
 475
 476 #define CONFIG_BOARD_EARLY_INIT_R
 477 #define CONFIG_MISC_INIT_R
 478
 479 #define CONFIG_HWCONFIG
 480
 481 /* define to use L1 as initial stack */
 482 #define CONFIG_L1_INIT_RAM
 483 #define CONFIG_SYS_INIT_RAM_LOCK
 484 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 485 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 486 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 487 /* The assembler doesn't like typecast */
 488 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 489         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 490           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 491 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 492
 493 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 494                                         GENERATED_GBL_DATA_SIZE)
 495 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 496
 497 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 498 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 499
 500 /* Serial Port - controlled on board with jumper J8
 501  * open - index 2
 502  * shorted - index 1
 503  */
 504 #define CONFIG_CONS_INDEX       1
 505 #define CONFIG_SYS_NS16550_SERIAL
 506 #define CONFIG_SYS_NS16550_REG_SIZE     1
 507 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 508
 509 #define CONFIG_SYS_BAUDRATE_TABLE       \
 510         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 511
 512 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 513 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 514 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 515 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 516
 517 #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB)
 518 /* Video */
 519 #define CONFIG_FSL_DIU_FB
 520
 521 #ifdef CONFIG_FSL_DIU_FB
 522 #define CONFIG_FSL_DIU_CH7301
 523 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 524 #define CONFIG_CMD_BMP
 525 #define CONFIG_VIDEO_LOGO
 526 #define CONFIG_VIDEO_BMP_LOGO
 527 #endif
 528 #endif
 529
 530 /* I2C */
 531 #define CONFIG_SYS_I2C
 532 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 533 #define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C speed in Hz */
 534 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 535 #define CONFIG_SYS_FSL_I2C3_SPEED       400000
 536 #define CONFIG_SYS_FSL_I2C4_SPEED       400000
 537 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 538 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 539 #define CONFIG_SYS_FSL_I2C3_SLAVE       0x7F
 540 #define CONFIG_SYS_FSL_I2C4_SLAVE       0x7F
 541 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 542 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 543 #define CONFIG_SYS_FSL_I2C3_OFFSET      0x119000
 544 #define CONFIG_SYS_FSL_I2C4_OFFSET      0x119100
 545
 546 /* I2C bus multiplexer */
 547 #define I2C_MUX_PCA_ADDR                0x70
 548 #define I2C_MUX_CH_DEFAULT      0x8
 549
 550 #if defined(CONFIG_TARGET_T1042RDB_PI)  || \
 551         defined(CONFIG_TARGET_T1040D4RDB)       || \
 552         defined(CONFIG_TARGET_T1042D4RDB)
 553 /* LDI/DVI Encoder for display */
 554 #define CONFIG_SYS_I2C_LDI_ADDR         0x38
 555 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 556
 557 /*
 558  * RTC configuration
 559  */
 560 #define RTC
 561 #define CONFIG_RTC_DS1337               1
 562 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 563
 564 /*DVI encoder*/
 565 #define CONFIG_HDMI_ENCODER_I2C_ADDR  0x75
 566 #endif
 567
 568 /*
 569  * eSPI - Enhanced SPI
 570  */
 571 #define CONFIG_SPI_FLASH_BAR
 572 #define CONFIG_SF_DEFAULT_SPEED         10000000
 573 #define CONFIG_SF_DEFAULT_MODE          0
 574 #define CONFIG_ENV_SPI_BUS              0
 575 #define CONFIG_ENV_SPI_CS               0
 576 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 577 #define CONFIG_ENV_SPI_MODE             0
 578
 579 /*
 580  * General PCI
 581  * Memory space is mapped 1-1, but I/O space must start from 0.
 582  */
 583
 584 #ifdef CONFIG_PCI
 585 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 586 #ifdef CONFIG_PCIE1
 587 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 588 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 589 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 590 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 591 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 592 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 593 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 594 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 595 #endif
 596
 597 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 598 #ifdef CONFIG_PCIE2
 599 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 600 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 601 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 602 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 603 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 604 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 605 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 606 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 607 #endif
 608
 609 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 610 #ifdef CONFIG_PCIE3
 611 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 612 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 613 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 614 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 615 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 616 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 617 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 618 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 619 #endif
 620
 621 /* controller 4, Base address 203000 */
 622 #ifdef CONFIG_PCIE4
 623 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
 624 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 625 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
 626 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 627 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
 628 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 629 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 630 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 631 #endif
 632
 633 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 634 #define CONFIG_DOS_PARTITION
 635 #endif  /* CONFIG_PCI */
 636
 637 /* SATA */
 638 #define CONFIG_FSL_SATA_V2
 639 #ifdef CONFIG_FSL_SATA_V2
 640 #define CONFIG_LIBATA
 641 #define CONFIG_FSL_SATA
 642
 643 #define CONFIG_SYS_SATA_MAX_DEVICE      1
 644 #define CONFIG_SATA1
 645 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 646 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 647
 648 #define CONFIG_LBA48
 649 #define CONFIG_CMD_SATA
 650 #define CONFIG_DOS_PARTITION
 651 #endif
 652
 653 /*
 654 * USB
 655 */
 656 #define CONFIG_HAS_FSL_DR_USB
 657
 658 #ifdef CONFIG_HAS_FSL_DR_USB
 659 #define CONFIG_USB_EHCI
 660
 661 #ifdef CONFIG_USB_EHCI
 662 #define CONFIG_USB_EHCI_FSL
 663 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 664 #endif
 665 #endif
 666
 667 #define CONFIG_MMC
 668
 669 #ifdef CONFIG_MMC
 670 #define CONFIG_FSL_ESDHC
 671 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 672 #define CONFIG_GENERIC_MMC
 673 #define CONFIG_DOS_PARTITION
 674 #endif
 675
 676 /* Qman/Bman */
 677 #ifndef CONFIG_NOBQFMAN
 678 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 679 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 680 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 681 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 682 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 683 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 684 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 685 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 686 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 687 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 688                                         CONFIG_SYS_BMAN_CENA_SIZE)
 689 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 690 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 691 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 692 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 693 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 694 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 695 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 696 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 697 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 698 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 699 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 700                                         CONFIG_SYS_QMAN_CENA_SIZE)
 701 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 702 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 703
 704 #define CONFIG_SYS_DPAA_FMAN
 705 #define CONFIG_SYS_DPAA_PME
 706
 707 #define CONFIG_QE
 708 #define CONFIG_U_QE
 709
 710 /* Default address of microcode for the Linux Fman driver */
 711 #if defined(CONFIG_SPIFLASH)
 712 /*
 713  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 714  * env, so we got 0x110000.
 715  */
 716 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 717 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 718 #elif defined(CONFIG_SDCARD)
 719 /*
 720  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 721  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 722  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 723  */
 724 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 725 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 726 #elif defined(CONFIG_NAND)
 727 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 728 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
 729 #else
 730 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 731 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 732 #endif
 733
 734 #if defined(CONFIG_SPIFLASH)
 735 #define CONFIG_SYS_QE_FW_ADDR           0x130000
 736 #elif defined(CONFIG_SDCARD)
 737 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 738 #elif defined(CONFIG_NAND)
 739 #define CONFIG_SYS_QE_FW_ADDR           (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 740 #else
 741 #define CONFIG_SYS_QE_FW_ADDR           0xEFF10000
 742 #endif
 743
 744 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 745 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 746 #endif /* CONFIG_NOBQFMAN */
 747
 748 #ifdef CONFIG_SYS_DPAA_FMAN
 749 #define CONFIG_FMAN_ENET
 750 #define CONFIG_PHY_VITESSE
 751 #define CONFIG_PHY_REALTEK
 752 #endif
 753
 754 #ifdef CONFIG_FMAN_ENET
 755 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
 756 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x03
 757 #elif defined(CONFIG_TARGET_T1040D4RDB)
 758 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x01
 759 #elif defined(CONFIG_TARGET_T1042D4RDB)
 760 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x02
 761 #define CONFIG_SYS_SGMII2_PHY_ADDR             0x03
 762 #define CONFIG_SYS_SGMII3_PHY_ADDR             0x01
 763 #endif
 764
 765 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
 766 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x04
 767 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x05
 768 #else
 769 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x01
 770 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x02
 771 #endif
 772
 773 /* Enable VSC9953 L2 Switch driver on T1040 SoC */
 774 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
 775 #define CONFIG_VSC9953
 776 #define CONFIG_CMD_ETHSW
 777 #ifdef CONFIG_TARGET_T1040RDB
 778 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x04
 779 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x08
 780 #else
 781 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x08
 782 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x0c
 783 #endif
 784 #endif
 785
 786 #define CONFIG_MII              /* MII PHY management */
 787 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 788 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 789 #endif
 790
 791 /*
 792  * Environment
 793  */
 794 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 795 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 796
 797 /*
 798  * Command line configuration.
 799  */
 800 #ifdef CONFIG_TARGET_T1042RDB_PI
 801 #define CONFIG_CMD_DATE
 802 #endif
 803 #define CONFIG_CMD_ERRATA
 804 #define CONFIG_CMD_IRQ
 805 #define CONFIG_CMD_REGINFO
 806
 807 #ifdef CONFIG_PCI
 808 #define CONFIG_CMD_PCI
 809 #endif
 810
 811 /* Hash command with SHA acceleration supported in hardware */
 812 #ifdef CONFIG_FSL_CAAM
 813 #define CONFIG_CMD_HASH
 814 #define CONFIG_SHA_HW_ACCEL
 815 #endif
 816
 817 /*
 818  * Miscellaneous configurable options
 819  */
 820 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 821 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 822 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 823 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 824 #ifdef CONFIG_CMD_KGDB
 825 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 826 #else
 827 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 828 #endif
 829 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 830 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 831 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 832
 833 /*
 834  * For booting Linux, the board info and command line data
 835  * have to be in the first 64 MB of memory, since this is
 836  * the maximum mapped by the Linux kernel during initialization.
 837  */
 838 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 839 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 840
 841 #ifdef CONFIG_CMD_KGDB
 842 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 843 #endif
 844
 845 /*
 846  * Dynamic MTD Partition support with mtdparts
 847  */
 848 #ifndef CONFIG_SYS_NO_FLASH
 849 #define CONFIG_MTD_DEVICE
 850 #define CONFIG_MTD_PARTITIONS
 851 #define CONFIG_CMD_MTDPARTS
 852 #define CONFIG_FLASH_CFI_MTD
 853 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
 854                         "spi0=spife110000.0"
 855 #define MTDPARTS_DEFAULT        "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
 856                                 "128k(dtb),96m(fs),-(user);"\
 857                                 "fff800000.flash:2m(uboot),9m(kernel),"\
 858                                 "128k(dtb),96m(fs),-(user);spife110000.0:" \
 859                                 "2m(uboot),9m(kernel),128k(dtb),-(user)"
 860 #endif
 861
 862 /*
 863  * Environment Configuration
 864  */
 865 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 866 #define CONFIG_BOOTFILE         "uImage"
 867 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 868
 869 /* default location for tftp and bootm */
 870 #define CONFIG_LOADADDR         1000000
 871
 872
 873 #define CONFIG_BAUDRATE 115200
 874
 875 #define __USB_PHY_TYPE  utmi
 876 #define RAMDISKFILE     "t104xrdb/ramdisk.uboot"
 877
 878 #ifdef CONFIG_TARGET_T1040RDB
 879 #define FDTFILE         "t1040rdb/t1040rdb.dtb"
 880 #elif defined(CONFIG_TARGET_T1042RDB_PI)
 881 #define FDTFILE         "t1042rdb_pi/t1042rdb_pi.dtb"
 882 #elif defined(CONFIG_TARGET_T1042RDB)
 883 #define FDTFILE         "t1042rdb/t1042rdb.dtb"
 884 #elif defined(CONFIG_TARGET_T1040D4RDB)
 885 #define FDTFILE         "t1042rdb/t1040d4rdb.dtb"
 886 #elif defined(CONFIG_TARGET_T1042D4RDB)
 887 #define FDTFILE         "t1042rdb/t1042d4rdb.dtb"
 888 #endif
 889
 890 #ifdef CONFIG_FSL_DIU_FB
 891 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
 892 #else
 893 #define DIU_ENVIRONMENT
 894 #endif
 895
 896 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 897         "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;"                  \
 898         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 899         "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 900         "netdev=eth0\0"                                         \
 901         "video-mode=" __stringify(DIU_ENVIRONMENT) "\0"         \
 902         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 903         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 904         "tftpflash=tftpboot $loadaddr $uboot && "               \
 905         "protect off $ubootaddr +$filesize && "                 \
 906         "erase $ubootaddr +$filesize && "                       \
 907         "cp.b $loadaddr $ubootaddr $filesize && "               \
 908         "protect on $ubootaddr +$filesize && "                  \
 909         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 910         "consoledev=ttyS0\0"                                    \
 911         "ramdiskaddr=2000000\0"                                 \
 912         "ramdiskfile=" __stringify(RAMDISKFILE) "\0"            \
 913         "fdtaddr=1e00000\0"                                     \
 914         "fdtfile=" __stringify(FDTFILE) "\0"                    \
 915         "bdev=sda3\0"
 916
 917 #define CONFIG_LINUX                       \
 918         "setenv bootargs root=/dev/ram rw "            \
 919         "console=$consoledev,$baudrate $othbootargs;"  \
 920         "setenv ramdiskaddr 0x02000000;"               \
 921         "setenv fdtaddr 0x00c00000;"                   \
 922         "setenv loadaddr 0x1000000;"                   \
 923         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 924
 925 #define CONFIG_HDBOOT                                   \
 926         "setenv bootargs root=/dev/$bdev rw "           \
 927         "console=$consoledev,$baudrate $othbootargs;"   \
 928         "tftp $loadaddr $bootfile;"                     \
 929         "tftp $fdtaddr $fdtfile;"                       \
 930         "bootm $loadaddr - $fdtaddr"
 931
 932 #define CONFIG_NFSBOOTCOMMAND                   \
 933         "setenv bootargs root=/dev/nfs rw "     \
 934         "nfsroot=$serverip:$rootpath "          \
 935         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 936         "console=$consoledev,$baudrate $othbootargs;"   \
 937         "tftp $loadaddr $bootfile;"             \
 938         "tftp $fdtaddr $fdtfile;"               \
 939         "bootm $loadaddr - $fdtaddr"
 940
 941 #define CONFIG_RAMBOOTCOMMAND                           \
 942         "setenv bootargs root=/dev/ram rw "             \
 943         "console=$consoledev,$baudrate $othbootargs;"   \
 944         "tftp $ramdiskaddr $ramdiskfile;"               \
 945         "tftp $loadaddr $bootfile;"                     \
 946         "tftp $fdtaddr $fdtfile;"                       \
 947         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 948
 949 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 950
 951 #include <asm/fsl_secure_boot.h>
 952
 953 #endif  /* __CONFIG_H */