include/configs/T104xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #include <linux/stringify.h>
  11
  12 /*
  13  * T104x RDB board configuration file
  14  */
  15 #include <asm/config_mpc85xx.h>
  16
  17 #ifdef CONFIG_RAMBOOT_PBL
  18 #define RESET_VECTOR_OFFSET             0x27FFC
  19 #define BOOT_PAGE_OFFSET                0x27000
  20
  21 #ifdef CONFIG_MTD_RAW_NAND
  22 #ifdef CONFIG_NXP_ESBC
  23 #define CONFIG_U_BOOT_HDR_SIZE          (16 << 10)
  24 /*
  25  * HDR would be appended at end of image and copied to DDR along
  26  * with U-Boot image.
  27  */
  28 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) + \
  29                                          CONFIG_U_BOOT_HDR_SIZE)
  30 #else
  31 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  32 #endif
  33 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  34 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  35 #ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
  36 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  37 #endif
  38 #endif
  39
  40 #ifdef CONFIG_SPIFLASH
  41 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  42 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  43 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  44 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  45 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  46 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  47 #ifndef CONFIG_SPL_BUILD
  48 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  49 #endif
  50 #endif
  51
  52 #ifdef CONFIG_SDCARD
  53 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  54 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  55 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
  56 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
  57 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  58 #ifndef CONFIG_SPL_BUILD
  59 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  60 #endif
  61 #endif
  62
  63 #endif
  64
  65 /* High Level Configuration Options */
  66 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  67
  68 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  69 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  70 #endif
  71
  72 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  73 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  74 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  75 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  76 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  77 #define CONFIG_PCIE4                    /* PCIE controller 4 */
  78
  79 #if defined(CONFIG_SPIFLASH)
  80 #elif defined(CONFIG_MTD_RAW_NAND)
  81 #ifdef CONFIG_NXP_ESBC
  82 #define CONFIG_RAMBOOT_NAND
  83 #define CONFIG_BOOTSCRIPT_COPY_RAM
  84 #endif
  85 #endif
  86
  87 /*
  88  * These can be toggled for performance analysis, otherwise use default.
  89  */
  90 #define CONFIG_SYS_CACHE_STASHING
  91 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  92 #ifdef CONFIG_DDR_ECC
  93 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  94 #endif
  95
  96 #define CONFIG_ENABLE_36BIT_PHYS
  97
  98 /*
  99  *  Config the L3 Cache as L3 SRAM
 100  */
 101 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 102 /*
 103  * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
 104  * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
 105  * (CONFIG_SYS_INIT_L3_VADDR) will be different.
 106  */
 107 #define CONFIG_SYS_INIT_L3_VADDR        0xFFFC0000
 108 #define CONFIG_SYS_L3_SIZE              256 << 10
 109 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
 110 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
 111
 112 #define CONFIG_SYS_DCSRBAR              0xf0000000
 113 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 114
 115 /*
 116  * DDR Setup
 117  */
 118 #define CONFIG_VERY_BIG_RAM
 119 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 120 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 121
 122 #define CONFIG_SYS_SPD_BUS_NUM  0
 123 #define SPD_EEPROM_ADDRESS      0x51
 124
 125 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 126
 127 /*
 128  * IFC Definitions
 129  */
 130 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 131 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 132
 133 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
 134 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
 135                                 CSPR_PORT_SIZE_16 | \
 136                                 CSPR_MSEL_NOR | \
 137                                 CSPR_V)
 138 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 139
 140 /*
 141  * TDM Definition
 142  */
 143 #define T1040_TDM_QUIRK_CCSR_BASE       0xfe000000
 144
 145 /* NOR Flash Timing Params */
 146 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 147 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 148                                 FTIM0_NOR_TEADC(0x5) | \
 149                                 FTIM0_NOR_TEAHC(0x5))
 150 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 151                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 152                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 153 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 154                                 FTIM2_NOR_TCH(0x4) | \
 155                                 FTIM2_NOR_TWPH(0x0E) | \
 156                                 FTIM2_NOR_TWP(0x1c))
 157 #define CONFIG_SYS_NOR_FTIM3    0x0
 158
 159 #define CONFIG_SYS_FLASH_QUIET_TEST
 160 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 161
 162 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 163 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 164 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 165
 166 #define CONFIG_SYS_FLASH_EMPTY_INFO
 167 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 168
 169 /* CPLD on IFC */
 170 #define CPLD_LBMAP_MASK                 0x3F
 171 #define CPLD_BANK_SEL_MASK              0x07
 172 #define CPLD_BANK_OVERRIDE              0x40
 173 #define CPLD_LBMAP_ALTBANK              0x44 /* BANK OR | BANK 4 */
 174 #define CPLD_LBMAP_DFLTBANK             0x40 /* BANK OR | BANK0 */
 175 #define CPLD_LBMAP_RESET                0xFF
 176 #define CPLD_LBMAP_SHIFT                0x03
 177
 178 #if defined(CONFIG_TARGET_T1042RDB_PI)
 179 #define CPLD_DIU_SEL_DFP                0x80
 180 #elif defined(CONFIG_TARGET_T1042D4RDB)
 181 #define CPLD_DIU_SEL_DFP                0xc0
 182 #endif
 183
 184 #if defined(CONFIG_TARGET_T1040D4RDB)
 185 #define CPLD_INT_MASK_ALL               0xFF
 186 #define CPLD_INT_MASK_THERM             0x80
 187 #define CPLD_INT_MASK_DVI_DFP           0x40
 188 #define CPLD_INT_MASK_QSGMII1           0x20
 189 #define CPLD_INT_MASK_QSGMII2           0x10
 190 #define CPLD_INT_MASK_SGMI1             0x08
 191 #define CPLD_INT_MASK_SGMI2             0x04
 192 #define CPLD_INT_MASK_TDMR1             0x02
 193 #define CPLD_INT_MASK_TDMR2             0x01
 194 #endif
 195
 196 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 197 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 198 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 199 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 200                                 | CSPR_PORT_SIZE_8 \
 201                                 | CSPR_MSEL_GPCM \
 202                                 | CSPR_V)
 203 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 204 #define CONFIG_SYS_CSOR2        0x0
 205 /* CPLD Timing parameters for IFC CS2 */
 206 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 207                                         FTIM0_GPCM_TEADC(0x0e) | \
 208                                         FTIM0_GPCM_TEAHC(0x0e))
 209 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 210                                         FTIM1_GPCM_TRAD(0x1f))
 211 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 212                                         FTIM2_GPCM_TCH(0x8) | \
 213                                         FTIM2_GPCM_TWP(0x1f))
 214 #define CONFIG_SYS_CS2_FTIM3            0x0
 215
 216 /* NAND Flash on IFC */
 217 #define CONFIG_SYS_NAND_BASE            0xff800000
 218 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 219
 220 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 221 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 222                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 223                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 224                                 | CSPR_V)
 225 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 226
 227 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 228                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 229                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 230                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 231                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 232                                 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
 233                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 234
 235 /* ONFI NAND Flash mode0 Timing Params */
 236 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 237                                         FTIM0_NAND_TWP(0x18)   | \
 238                                         FTIM0_NAND_TWCHT(0x07) | \
 239                                         FTIM0_NAND_TWH(0x0a))
 240 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 241                                         FTIM1_NAND_TWBE(0x39)  | \
 242                                         FTIM1_NAND_TRR(0x0e)   | \
 243                                         FTIM1_NAND_TRP(0x18))
 244 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 245                                         FTIM2_NAND_TREH(0x0a) | \
 246                                         FTIM2_NAND_TWHRE(0x1e))
 247 #define CONFIG_SYS_NAND_FTIM3           0x0
 248
 249 #define CONFIG_SYS_NAND_DDR_LAW         11
 250 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 251 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 252
 253 #if defined(CONFIG_MTD_RAW_NAND)
 254 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 255 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 256 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 257 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 258 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 259 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 260 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 261 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 262 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR_CSPR_EXT
 263 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 264 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 265 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 266 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 267 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 268 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 269 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 270 #else
 271 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 272 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 273 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 274 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 275 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 276 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 277 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 278 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 279 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 280 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 281 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 282 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 283 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 284 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 285 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 286 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 287 #endif
 288
 289 #if defined(CONFIG_RAMBOOT_PBL)
 290 #define CONFIG_SYS_RAMBOOT
 291 #endif
 292
 293 #define CONFIG_HWCONFIG
 294
 295 /* define to use L1 as initial stack */
 296 #define CONFIG_L1_INIT_RAM
 297 #define CONFIG_SYS_INIT_RAM_LOCK
 298 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 299 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 300 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 301 /* The assembler doesn't like typecast */
 302 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 303         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 304           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 305 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 306
 307 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 308
 309 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 310
 311 /* Serial Port - controlled on board with jumper J8
 312  * open - index 2
 313  * shorted - index 1
 314  */
 315 #define CONFIG_SYS_NS16550_SERIAL
 316 #define CONFIG_SYS_NS16550_REG_SIZE     1
 317 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 318
 319 #define CONFIG_SYS_BAUDRATE_TABLE       \
 320         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 321
 322 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 323 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 324 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 325 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 326
 327 /* I2C bus multiplexer */
 328 #define I2C_MUX_PCA_ADDR                0x70
 329 #define I2C_MUX_CH_DEFAULT      0x8
 330
 331 #if defined(CONFIG_TARGET_T1042RDB_PI)  || \
 332         defined(CONFIG_TARGET_T1040D4RDB)       || \
 333         defined(CONFIG_TARGET_T1042D4RDB)
 334 /* LDI/DVI Encoder for display */
 335 #define CONFIG_SYS_I2C_LDI_ADDR         0x38
 336 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 337 #define CONFIG_SYS_I2C_DVI_BUS_NUM      0
 338
 339 /*
 340  * RTC configuration
 341  */
 342 #define RTC
 343 #define CONFIG_RTC_DS1337               1
 344 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 345
 346 /*DVI encoder*/
 347 #define CONFIG_HDMI_ENCODER_I2C_ADDR  0x75
 348 #endif
 349
 350 /*
 351  * eSPI - Enhanced SPI
 352  */
 353
 354 /*
 355  * General PCI
 356  * Memory space is mapped 1-1, but I/O space must start from 0.
 357  */
 358
 359 #ifdef CONFIG_PCI
 360 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 361 #ifdef CONFIG_PCIE1
 362 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 363 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 364 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 365 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 366 #endif
 367
 368 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 369 #ifdef CONFIG_PCIE2
 370 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 371 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 372 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 373 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 374 #endif
 375
 376 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 377 #ifdef CONFIG_PCIE3
 378 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 379 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 380 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 381 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 382 #endif
 383
 384 /* controller 4, Base address 203000 */
 385 #ifdef CONFIG_PCIE4
 386 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
 387 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
 388 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
 389 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 390 #endif
 391
 392 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 393 #endif  /* CONFIG_PCI */
 394
 395 /* SATA */
 396 #define CONFIG_FSL_SATA_V2
 397 #ifdef CONFIG_FSL_SATA_V2
 398 #define CONFIG_SATA1
 399 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 400 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 401
 402 #define CONFIG_LBA48
 403 #endif
 404
 405 /*
 406 * USB
 407 */
 408 #define CONFIG_HAS_FSL_DR_USB
 409
 410 #ifdef CONFIG_HAS_FSL_DR_USB
 411 #ifdef CONFIG_USB_EHCI_HCD
 412 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 413 #endif
 414 #endif
 415
 416 #ifdef CONFIG_MMC
 417 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 418 #endif
 419
 420 /* Qman/Bman */
 421 #ifndef CONFIG_NOBQFMAN
 422 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 423 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 424 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 425 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 426 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 427 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 428 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 429 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 430 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 431                                         CONFIG_SYS_BMAN_CENA_SIZE)
 432 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 433 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 434 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 435 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 436 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 437 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 438 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 439 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 440 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 441 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 442 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 443                                         CONFIG_SYS_QMAN_CENA_SIZE)
 444 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 445 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 446
 447 #define CONFIG_SYS_DPAA_FMAN
 448 #define CONFIG_SYS_DPAA_PME
 449
 450 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 451 #endif /* CONFIG_NOBQFMAN */
 452
 453 #ifdef CONFIG_FMAN_ENET
 454 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
 455 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x03
 456 #elif defined(CONFIG_TARGET_T1040D4RDB)
 457 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x01
 458 #elif defined(CONFIG_TARGET_T1042D4RDB)
 459 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x02
 460 #define CONFIG_SYS_SGMII2_PHY_ADDR             0x03
 461 #define CONFIG_SYS_SGMII3_PHY_ADDR             0x01
 462 #endif
 463
 464 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
 465 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x04
 466 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x05
 467 #else
 468 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x01
 469 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x02
 470 #endif
 471
 472 /* Enable VSC9953 L2 Switch driver on T1040 SoC */
 473 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
 474 #define CONFIG_VSC9953
 475 #ifdef CONFIG_TARGET_T1040RDB
 476 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x04
 477 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x08
 478 #else
 479 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x08
 480 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x0c
 481 #endif
 482 #endif
 483 #endif
 484
 485 /*
 486  * Environment
 487  */
 488 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 489 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 490
 491 /*
 492  * Miscellaneous configurable options
 493  */
 494
 495 /*
 496  * For booting Linux, the board info and command line data
 497  * have to be in the first 64 MB of memory, since this is
 498  * the maximum mapped by the Linux kernel during initialization.
 499  */
 500 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 501 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 502
 503 /*
 504  * Dynamic MTD Partition support with mtdparts
 505  */
 506
 507 /*
 508  * Environment Configuration
 509  */
 510 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 511 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 512
 513 #define __USB_PHY_TYPE  utmi
 514 #define RAMDISKFILE     "t104xrdb/ramdisk.uboot"
 515
 516 #ifdef CONFIG_TARGET_T1040RDB
 517 #define FDTFILE         "t1040rdb/t1040rdb.dtb"
 518 #elif defined(CONFIG_TARGET_T1042RDB_PI)
 519 #define FDTFILE         "t1042rdb_pi/t1042rdb_pi.dtb"
 520 #elif defined(CONFIG_TARGET_T1042RDB)
 521 #define FDTFILE         "t1042rdb/t1042rdb.dtb"
 522 #elif defined(CONFIG_TARGET_T1040D4RDB)
 523 #define FDTFILE         "t1042rdb/t1040d4rdb.dtb"
 524 #elif defined(CONFIG_TARGET_T1042D4RDB)
 525 #define FDTFILE         "t1042rdb/t1042d4rdb.dtb"
 526 #endif
 527
 528 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 529         "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;"                  \
 530         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 531         "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 532         "netdev=eth0\0"                                         \
 533         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 534         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 535         "tftpflash=tftpboot $loadaddr $uboot && "               \
 536         "protect off $ubootaddr +$filesize && "                 \
 537         "erase $ubootaddr +$filesize && "                       \
 538         "cp.b $loadaddr $ubootaddr $filesize && "               \
 539         "protect on $ubootaddr +$filesize && "                  \
 540         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 541         "consoledev=ttyS0\0"                                    \
 542         "ramdiskaddr=2000000\0"                                 \
 543         "ramdiskfile=" __stringify(RAMDISKFILE) "\0"            \
 544         "fdtaddr=1e00000\0"                                     \
 545         "fdtfile=" __stringify(FDTFILE) "\0"                    \
 546         "bdev=sda3\0"
 547
 548 #include <asm/fsl_secure_boot.h>
 549
 550 #endif  /* __CONFIG_H */