include/configs/T104xRDB.h

   1 /*
   2 + * Copyright 2014 Freescale Semiconductor, Inc.
   3 + *
   4 + * SPDX-License-Identifier:     GPL-2.0+
   5 + */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 /*
  11  * T104x RDB board configuration file
  12  */
  13 #define CONFIG_T104xRDB
  14 #define CONFIG_DISPLAY_BOARDINFO
  15
  16 #define CONFIG_E500                     /* BOOKE e500 family */
  17 #include <asm/config_mpc85xx.h>
  18
  19 #ifdef CONFIG_RAMBOOT_PBL
  20
  21 #ifndef CONFIG_SECURE_BOOT
  22 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
  23 #else
  24 #define CONFIG_SYS_FSL_PBL_PBI \
  25                 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg
  26 #endif
  27
  28 #ifdef CONFIG_T1040RDB
  29 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg
  30 #endif
  31 #ifdef CONFIG_T1042RDB_PI
  32 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_rcw.cfg
  33 #endif
  34 #ifdef CONFIG_T1042RDB
  35 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg
  36 #endif
  37 #ifdef CONFIG_T1040D4RDB
  38 #define CONFIG_SYS_FSL_PBL_RCW \
  39 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_rcw.cfg
  40 #endif
  41 #ifdef CONFIG_T1042D4RDB
  42 #define CONFIG_SYS_FSL_PBL_RCW \
  43 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
  44 #endif
  45
  46 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  47 #define CONFIG_SPL_SERIAL_SUPPORT
  48 #define CONFIG_SPL_FLUSH_IMAGE
  49 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  50 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  51 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  52 #define CONFIG_SPL_I2C_SUPPORT
  53 #define CONFIG_FSL_LAW                 /* Use common FSL init code */
  54 #define CONFIG_SYS_TEXT_BASE            0x30001000
  55 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  56 #define CONFIG_SPL_PAD_TO               0x40000
  57 #define CONFIG_SPL_MAX_SIZE             0x28000
  58 #ifdef CONFIG_SPL_BUILD
  59 #define CONFIG_SPL_SKIP_RELOCATE
  60 #define CONFIG_SPL_COMMON_INIT_DDR
  61 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  62 #define CONFIG_SYS_NO_FLASH
  63 #endif
  64 #define RESET_VECTOR_OFFSET             0x27FFC
  65 #define BOOT_PAGE_OFFSET                0x27000
  66
  67 #ifdef CONFIG_NAND
  68 #define CONFIG_SPL_NAND_SUPPORT
  69 #ifdef CONFIG_SECURE_BOOT
  70 #define CONFIG_U_BOOT_HDR_SIZE          (16 << 10)
  71 /*
  72  * HDR would be appended at end of image and copied to DDR along
  73  * with U-Boot image.
  74  */
  75 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) + \
  76                                          CONFIG_U_BOOT_HDR_SIZE)
  77 #else
  78 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  79 #endif
  80 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  81 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  82 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  83 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  84 #define CONFIG_SPL_NAND_BOOT
  85 #endif
  86
  87 #ifdef CONFIG_SPIFLASH
  88 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  89 #define CONFIG_SPL_SPI_SUPPORT
  90 #define CONFIG_SPL_SPI_FLASH_SUPPORT
  91 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  92 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  93 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  94 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  95 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  96 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  97 #ifndef CONFIG_SPL_BUILD
  98 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  99 #endif
 100 #define CONFIG_SPL_SPI_BOOT
 101 #endif
 102
 103 #ifdef CONFIG_SDCARD
 104 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
 105 #define CONFIG_SPL_MMC_SUPPORT
 106 #define CONFIG_SPL_MMC_MINIMAL
 107 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
 108 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
 109 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
 110 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
 111 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
 112 #ifndef CONFIG_SPL_BUILD
 113 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 114 #endif
 115 #define CONFIG_SPL_MMC_BOOT
 116 #endif
 117
 118 #endif
 119
 120 /* High Level Configuration Options */
 121 #define CONFIG_BOOKE
 122 #define CONFIG_E500MC                   /* BOOKE e500mc family */
 123 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
 124 #define CONFIG_MP                       /* support multiple processors */
 125
 126 /* support deep sleep */
 127 #define CONFIG_DEEP_SLEEP
 128 #if defined(CONFIG_DEEP_SLEEP)
 129 #define CONFIG_BOARD_EARLY_INIT_F
 130 #define CONFIG_SILENT_CONSOLE
 131 #endif
 132
 133 #ifndef CONFIG_SYS_TEXT_BASE
 134 #define CONFIG_SYS_TEXT_BASE    0xeff40000
 135 #endif
 136
 137 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 138 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 139 #endif
 140
 141 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
 142 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
 143 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
 144 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
 145 #define CONFIG_PCI                      /* Enable PCI/PCIE */
 146 #define CONFIG_PCI_INDIRECT_BRIDGE
 147 #define CONFIG_PCIE1                    /* PCIE controller 1 */
 148 #define CONFIG_PCIE2                    /* PCIE controller 2 */
 149 #define CONFIG_PCIE3                    /* PCIE controller 3 */
 150 #define CONFIG_PCIE4                    /* PCIE controller 4 */
 151
 152 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
 153 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
 154
 155 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
 156
 157 #define CONFIG_ENV_OVERWRITE
 158
 159 #ifndef CONFIG_SYS_NO_FLASH
 160 #define CONFIG_FLASH_CFI_DRIVER
 161 #define CONFIG_SYS_FLASH_CFI
 162 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 163 #endif
 164
 165 #if defined(CONFIG_SPIFLASH)
 166 #define CONFIG_SYS_EXTRA_ENV_RELOC
 167 #define CONFIG_ENV_IS_IN_SPI_FLASH
 168 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 169 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 170 #define CONFIG_ENV_SECT_SIZE            0x10000
 171 #elif defined(CONFIG_SDCARD)
 172 #define CONFIG_SYS_EXTRA_ENV_RELOC
 173 #define CONFIG_ENV_IS_IN_MMC
 174 #define CONFIG_SYS_MMC_ENV_DEV          0
 175 #define CONFIG_ENV_SIZE                 0x2000
 176 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 177 #elif defined(CONFIG_NAND)
 178 #ifdef CONFIG_SECURE_BOOT
 179 #define CONFIG_RAMBOOT_NAND
 180 #define CONFIG_BOOTSCRIPT_COPY_RAM
 181 #endif
 182 #define CONFIG_SYS_EXTRA_ENV_RELOC
 183 #define CONFIG_ENV_IS_IN_NAND
 184 #define CONFIG_ENV_SIZE                 0x2000
 185 #define CONFIG_ENV_OFFSET               (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 186 #else
 187 #define CONFIG_ENV_IS_IN_FLASH
 188 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 189 #define CONFIG_ENV_SIZE         0x2000
 190 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 191 #endif
 192
 193 #define CONFIG_SYS_CLK_FREQ     100000000
 194 #define CONFIG_DDR_CLK_FREQ     66666666
 195
 196 /*
 197  * These can be toggled for performance analysis, otherwise use default.
 198  */
 199 #define CONFIG_SYS_CACHE_STASHING
 200 #define CONFIG_BACKSIDE_L2_CACHE
 201 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 202 #define CONFIG_BTB                      /* toggle branch predition */
 203 #define CONFIG_DDR_ECC
 204 #ifdef CONFIG_DDR_ECC
 205 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 206 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 207 #endif
 208
 209 #define CONFIG_ENABLE_36BIT_PHYS
 210
 211 #define CONFIG_ADDR_MAP
 212 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 213
 214 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 215 #define CONFIG_SYS_MEMTEST_END          0x00400000
 216 #define CONFIG_SYS_ALT_MEMTEST
 217 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 218
 219 /*
 220  *  Config the L3 Cache as L3 SRAM
 221  */
 222 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 223 /*
 224  * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
 225  * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
 226  * (CONFIG_SYS_INIT_L3_VADDR) will be different.
 227  */
 228 #define CONFIG_SYS_INIT_L3_VADDR        0xFFFC0000
 229 #define CONFIG_SYS_L3_SIZE              256 << 10
 230 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
 231 #ifdef CONFIG_RAMBOOT_PBL
 232 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 233 #endif
 234 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 235 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 236 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 237 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 238
 239 #define CONFIG_SYS_DCSRBAR              0xf0000000
 240 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 241
 242 /*
 243  * DDR Setup
 244  */
 245 #define CONFIG_VERY_BIG_RAM
 246 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 247 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 248
 249 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
 250 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 251 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 252
 253 #define CONFIG_DDR_SPD
 254 #ifndef CONFIG_SYS_FSL_DDR4
 255 #define CONFIG_SYS_FSL_DDR3
 256 #endif
 257
 258 #define CONFIG_SYS_SPD_BUS_NUM  0
 259 #define SPD_EEPROM_ADDRESS      0x51
 260
 261 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 262
 263 /*
 264  * IFC Definitions
 265  */
 266 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 267 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 268
 269 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
 270 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
 271                                 CSPR_PORT_SIZE_16 | \
 272                                 CSPR_MSEL_NOR | \
 273                                 CSPR_V)
 274 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 275
 276 /*
 277  * TDM Definition
 278  */
 279 #define T1040_TDM_QUIRK_CCSR_BASE       0xfe000000
 280
 281 /* NOR Flash Timing Params */
 282 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 283 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 284                                 FTIM0_NOR_TEADC(0x5) | \
 285                                 FTIM0_NOR_TEAHC(0x5))
 286 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 287                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 288                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 289 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 290                                 FTIM2_NOR_TCH(0x4) | \
 291                                 FTIM2_NOR_TWPH(0x0E) | \
 292                                 FTIM2_NOR_TWP(0x1c))
 293 #define CONFIG_SYS_NOR_FTIM3    0x0
 294
 295 #define CONFIG_SYS_FLASH_QUIET_TEST
 296 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 297
 298 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 299 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 300 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 301 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 302
 303 #define CONFIG_SYS_FLASH_EMPTY_INFO
 304 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 305
 306 /* CPLD on IFC */
 307 #define CPLD_LBMAP_MASK                 0x3F
 308 #define CPLD_BANK_SEL_MASK              0x07
 309 #define CPLD_BANK_OVERRIDE              0x40
 310 #define CPLD_LBMAP_ALTBANK              0x44 /* BANK OR | BANK 4 */
 311 #define CPLD_LBMAP_DFLTBANK             0x40 /* BANK OR | BANK0 */
 312 #define CPLD_LBMAP_RESET                0xFF
 313 #define CPLD_LBMAP_SHIFT                0x03
 314
 315 #if defined(CONFIG_T1042RDB_PI)
 316 #define CPLD_DIU_SEL_DFP                0x80
 317 #elif defined(CONFIG_T1042D4RDB)
 318 #define CPLD_DIU_SEL_DFP                0xc0
 319 #endif
 320
 321 #if defined(CONFIG_T1040D4RDB)
 322 #define CPLD_INT_MASK_ALL               0xFF
 323 #define CPLD_INT_MASK_THERM             0x80
 324 #define CPLD_INT_MASK_DVI_DFP           0x40
 325 #define CPLD_INT_MASK_QSGMII1           0x20
 326 #define CPLD_INT_MASK_QSGMII2           0x10
 327 #define CPLD_INT_MASK_SGMI1             0x08
 328 #define CPLD_INT_MASK_SGMI2             0x04
 329 #define CPLD_INT_MASK_TDMR1             0x02
 330 #define CPLD_INT_MASK_TDMR2             0x01
 331 #endif
 332
 333 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 334 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 335 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 336 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 337                                 | CSPR_PORT_SIZE_8 \
 338                                 | CSPR_MSEL_GPCM \
 339                                 | CSPR_V)
 340 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 341 #define CONFIG_SYS_CSOR2        0x0
 342 /* CPLD Timing parameters for IFC CS2 */
 343 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 344                                         FTIM0_GPCM_TEADC(0x0e) | \
 345                                         FTIM0_GPCM_TEAHC(0x0e))
 346 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 347                                         FTIM1_GPCM_TRAD(0x1f))
 348 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 349                                         FTIM2_GPCM_TCH(0x8) | \
 350                                         FTIM2_GPCM_TWP(0x1f))
 351 #define CONFIG_SYS_CS2_FTIM3            0x0
 352
 353 /* NAND Flash on IFC */
 354 #define CONFIG_NAND_FSL_IFC
 355 #define CONFIG_SYS_NAND_BASE            0xff800000
 356 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 357
 358 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 359 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 360                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 361                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 362                                 | CSPR_V)
 363 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 364
 365 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 366                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 367                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 368                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 369                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 370                                 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
 371                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 372
 373 #define CONFIG_SYS_NAND_ONFI_DETECTION
 374
 375 /* ONFI NAND Flash mode0 Timing Params */
 376 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 377                                         FTIM0_NAND_TWP(0x18)   | \
 378                                         FTIM0_NAND_TWCHT(0x07) | \
 379                                         FTIM0_NAND_TWH(0x0a))
 380 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 381                                         FTIM1_NAND_TWBE(0x39)  | \
 382                                         FTIM1_NAND_TRR(0x0e)   | \
 383                                         FTIM1_NAND_TRP(0x18))
 384 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 385                                         FTIM2_NAND_TREH(0x0a) | \
 386                                         FTIM2_NAND_TWHRE(0x1e))
 387 #define CONFIG_SYS_NAND_FTIM3           0x0
 388
 389 #define CONFIG_SYS_NAND_DDR_LAW         11
 390 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 391 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 392 #define CONFIG_CMD_NAND
 393
 394 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 395
 396 #if defined(CONFIG_NAND)
 397 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 398 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 399 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 400 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 401 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 402 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 403 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 404 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 405 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR_CSPR_EXT
 406 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 407 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 408 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 409 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 410 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 411 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 412 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 413 #else
 414 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 415 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 416 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 417 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 418 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 419 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 420 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 421 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 422 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 423 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 424 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 425 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 426 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 427 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 428 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 429 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 430 #endif
 431
 432 #ifdef CONFIG_SPL_BUILD
 433 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 434 #else
 435 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 436 #endif
 437
 438 #if defined(CONFIG_RAMBOOT_PBL)
 439 #define CONFIG_SYS_RAMBOOT
 440 #endif
 441
 442 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044
 443 #if defined(CONFIG_NAND)
 444 #define CONFIG_A008044_WORKAROUND
 445 #endif
 446 #endif
 447
 448 #define CONFIG_BOARD_EARLY_INIT_R
 449 #define CONFIG_MISC_INIT_R
 450
 451 #define CONFIG_HWCONFIG
 452
 453 /* define to use L1 as initial stack */
 454 #define CONFIG_L1_INIT_RAM
 455 #define CONFIG_SYS_INIT_RAM_LOCK
 456 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 457 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 458 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 459 /* The assembler doesn't like typecast */
 460 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 461         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 462           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 463 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 464
 465 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 466                                         GENERATED_GBL_DATA_SIZE)
 467 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 468
 469 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 470 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 471
 472 /* Serial Port - controlled on board with jumper J8
 473  * open - index 2
 474  * shorted - index 1
 475  */
 476 #define CONFIG_CONS_INDEX       1
 477 #define CONFIG_SYS_NS16550_SERIAL
 478 #define CONFIG_SYS_NS16550_REG_SIZE     1
 479 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 480
 481 #define CONFIG_SYS_BAUDRATE_TABLE       \
 482         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 483
 484 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 485 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 486 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 487 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 488 #ifndef CONFIG_SPL_BUILD
 489 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
 490 #endif
 491
 492 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T1042D4RDB)
 493 /* Video */
 494 #define CONFIG_FSL_DIU_FB
 495
 496 #ifdef CONFIG_FSL_DIU_FB
 497 #define CONFIG_FSL_DIU_CH7301
 498 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 499 #define CONFIG_VIDEO
 500 #define CONFIG_CMD_BMP
 501 #define CONFIG_CFB_CONSOLE
 502 #define CONFIG_CFB_CONSOLE_ANSI
 503 #define CONFIG_VIDEO_SW_CURSOR
 504 #define CONFIG_VGA_AS_SINGLE_DEVICE
 505 #define CONFIG_VIDEO_LOGO
 506 #define CONFIG_VIDEO_BMP_LOGO
 507 #endif
 508 #endif
 509
 510 /* I2C */
 511 #define CONFIG_SYS_I2C
 512 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 513 #define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C speed in Hz */
 514 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 515 #define CONFIG_SYS_FSL_I2C3_SPEED       400000
 516 #define CONFIG_SYS_FSL_I2C4_SPEED       400000
 517 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 518 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 519 #define CONFIG_SYS_FSL_I2C3_SLAVE       0x7F
 520 #define CONFIG_SYS_FSL_I2C4_SLAVE       0x7F
 521 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 522 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 523 #define CONFIG_SYS_FSL_I2C3_OFFSET      0x119000
 524 #define CONFIG_SYS_FSL_I2C4_OFFSET      0x119100
 525
 526 /* I2C bus multiplexer */
 527 #define I2C_MUX_PCA_ADDR                0x70
 528 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
 529 #define I2C_MUX_CH_DEFAULT      0x8
 530 #endif
 531
 532 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB)
 533 /* LDI/DVI Encoder for display */
 534 #define CONFIG_SYS_I2C_LDI_ADDR         0x38
 535 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 536
 537 /*
 538  * RTC configuration
 539  */
 540 #define RTC
 541 #define CONFIG_RTC_DS1337               1
 542 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 543
 544 /*DVI encoder*/
 545 #define CONFIG_HDMI_ENCODER_I2C_ADDR  0x75
 546 #endif
 547
 548 /*
 549  * eSPI - Enhanced SPI
 550  */
 551 #define CONFIG_SPI_FLASH_BAR
 552 #define CONFIG_SF_DEFAULT_SPEED         10000000
 553 #define CONFIG_SF_DEFAULT_MODE          0
 554 #define CONFIG_ENV_SPI_BUS              0
 555 #define CONFIG_ENV_SPI_CS               0
 556 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 557 #define CONFIG_ENV_SPI_MODE             0
 558
 559 /*
 560  * General PCI
 561  * Memory space is mapped 1-1, but I/O space must start from 0.
 562  */
 563
 564 #ifdef CONFIG_PCI
 565 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 566 #ifdef CONFIG_PCIE1
 567 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 568 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 569 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 570 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 571 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 572 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 573 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 574 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 575 #endif
 576
 577 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 578 #ifdef CONFIG_PCIE2
 579 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 580 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 581 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 582 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 583 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 584 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 585 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 586 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 587 #endif
 588
 589 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 590 #ifdef CONFIG_PCIE3
 591 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 592 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 593 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 594 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 595 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 596 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 597 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 598 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 599 #endif
 600
 601 /* controller 4, Base address 203000 */
 602 #ifdef CONFIG_PCIE4
 603 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
 604 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 605 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
 606 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 607 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
 608 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 609 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 610 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 611 #endif
 612
 613 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 614
 615 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 616 #define CONFIG_DOS_PARTITION
 617 #endif  /* CONFIG_PCI */
 618
 619 /* SATA */
 620 #define CONFIG_FSL_SATA_V2
 621 #ifdef CONFIG_FSL_SATA_V2
 622 #define CONFIG_LIBATA
 623 #define CONFIG_FSL_SATA
 624
 625 #define CONFIG_SYS_SATA_MAX_DEVICE      1
 626 #define CONFIG_SATA1
 627 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 628 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 629
 630 #define CONFIG_LBA48
 631 #define CONFIG_CMD_SATA
 632 #define CONFIG_DOS_PARTITION
 633 #endif
 634
 635 /*
 636 * USB
 637 */
 638 #define CONFIG_HAS_FSL_DR_USB
 639
 640 #ifdef CONFIG_HAS_FSL_DR_USB
 641 #define CONFIG_USB_EHCI
 642
 643 #ifdef CONFIG_USB_EHCI
 644 #define CONFIG_USB_EHCI_FSL
 645 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 646 #endif
 647 #endif
 648
 649 #define CONFIG_MMC
 650
 651 #ifdef CONFIG_MMC
 652 #define CONFIG_FSL_ESDHC
 653 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 654 #define CONFIG_GENERIC_MMC
 655 #define CONFIG_DOS_PARTITION
 656 #endif
 657
 658 /* Qman/Bman */
 659 #ifndef CONFIG_NOBQFMAN
 660 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 661 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 662 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 663 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 664 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 665 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 666 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 667 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 668 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 669 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 670                                         CONFIG_SYS_BMAN_CENA_SIZE)
 671 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 672 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 673 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 674 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 675 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 676 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 677 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 678 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 679 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 680 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 681 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 682                                         CONFIG_SYS_QMAN_CENA_SIZE)
 683 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 684 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 685
 686 #define CONFIG_SYS_DPAA_FMAN
 687 #define CONFIG_SYS_DPAA_PME
 688
 689 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
 690 #define CONFIG_QE
 691 #define CONFIG_U_QE
 692 #endif
 693
 694 /* Default address of microcode for the Linux Fman driver */
 695 #if defined(CONFIG_SPIFLASH)
 696 /*
 697  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 698  * env, so we got 0x110000.
 699  */
 700 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 701 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 702 #elif defined(CONFIG_SDCARD)
 703 /*
 704  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 705  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 706  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 707  */
 708 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 709 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 710 #elif defined(CONFIG_NAND)
 711 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 712 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
 713 #else
 714 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 715 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 716 #endif
 717
 718 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
 719 #if defined(CONFIG_SPIFLASH)
 720 #define CONFIG_SYS_QE_FW_ADDR           0x130000
 721 #elif defined(CONFIG_SDCARD)
 722 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 723 #elif defined(CONFIG_NAND)
 724 #define CONFIG_SYS_QE_FW_ADDR           (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 725 #else
 726 #define CONFIG_SYS_QE_FW_ADDR           0xEFF10000
 727 #endif
 728 #endif
 729
 730 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 731 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 732 #endif /* CONFIG_NOBQFMAN */
 733
 734 #ifdef CONFIG_SYS_DPAA_FMAN
 735 #define CONFIG_FMAN_ENET
 736 #define CONFIG_PHY_VITESSE
 737 #define CONFIG_PHY_REALTEK
 738 #endif
 739
 740 #ifdef CONFIG_FMAN_ENET
 741 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
 742 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x03
 743 #elif defined(CONFIG_T1040D4RDB)
 744 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x01
 745 #elif defined(CONFIG_T1042D4RDB)
 746 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x02
 747 #define CONFIG_SYS_SGMII2_PHY_ADDR             0x03
 748 #define CONFIG_SYS_SGMII3_PHY_ADDR             0x01
 749 #endif
 750
 751 #ifdef CONFIG_T104XD4RDB
 752 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x04
 753 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x05
 754 #else
 755 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x01
 756 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x02
 757 #endif
 758
 759 /* Enable VSC9953 L2 Switch driver on T1040 SoC */
 760 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB)
 761 #define CONFIG_VSC9953
 762 #define CONFIG_CMD_ETHSW
 763 #ifdef CONFIG_T1040RDB
 764 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x04
 765 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x08
 766 #else
 767 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x08
 768 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x0c
 769 #endif
 770 #endif
 771
 772 #define CONFIG_MII              /* MII PHY management */
 773 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 774 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 775 #endif
 776
 777 /*
 778  * Environment
 779  */
 780 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 781 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 782
 783 /*
 784  * Command line configuration.
 785  */
 786 #ifdef CONFIG_T1042RDB_PI
 787 #define CONFIG_CMD_DATE
 788 #endif
 789 #define CONFIG_CMD_ERRATA
 790 #define CONFIG_CMD_IRQ
 791 #define CONFIG_CMD_REGINFO
 792
 793 #ifdef CONFIG_PCI
 794 #define CONFIG_CMD_PCI
 795 #endif
 796
 797 /* Hash command with SHA acceleration supported in hardware */
 798 #ifdef CONFIG_FSL_CAAM
 799 #define CONFIG_CMD_HASH
 800 #define CONFIG_SHA_HW_ACCEL
 801 #endif
 802
 803 /*
 804  * Miscellaneous configurable options
 805  */
 806 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 807 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 808 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 809 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 810 #ifdef CONFIG_CMD_KGDB
 811 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 812 #else
 813 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 814 #endif
 815 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 816 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 817 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 818
 819 /*
 820  * For booting Linux, the board info and command line data
 821  * have to be in the first 64 MB of memory, since this is
 822  * the maximum mapped by the Linux kernel during initialization.
 823  */
 824 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 825 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 826
 827 #ifdef CONFIG_CMD_KGDB
 828 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 829 #endif
 830
 831 /*
 832  * Dynamic MTD Partition support with mtdparts
 833  */
 834 #ifndef CONFIG_SYS_NO_FLASH
 835 #define CONFIG_MTD_DEVICE
 836 #define CONFIG_MTD_PARTITIONS
 837 #define CONFIG_CMD_MTDPARTS
 838 #define CONFIG_FLASH_CFI_MTD
 839 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
 840                         "spi0=spife110000.0"
 841 #define MTDPARTS_DEFAULT        "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
 842                                 "128k(dtb),96m(fs),-(user);"\
 843                                 "fff800000.flash:2m(uboot),9m(kernel),"\
 844                                 "128k(dtb),96m(fs),-(user);spife110000.0:" \
 845                                 "2m(uboot),9m(kernel),128k(dtb),-(user)"
 846 #endif
 847
 848 /*
 849  * Environment Configuration
 850  */
 851 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 852 #define CONFIG_BOOTFILE         "uImage"
 853 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 854
 855 /* default location for tftp and bootm */
 856 #define CONFIG_LOADADDR         1000000
 857
 858
 859 #define CONFIG_BAUDRATE 115200
 860
 861 #define __USB_PHY_TYPE  utmi
 862 #define RAMDISKFILE     "t104xrdb/ramdisk.uboot"
 863
 864 #ifdef CONFIG_T1040RDB
 865 #define FDTFILE         "t1040rdb/t1040rdb.dtb"
 866 #elif defined(CONFIG_T1042RDB_PI)
 867 #define FDTFILE         "t1042rdb_pi/t1042rdb_pi.dtb"
 868 #elif defined(CONFIG_T1042RDB)
 869 #define FDTFILE         "t1042rdb/t1042rdb.dtb"
 870 #elif defined(CONFIG_T1040D4RDB)
 871 #define FDTFILE         "t1042rdb/t1040d4rdb.dtb"
 872 #elif defined(CONFIG_T1042D4RDB)
 873 #define FDTFILE         "t1042rdb/t1042d4rdb.dtb"
 874 #endif
 875
 876 #ifdef CONFIG_FSL_DIU_FB
 877 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
 878 #else
 879 #define DIU_ENVIRONMENT
 880 #endif
 881
 882 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 883         "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;"                  \
 884         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 885         "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 886         "netdev=eth0\0"                                         \
 887         "video-mode=" __stringify(DIU_ENVIRONMENT) "\0"         \
 888         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 889         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 890         "tftpflash=tftpboot $loadaddr $uboot && "               \
 891         "protect off $ubootaddr +$filesize && "                 \
 892         "erase $ubootaddr +$filesize && "                       \
 893         "cp.b $loadaddr $ubootaddr $filesize && "               \
 894         "protect on $ubootaddr +$filesize && "                  \
 895         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 896         "consoledev=ttyS0\0"                                    \
 897         "ramdiskaddr=2000000\0"                                 \
 898         "ramdiskfile=" __stringify(RAMDISKFILE) "\0"            \
 899         "fdtaddr=1e00000\0"                                     \
 900         "fdtfile=" __stringify(FDTFILE) "\0"                    \
 901         "bdev=sda3\0"
 902
 903 #define CONFIG_LINUX                       \
 904         "setenv bootargs root=/dev/ram rw "            \
 905         "console=$consoledev,$baudrate $othbootargs;"  \
 906         "setenv ramdiskaddr 0x02000000;"               \
 907         "setenv fdtaddr 0x00c00000;"                   \
 908         "setenv loadaddr 0x1000000;"                   \
 909         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 910
 911 #define CONFIG_HDBOOT                                   \
 912         "setenv bootargs root=/dev/$bdev rw "           \
 913         "console=$consoledev,$baudrate $othbootargs;"   \
 914         "tftp $loadaddr $bootfile;"                     \
 915         "tftp $fdtaddr $fdtfile;"                       \
 916         "bootm $loadaddr - $fdtaddr"
 917
 918 #define CONFIG_NFSBOOTCOMMAND                   \
 919         "setenv bootargs root=/dev/nfs rw "     \
 920         "nfsroot=$serverip:$rootpath "          \
 921         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 922         "console=$consoledev,$baudrate $othbootargs;"   \
 923         "tftp $loadaddr $bootfile;"             \
 924         "tftp $fdtaddr $fdtfile;"               \
 925         "bootm $loadaddr - $fdtaddr"
 926
 927 #define CONFIG_RAMBOOTCOMMAND                           \
 928         "setenv bootargs root=/dev/ram rw "             \
 929         "console=$consoledev,$baudrate $othbootargs;"   \
 930         "tftp $ramdiskaddr $ramdiskfile;"               \
 931         "tftp $loadaddr $bootfile;"                     \
 932         "tftp $fdtaddr $fdtfile;"                       \
 933         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 934
 935 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 936
 937 #include <asm/fsl_secure_boot.h>
 938
 939 #endif  /* __CONFIG_H */