include/configs/T104xRDB.h

   1 /*
   2 + * Copyright 2014 Freescale Semiconductor, Inc.
   3 + *
   4 + * SPDX-License-Identifier:     GPL-2.0+
   5 + */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 /*
  11  * T104x RDB board configuration file
  12  */
  13 #define CONFIG_T104xRDB
  14 #define CONFIG_PHYS_64BIT
  15
  16 #ifdef CONFIG_RAMBOOT_PBL
  17 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
  18 #ifdef CONFIG_T1040RDB
  19 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg
  20 #endif
  21 #ifdef CONFIG_T1042RDB_PI
  22 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg
  23 #endif
  24
  25 #define CONFIG_SPL
  26 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  27 #define CONFIG_SPL_ENV_SUPPORT
  28 #define CONFIG_SPL_SERIAL_SUPPORT
  29 #define CONFIG_SPL_FLUSH_IMAGE
  30 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  31 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  32 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  33 #define CONFIG_SPL_I2C_SUPPORT
  34 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
  35 #define CONFIG_FSL_LAW                 /* Use common FSL init code */
  36 #define CONFIG_SYS_TEXT_BASE            0x00201000
  37 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  38 #define CONFIG_SPL_PAD_TO               0x40000
  39 #define CONFIG_SPL_MAX_SIZE             0x28000
  40 #ifdef CONFIG_SPL_BUILD
  41 #define CONFIG_SPL_SKIP_RELOCATE
  42 #define CONFIG_SPL_COMMON_INIT_DDR
  43 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  44 #define CONFIG_SYS_NO_FLASH
  45 #endif
  46 #define RESET_VECTOR_OFFSET             0x27FFC
  47 #define BOOT_PAGE_OFFSET                0x27000
  48
  49 #ifdef CONFIG_NAND
  50 #define CONFIG_SPL_NAND_SUPPORT
  51 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  52 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  53 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  54 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  55 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  56 #define CONFIG_SPL_NAND_BOOT
  57 #endif
  58
  59 #ifdef CONFIG_SPIFLASH
  60 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  61 #define CONFIG_SPL_SPI_SUPPORT
  62 #define CONFIG_SPL_SPI_FLASH_SUPPORT
  63 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
  66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
  67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  68 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  69 #ifndef CONFIG_SPL_BUILD
  70 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  71 #endif
  72 #define CONFIG_SPL_SPI_BOOT
  73 #endif
  74
  75 #ifdef CONFIG_SDCARD
  76 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  77 #define CONFIG_SPL_MMC_SUPPORT
  78 #define CONFIG_SPL_MMC_MINIMAL
  79 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  80 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
  81 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
  82 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  83 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  84 #ifndef CONFIG_SPL_BUILD
  85 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  86 #endif
  87 #define CONFIG_SPL_MMC_BOOT
  88 #endif
  89
  90 #endif
  91
  92 /* High Level Configuration Options */
  93 #define CONFIG_BOOKE
  94 #define CONFIG_E500                     /* BOOKE e500 family */
  95 #define CONFIG_E500MC                   /* BOOKE e500mc family */
  96 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  97 #define CONFIG_MP                       /* support multiple processors */
  98
  99 /* support deep sleep */
 100 #define CONFIG_DEEP_SLEEP
 101 #define CONFIG_SILENT_CONSOLE
 102
 103 #ifndef CONFIG_SYS_TEXT_BASE
 104 #define CONFIG_SYS_TEXT_BASE    0xeff40000
 105 #endif
 106
 107 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 108 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 109 #endif
 110
 111 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
 112 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
 113 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
 114 #define CONFIG_PCI                      /* Enable PCI/PCIE */
 115 #define CONFIG_PCI_INDIRECT_BRIDGE
 116 #define CONFIG_PCIE1                    /* PCIE controler 1 */
 117 #define CONFIG_PCIE2                    /* PCIE controler 2 */
 118 #define CONFIG_PCIE3                    /* PCIE controler 3 */
 119 #define CONFIG_PCIE4                    /* PCIE controler 4 */
 120
 121 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
 122 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
 123
 124 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
 125
 126 #define CONFIG_ENV_OVERWRITE
 127
 128 #ifndef CONFIG_SYS_NO_FLASH
 129 #define CONFIG_FLASH_CFI_DRIVER
 130 #define CONFIG_SYS_FLASH_CFI
 131 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 132 #endif
 133
 134 #if defined(CONFIG_SPIFLASH)
 135 #define CONFIG_SYS_EXTRA_ENV_RELOC
 136 #define CONFIG_ENV_IS_IN_SPI_FLASH
 137 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 138 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 139 #define CONFIG_ENV_SECT_SIZE            0x10000
 140 #elif defined(CONFIG_SDCARD)
 141 #define CONFIG_SYS_EXTRA_ENV_RELOC
 142 #define CONFIG_ENV_IS_IN_MMC
 143 #define CONFIG_SYS_MMC_ENV_DEV          0
 144 #define CONFIG_ENV_SIZE                 0x2000
 145 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 146 #elif defined(CONFIG_NAND)
 147 #define CONFIG_SYS_EXTRA_ENV_RELOC
 148 #define CONFIG_ENV_IS_IN_NAND
 149 #define CONFIG_ENV_SIZE                 0x2000
 150 #define CONFIG_ENV_OFFSET               (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 151 #else
 152 #define CONFIG_ENV_IS_IN_FLASH
 153 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 154 #define CONFIG_ENV_SIZE         0x2000
 155 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 156 #endif
 157
 158 #define CONFIG_SYS_CLK_FREQ     100000000
 159 #define CONFIG_DDR_CLK_FREQ     66666666
 160
 161 /*
 162  * These can be toggled for performance analysis, otherwise use default.
 163  */
 164 #define CONFIG_SYS_CACHE_STASHING
 165 #define CONFIG_BACKSIDE_L2_CACHE
 166 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 167 #define CONFIG_BTB                      /* toggle branch predition */
 168 #define CONFIG_DDR_ECC
 169 #ifdef CONFIG_DDR_ECC
 170 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 171 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 172 #endif
 173
 174 #define CONFIG_ENABLE_36BIT_PHYS
 175
 176 #define CONFIG_ADDR_MAP
 177 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 178
 179 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 180 #define CONFIG_SYS_MEMTEST_END          0x00400000
 181 #define CONFIG_SYS_ALT_MEMTEST
 182 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 183
 184 /*
 185  *  Config the L3 Cache as L3 SRAM
 186  */
 187 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 188 #define CONFIG_SYS_L3_SIZE              256 << 10
 189 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 190 #ifdef CONFIG_RAMBOOT_PBL
 191 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 192 #endif
 193 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 194 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 195 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 196 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 197
 198 #define CONFIG_SYS_DCSRBAR              0xf0000000
 199 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 200
 201 /*
 202  * DDR Setup
 203  */
 204 #define CONFIG_VERY_BIG_RAM
 205 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 206 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 207
 208 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
 209 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 210 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 211
 212 #define CONFIG_DDR_SPD
 213 #define CONFIG_SYS_DDR_RAW_TIMING
 214 #define CONFIG_SYS_FSL_DDR3
 215
 216 #define CONFIG_SYS_SPD_BUS_NUM  0
 217 #define SPD_EEPROM_ADDRESS      0x51
 218
 219 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 220
 221 /*
 222  * IFC Definitions
 223  */
 224 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 225 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 226
 227 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
 228 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
 229                                 CSPR_PORT_SIZE_16 | \
 230                                 CSPR_MSEL_NOR | \
 231                                 CSPR_V)
 232 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 233 /* NOR Flash Timing Params */
 234 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 235 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 236                                 FTIM0_NOR_TEADC(0x5) | \
 237                                 FTIM0_NOR_TEAHC(0x5))
 238 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 239                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 240                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 241 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 242                                 FTIM2_NOR_TCH(0x4) | \
 243                                 FTIM2_NOR_TWPH(0x0E) | \
 244                                 FTIM2_NOR_TWP(0x1c))
 245 #define CONFIG_SYS_NOR_FTIM3    0x0
 246
 247 #define CONFIG_SYS_FLASH_QUIET_TEST
 248 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 249
 250 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 251 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 252 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 253 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 254
 255 #define CONFIG_SYS_FLASH_EMPTY_INFO
 256 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 257
 258 /* CPLD on IFC */
 259 #define CPLD_LBMAP_MASK                 0x3F
 260 #define CPLD_BANK_SEL_MASK              0x07
 261 #define CPLD_BANK_OVERRIDE              0x40
 262 #define CPLD_LBMAP_ALTBANK              0x44 /* BANK OR | BANK 4 */
 263 #define CPLD_LBMAP_DFLTBANK             0x40 /* BANK OR | BANK0 */
 264 #define CPLD_LBMAP_RESET                0xFF
 265 #define CPLD_LBMAP_SHIFT                0x03
 266
 267 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 268 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 269 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 270 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 271                                 | CSPR_PORT_SIZE_8 \
 272                                 | CSPR_MSEL_GPCM \
 273                                 | CSPR_V)
 274 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 275 #define CONFIG_SYS_CSOR2        0x0
 276 /* CPLD Timing parameters for IFC CS2 */
 277 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 278                                         FTIM0_GPCM_TEADC(0x0e) | \
 279                                         FTIM0_GPCM_TEAHC(0x0e))
 280 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 281                                         FTIM1_GPCM_TRAD(0x1f))
 282 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 283                                         FTIM2_GPCM_TCH(0x0) | \
 284                                         FTIM2_GPCM_TWP(0x1f))
 285 #define CONFIG_SYS_CS2_FTIM3            0x0
 286
 287 /* NAND Flash on IFC */
 288 #define CONFIG_NAND_FSL_IFC
 289 #define CONFIG_SYS_NAND_BASE            0xff800000
 290 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 291
 292 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 293 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 294                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 295                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 296                                 | CSPR_V)
 297 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 298
 299 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 300                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 301                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 302                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 303                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 304                                 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
 305                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 306
 307 #define CONFIG_SYS_NAND_ONFI_DETECTION
 308
 309 /* ONFI NAND Flash mode0 Timing Params */
 310 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 311                                         FTIM0_NAND_TWP(0x18)   | \
 312                                         FTIM0_NAND_TWCHT(0x07) | \
 313                                         FTIM0_NAND_TWH(0x0a))
 314 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 315                                         FTIM1_NAND_TWBE(0x39)  | \
 316                                         FTIM1_NAND_TRR(0x0e)   | \
 317                                         FTIM1_NAND_TRP(0x18))
 318 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 319                                         FTIM2_NAND_TREH(0x0a) | \
 320                                         FTIM2_NAND_TWHRE(0x1e))
 321 #define CONFIG_SYS_NAND_FTIM3           0x0
 322
 323 #define CONFIG_SYS_NAND_DDR_LAW         11
 324 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 325 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 326 #define CONFIG_MTD_NAND_VERIFY_WRITE
 327 #define CONFIG_CMD_NAND
 328
 329 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 330
 331 #if defined(CONFIG_NAND)
 332 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 333 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 334 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 335 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 336 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 337 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 338 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 339 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 340 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR_CSPR_EXT
 341 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 342 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 343 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 344 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 345 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 346 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 347 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 348 #else
 349 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 350 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 351 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 352 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 353 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 354 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 355 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 356 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 357 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 358 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 359 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 360 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 361 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 362 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 363 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 364 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 365 #endif
 366
 367 #ifdef CONFIG_SPL_BUILD
 368 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 369 #else
 370 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 371 #endif
 372
 373 #if defined(CONFIG_RAMBOOT_PBL)
 374 #define CONFIG_SYS_RAMBOOT
 375 #endif
 376
 377 #define CONFIG_BOARD_EARLY_INIT_R
 378 #define CONFIG_MISC_INIT_R
 379
 380 #define CONFIG_HWCONFIG
 381
 382 /* define to use L1 as initial stack */
 383 #define CONFIG_L1_INIT_RAM
 384 #define CONFIG_SYS_INIT_RAM_LOCK
 385 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 386 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 387 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe0ec000
 388 /* The assembler doesn't like typecast */
 389 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 390         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 391           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 392 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 393
 394 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 395                                         GENERATED_GBL_DATA_SIZE)
 396 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 397
 398 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 399 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 400
 401 /* Serial Port - controlled on board with jumper J8
 402  * open - index 2
 403  * shorted - index 1
 404  */
 405 #define CONFIG_CONS_INDEX       1
 406 #define CONFIG_SYS_NS16550
 407 #define CONFIG_SYS_NS16550_SERIAL
 408 #define CONFIG_SYS_NS16550_REG_SIZE     1
 409 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 410
 411 #define CONFIG_SYS_BAUDRATE_TABLE       \
 412         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 413
 414 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 415 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 416 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 417 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 418 #define CONFIG_SERIAL_MULTI             /* Enable both serial ports */
 419 #ifndef CONFIG_SPL_BUILD
 420 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
 421 #endif
 422
 423 /* Use the HUSH parser */
 424 #define CONFIG_SYS_HUSH_PARSER
 425 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 426
 427 /* pass open firmware flat tree */
 428 #define CONFIG_OF_LIBFDT
 429 #define CONFIG_OF_BOARD_SETUP
 430 #define CONFIG_OF_STDOUT_VIA_ALIAS
 431
 432 /* new uImage format support */
 433 #define CONFIG_FIT
 434 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
 435
 436 /* I2C */
 437 #define CONFIG_SYS_I2C
 438 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 439 #define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C speed in Hz */
 440 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 441 #define CONFIG_SYS_FSL_I2C2_SPEED       400000  /* I2C speed in Hz */
 442 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 443 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 444 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x119000
 445
 446 /* I2C bus multiplexer */
 447 #define I2C_MUX_PCA_ADDR                0x70
 448 #ifdef CONFIG_T1040RDB
 449 #define I2C_MUX_CH_DEFAULT      0x8
 450 #endif
 451
 452 #ifdef CONFIG_T1042RDB_PI
 453 /*
 454  * RTC configuration
 455  */
 456 #define RTC
 457 #define CONFIG_RTC_DS1337               1
 458 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 459
 460 /*DVI encoder*/
 461 #define CONFIG_HDMI_ENCODER_I2C_ADDR  0x75
 462 #endif
 463
 464 /*
 465  * eSPI - Enhanced SPI
 466  */
 467 #define CONFIG_FSL_ESPI
 468 #define CONFIG_SPI_FLASH
 469 #define CONFIG_SPI_FLASH_STMICRO
 470 #define CONFIG_CMD_SF
 471 #define CONFIG_SF_DEFAULT_SPEED         10000000
 472 #define CONFIG_SF_DEFAULT_MODE          0
 473 #define CONFIG_ENV_SPI_BUS              0
 474 #define CONFIG_ENV_SPI_CS               0
 475 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 476 #define CONFIG_ENV_SPI_MODE             0
 477
 478 /*
 479  * General PCI
 480  * Memory space is mapped 1-1, but I/O space must start from 0.
 481  */
 482
 483 #ifdef CONFIG_PCI
 484 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 485 #ifdef CONFIG_PCIE1
 486 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 487 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 488 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 489 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 490 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 491 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 492 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 493 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 494 #endif
 495
 496 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 497 #ifdef CONFIG_PCIE2
 498 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 499 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 500 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 501 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 502 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 503 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 504 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 505 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 506 #endif
 507
 508 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 509 #ifdef CONFIG_PCIE3
 510 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 511 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 512 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 513 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 514 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 515 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 516 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 517 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 518 #endif
 519
 520 /* controller 4, Base address 203000 */
 521 #ifdef CONFIG_PCIE4
 522 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
 523 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 524 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
 525 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 526 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
 527 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 528 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 529 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 530 #endif
 531
 532 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 533 #define CONFIG_E1000
 534
 535 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 536 #define CONFIG_DOS_PARTITION
 537 #endif  /* CONFIG_PCI */
 538
 539 /* SATA */
 540 #define CONFIG_FSL_SATA_V2
 541 #ifdef CONFIG_FSL_SATA_V2
 542 #define CONFIG_LIBATA
 543 #define CONFIG_FSL_SATA
 544
 545 #define CONFIG_SYS_SATA_MAX_DEVICE      1
 546 #define CONFIG_SATA1
 547 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 548 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 549
 550 #define CONFIG_LBA48
 551 #define CONFIG_CMD_SATA
 552 #define CONFIG_DOS_PARTITION
 553 #define CONFIG_CMD_EXT2
 554 #endif
 555
 556 /*
 557 * USB
 558 */
 559 #define CONFIG_HAS_FSL_DR_USB
 560
 561 #ifdef CONFIG_HAS_FSL_DR_USB
 562 #define CONFIG_USB_EHCI
 563
 564 #ifdef CONFIG_USB_EHCI
 565 #define CONFIG_CMD_USB
 566 #define CONFIG_USB_STORAGE
 567 #define CONFIG_USB_EHCI_FSL
 568 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 569 #define CONFIG_CMD_EXT2
 570 #endif
 571 #endif
 572
 573 #define CONFIG_MMC
 574
 575 #ifdef CONFIG_MMC
 576 #define CONFIG_FSL_ESDHC
 577 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 578 #define CONFIG_CMD_MMC
 579 #define CONFIG_GENERIC_MMC
 580 #define CONFIG_CMD_EXT2
 581 #define CONFIG_CMD_FAT
 582 #define CONFIG_DOS_PARTITION
 583 #endif
 584
 585 /* Qman/Bman */
 586 #ifndef CONFIG_NOBQFMAN
 587 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 588 #define CONFIG_SYS_BMAN_NUM_PORTALS     25
 589 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 590 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 591 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 592 #define CONFIG_SYS_QMAN_NUM_PORTALS     25
 593 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 594 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 595 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 596
 597 #define CONFIG_SYS_DPAA_FMAN
 598 #define CONFIG_SYS_DPAA_PME
 599
 600 #ifdef CONFIG_T1040RDB
 601 #define CONFIG_QE
 602 #define CONFIG_U_QE
 603 #endif
 604
 605 /* Default address of microcode for the Linux Fman driver */
 606 #if defined(CONFIG_SPIFLASH)
 607 /*
 608  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 609  * env, so we got 0x110000.
 610  */
 611 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 612 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 613 #elif defined(CONFIG_SDCARD)
 614 /*
 615  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 616  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 617  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 618  */
 619 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 620 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 621 #elif defined(CONFIG_NAND)
 622 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 623 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
 624 #else
 625 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 626 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 627 #endif
 628
 629 #ifdef CONFIG_T1040RDB
 630 #if defined(CONFIG_SPIFLASH)
 631 #define CONFIG_SYS_QE_FW_ADDR           0x130000
 632 #elif defined(CONFIG_SDCARD)
 633 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 634 #elif defined(CONFIG_NAND)
 635 #define CONFIG_SYS_QE_FW_ADDR           (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 636 #else
 637 #define CONFIG_SYS_QE_FW_ADDR           0xEFF10000
 638 #endif
 639 #endif
 640
 641
 642 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 643 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 644 #endif /* CONFIG_NOBQFMAN */
 645
 646 #ifdef CONFIG_SYS_DPAA_FMAN
 647 #define CONFIG_FMAN_ENET
 648 #define CONFIG_PHY_VITESSE
 649 #define CONFIG_PHY_REALTEK
 650 #endif
 651
 652 #ifdef CONFIG_FMAN_ENET
 653 #ifdef CONFIG_T1040RDB
 654 #define CONFIG_SYS_SGMII1_PHY_ADDR              0x03
 655 #endif
 656 #define CONFIG_SYS_RGMII1_PHY_ADDR              0x01
 657 #define CONFIG_SYS_RGMII2_PHY_ADDR              0x02
 658
 659 #define CONFIG_MII              /* MII PHY management */
 660 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 661 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 662 #endif
 663
 664 /*
 665  * Environment
 666  */
 667 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 668 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 669
 670 /*
 671  * Command line configuration.
 672  */
 673 #include <config_cmd_default.h>
 674
 675 #ifdef CONFIG_T1042RDB_PI
 676 #define CONFIG_CMD_DATE
 677 #endif
 678 #define CONFIG_CMD_DHCP
 679 #define CONFIG_CMD_ELF
 680 #define CONFIG_CMD_ERRATA
 681 #define CONFIG_CMD_GREPENV
 682 #define CONFIG_CMD_IRQ
 683 #define CONFIG_CMD_I2C
 684 #define CONFIG_CMD_MII
 685 #define CONFIG_CMD_PING
 686 #define CONFIG_CMD_REGINFO
 687 #define CONFIG_CMD_SETEXPR
 688
 689 #ifdef CONFIG_PCI
 690 #define CONFIG_CMD_PCI
 691 #define CONFIG_CMD_NET
 692 #endif
 693
 694 /*
 695  * Miscellaneous configurable options
 696  */
 697 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 698 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 699 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 700 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 701 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 702 #ifdef CONFIG_CMD_KGDB
 703 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 704 #else
 705 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 706 #endif
 707 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 708 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 709 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 710
 711 /*
 712  * For booting Linux, the board info and command line data
 713  * have to be in the first 64 MB of memory, since this is
 714  * the maximum mapped by the Linux kernel during initialization.
 715  */
 716 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 717 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 718
 719 #ifdef CONFIG_CMD_KGDB
 720 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 721 #endif
 722
 723 /*
 724  * Dynamic MTD Partition support with mtdparts
 725  */
 726 #ifndef CONFIG_SYS_NO_FLASH
 727 #define CONFIG_MTD_DEVICE
 728 #define CONFIG_MTD_PARTITIONS
 729 #define CONFIG_CMD_MTDPARTS
 730 #define CONFIG_FLASH_CFI_MTD
 731 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
 732                         "spi0=spife110000.0"
 733 #define MTDPARTS_DEFAULT        "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
 734                                 "128k(dtb),96m(fs),-(user);"\
 735                                 "fff800000.flash:2m(uboot),9m(kernel),"\
 736                                 "128k(dtb),96m(fs),-(user);spife110000.0:" \
 737                                 "2m(uboot),9m(kernel),128k(dtb),-(user)"
 738 #endif
 739
 740 /*
 741  * Environment Configuration
 742  */
 743 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 744 #define CONFIG_BOOTFILE         "uImage"
 745 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 746
 747 /* default location for tftp and bootm */
 748 #define CONFIG_LOADADDR         1000000
 749
 750 #define CONFIG_BOOTDELAY        10      /*-1 disables auto-boot*/
 751
 752 #define CONFIG_BAUDRATE 115200
 753
 754 #define __USB_PHY_TYPE  utmi
 755
 756 #ifdef CONFIG_T1040RDB
 757 #define FDTFILE         "t1040rdb/t1040rdb.dtb"
 758 #define RAMDISKFILE     "t1040rdb/ramdisk.uboot"
 759 #elif CONFIG_T1042RDB_PI
 760 #define FDTFILE         "t1040rdb_pi/t1040rdb_pi.dtb"
 761 #define RAMDISKFILE     "t1040rdb_pi/ramdisk.uboot"
 762 #endif
 763
 764 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 765         "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;"                  \
 766         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 767         "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 768         "netdev=eth0\0"                                         \
 769         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 770         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 771         "tftpflash=tftpboot $loadaddr $uboot && "               \
 772         "protect off $ubootaddr +$filesize && "                 \
 773         "erase $ubootaddr +$filesize && "                       \
 774         "cp.b $loadaddr $ubootaddr $filesize && "               \
 775         "protect on $ubootaddr +$filesize && "                  \
 776         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 777         "consoledev=ttyS0\0"                                    \
 778         "ramdiskaddr=2000000\0"                                 \
 779         "ramdiskfile=" __stringify(RAMDISKFILE) "\0"            \
 780         "fdtaddr=c00000\0"                                      \
 781         "fdtfile=" __stringify(FDTFILE) "\0"                    \
 782         "bdev=sda3\0"
 783
 784 #define CONFIG_LINUX                       \
 785         "setenv bootargs root=/dev/ram rw "            \
 786         "console=$consoledev,$baudrate $othbootargs;"  \
 787         "setenv ramdiskaddr 0x02000000;"               \
 788         "setenv fdtaddr 0x00c00000;"                   \
 789         "setenv loadaddr 0x1000000;"                   \
 790         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 791
 792 #define CONFIG_HDBOOT                                   \
 793         "setenv bootargs root=/dev/$bdev rw "           \
 794         "console=$consoledev,$baudrate $othbootargs;"   \
 795         "tftp $loadaddr $bootfile;"                     \
 796         "tftp $fdtaddr $fdtfile;"                       \
 797         "bootm $loadaddr - $fdtaddr"
 798
 799 #define CONFIG_NFSBOOTCOMMAND                   \
 800         "setenv bootargs root=/dev/nfs rw "     \
 801         "nfsroot=$serverip:$rootpath "          \
 802         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 803         "console=$consoledev,$baudrate $othbootargs;"   \
 804         "tftp $loadaddr $bootfile;"             \
 805         "tftp $fdtaddr $fdtfile;"               \
 806         "bootm $loadaddr - $fdtaddr"
 807
 808 #define CONFIG_RAMBOOTCOMMAND                           \
 809         "setenv bootargs root=/dev/ram rw "             \
 810         "console=$consoledev,$baudrate $othbootargs;"   \
 811         "tftp $ramdiskaddr $ramdiskfile;"               \
 812         "tftp $loadaddr $bootfile;"                     \
 813         "tftp $fdtaddr $fdtfile;"                       \
 814         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 815
 816 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 817
 818 #ifdef CONFIG_SECURE_BOOT
 819 #include <asm/fsl_secure_boot.h>
 820 #endif
 821
 822 #endif  /* __CONFIG_H */