include/configs/T104xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #include <linux/stringify.h>
  11
  12 /*
  13  * T104x RDB board configuration file
  14  */
  15 #include <asm/config_mpc85xx.h>
  16
  17 #ifdef CONFIG_RAMBOOT_PBL
  18 #define CONFIG_SPL_FLUSH_IMAGE
  19 #define CONFIG_SPL_PAD_TO               0x40000
  20 #define CONFIG_SPL_MAX_SIZE             0x28000
  21 #ifdef CONFIG_SPL_BUILD
  22 #define CONFIG_SPL_SKIP_RELOCATE
  23 #define CONFIG_SPL_COMMON_INIT_DDR
  24 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  25 #endif
  26 #define RESET_VECTOR_OFFSET             0x27FFC
  27 #define BOOT_PAGE_OFFSET                0x27000
  28
  29 #ifdef CONFIG_MTD_RAW_NAND
  30 #ifdef CONFIG_NXP_ESBC
  31 #define CONFIG_U_BOOT_HDR_SIZE          (16 << 10)
  32 /*
  33  * HDR would be appended at end of image and copied to DDR along
  34  * with U-Boot image.
  35  */
  36 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) + \
  37                                          CONFIG_U_BOOT_HDR_SIZE)
  38 #else
  39 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  40 #endif
  41 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  42 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  43 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  44 #endif
  45
  46 #ifdef CONFIG_SPIFLASH
  47 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  48 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  49 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  50 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  51 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  52 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  53 #ifndef CONFIG_SPL_BUILD
  54 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  55 #endif
  56 #endif
  57
  58 #ifdef CONFIG_SDCARD
  59 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  60 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  61 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
  62 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
  63 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  64 #ifndef CONFIG_SPL_BUILD
  65 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  66 #endif
  67 #endif
  68
  69 #endif
  70
  71 /* High Level Configuration Options */
  72 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  73
  74 /* support deep sleep */
  75 #define CONFIG_DEEP_SLEEP
  76
  77 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  78 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  79 #endif
  80
  81 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  82 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  83 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  84 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  85 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  86 #define CONFIG_PCIE4                    /* PCIE controller 4 */
  87
  88 #if defined(CONFIG_SPIFLASH)
  89 #elif defined(CONFIG_MTD_RAW_NAND)
  90 #ifdef CONFIG_NXP_ESBC
  91 #define CONFIG_RAMBOOT_NAND
  92 #define CONFIG_BOOTSCRIPT_COPY_RAM
  93 #endif
  94 #endif
  95
  96 #define CONFIG_SYS_CLK_FREQ     100000000
  97
  98 /*
  99  * These can be toggled for performance analysis, otherwise use default.
 100  */
 101 #define CONFIG_SYS_CACHE_STASHING
 102 #define CONFIG_BACKSIDE_L2_CACHE
 103 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 104 #define CONFIG_BTB                      /* toggle branch predition */
 105 #ifdef CONFIG_DDR_ECC
 106 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 107 #endif
 108
 109 #define CONFIG_ENABLE_36BIT_PHYS
 110
 111 /*
 112  *  Config the L3 Cache as L3 SRAM
 113  */
 114 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 115 /*
 116  * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
 117  * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
 118  * (CONFIG_SYS_INIT_L3_VADDR) will be different.
 119  */
 120 #define CONFIG_SYS_INIT_L3_VADDR        0xFFFC0000
 121 #define CONFIG_SYS_L3_SIZE              256 << 10
 122 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
 123 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
 124 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 125 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 126 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 127
 128 #define CONFIG_SYS_DCSRBAR              0xf0000000
 129 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 130
 131 /*
 132  * DDR Setup
 133  */
 134 #define CONFIG_VERY_BIG_RAM
 135 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 136 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 137
 138 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 139 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 140
 141 #define CONFIG_SYS_SPD_BUS_NUM  0
 142 #define SPD_EEPROM_ADDRESS      0x51
 143
 144 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 145
 146 /*
 147  * IFC Definitions
 148  */
 149 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 150 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 151
 152 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
 153 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
 154                                 CSPR_PORT_SIZE_16 | \
 155                                 CSPR_MSEL_NOR | \
 156                                 CSPR_V)
 157 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 158
 159 /*
 160  * TDM Definition
 161  */
 162 #define T1040_TDM_QUIRK_CCSR_BASE       0xfe000000
 163
 164 /* NOR Flash Timing Params */
 165 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 166 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 167                                 FTIM0_NOR_TEADC(0x5) | \
 168                                 FTIM0_NOR_TEAHC(0x5))
 169 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 170                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 171                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 172 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 173                                 FTIM2_NOR_TCH(0x4) | \
 174                                 FTIM2_NOR_TWPH(0x0E) | \
 175                                 FTIM2_NOR_TWP(0x1c))
 176 #define CONFIG_SYS_NOR_FTIM3    0x0
 177
 178 #define CONFIG_SYS_FLASH_QUIET_TEST
 179 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 180
 181 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 182 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 183 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 184 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 185
 186 #define CONFIG_SYS_FLASH_EMPTY_INFO
 187 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 188
 189 /* CPLD on IFC */
 190 #define CPLD_LBMAP_MASK                 0x3F
 191 #define CPLD_BANK_SEL_MASK              0x07
 192 #define CPLD_BANK_OVERRIDE              0x40
 193 #define CPLD_LBMAP_ALTBANK              0x44 /* BANK OR | BANK 4 */
 194 #define CPLD_LBMAP_DFLTBANK             0x40 /* BANK OR | BANK0 */
 195 #define CPLD_LBMAP_RESET                0xFF
 196 #define CPLD_LBMAP_SHIFT                0x03
 197
 198 #if defined(CONFIG_TARGET_T1042RDB_PI)
 199 #define CPLD_DIU_SEL_DFP                0x80
 200 #elif defined(CONFIG_TARGET_T1042D4RDB)
 201 #define CPLD_DIU_SEL_DFP                0xc0
 202 #endif
 203
 204 #if defined(CONFIG_TARGET_T1040D4RDB)
 205 #define CPLD_INT_MASK_ALL               0xFF
 206 #define CPLD_INT_MASK_THERM             0x80
 207 #define CPLD_INT_MASK_DVI_DFP           0x40
 208 #define CPLD_INT_MASK_QSGMII1           0x20
 209 #define CPLD_INT_MASK_QSGMII2           0x10
 210 #define CPLD_INT_MASK_SGMI1             0x08
 211 #define CPLD_INT_MASK_SGMI2             0x04
 212 #define CPLD_INT_MASK_TDMR1             0x02
 213 #define CPLD_INT_MASK_TDMR2             0x01
 214 #endif
 215
 216 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 217 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 218 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 219 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 220                                 | CSPR_PORT_SIZE_8 \
 221                                 | CSPR_MSEL_GPCM \
 222                                 | CSPR_V)
 223 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 224 #define CONFIG_SYS_CSOR2        0x0
 225 /* CPLD Timing parameters for IFC CS2 */
 226 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 227                                         FTIM0_GPCM_TEADC(0x0e) | \
 228                                         FTIM0_GPCM_TEAHC(0x0e))
 229 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 230                                         FTIM1_GPCM_TRAD(0x1f))
 231 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 232                                         FTIM2_GPCM_TCH(0x8) | \
 233                                         FTIM2_GPCM_TWP(0x1f))
 234 #define CONFIG_SYS_CS2_FTIM3            0x0
 235
 236 /* NAND Flash on IFC */
 237 #define CONFIG_SYS_NAND_BASE            0xff800000
 238 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 239
 240 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 241 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 242                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 243                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 244                                 | CSPR_V)
 245 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 246
 247 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 248                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 249                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 250                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 251                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 252                                 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
 253                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 254
 255 /* ONFI NAND Flash mode0 Timing Params */
 256 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 257                                         FTIM0_NAND_TWP(0x18)   | \
 258                                         FTIM0_NAND_TWCHT(0x07) | \
 259                                         FTIM0_NAND_TWH(0x0a))
 260 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 261                                         FTIM1_NAND_TWBE(0x39)  | \
 262                                         FTIM1_NAND_TRR(0x0e)   | \
 263                                         FTIM1_NAND_TRP(0x18))
 264 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 265                                         FTIM2_NAND_TREH(0x0a) | \
 266                                         FTIM2_NAND_TWHRE(0x1e))
 267 #define CONFIG_SYS_NAND_FTIM3           0x0
 268
 269 #define CONFIG_SYS_NAND_DDR_LAW         11
 270 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 271 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 272
 273 #if defined(CONFIG_MTD_RAW_NAND)
 274 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 275 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 276 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 277 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 278 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 279 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 280 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 281 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 282 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR_CSPR_EXT
 283 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 284 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 285 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 286 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 287 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 288 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 289 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 290 #else
 291 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 292 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 293 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 294 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 295 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 296 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 297 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 298 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 299 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 300 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 301 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 302 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 303 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 304 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 305 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 306 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 307 #endif
 308
 309 #ifdef CONFIG_SPL_BUILD
 310 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 311 #else
 312 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 313 #endif
 314
 315 #if defined(CONFIG_RAMBOOT_PBL)
 316 #define CONFIG_SYS_RAMBOOT
 317 #endif
 318
 319 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044
 320 #if defined(CONFIG_MTD_RAW_NAND)
 321 #define CONFIG_A008044_WORKAROUND
 322 #endif
 323 #endif
 324
 325 #define CONFIG_HWCONFIG
 326
 327 /* define to use L1 as initial stack */
 328 #define CONFIG_L1_INIT_RAM
 329 #define CONFIG_SYS_INIT_RAM_LOCK
 330 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 331 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 332 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 333 /* The assembler doesn't like typecast */
 334 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 335         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 336           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 337 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 338
 339 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 340                                         GENERATED_GBL_DATA_SIZE)
 341 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 342
 343 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 344
 345 /* Serial Port - controlled on board with jumper J8
 346  * open - index 2
 347  * shorted - index 1
 348  */
 349 #define CONFIG_SYS_NS16550_SERIAL
 350 #define CONFIG_SYS_NS16550_REG_SIZE     1
 351 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 352
 353 #define CONFIG_SYS_BAUDRATE_TABLE       \
 354         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 355
 356 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 357 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 358 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 359 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 360
 361 #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB)
 362 /* Video */
 363 #define CONFIG_FSL_DIU_FB
 364
 365 #ifdef CONFIG_FSL_DIU_FB
 366 #define CONFIG_FSL_DIU_CH7301
 367 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 368 #define CONFIG_VIDEO_LOGO
 369 #define CONFIG_VIDEO_BMP_LOGO
 370 #endif
 371 #endif
 372
 373 /* I2C */
 374
 375 /* I2C bus multiplexer */
 376 #define I2C_MUX_PCA_ADDR                0x70
 377 #define I2C_MUX_CH_DEFAULT      0x8
 378
 379 #if defined(CONFIG_TARGET_T1042RDB_PI)  || \
 380         defined(CONFIG_TARGET_T1040D4RDB)       || \
 381         defined(CONFIG_TARGET_T1042D4RDB)
 382 /* LDI/DVI Encoder for display */
 383 #define CONFIG_SYS_I2C_LDI_ADDR         0x38
 384 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 385 #define CONFIG_SYS_I2C_DVI_BUS_NUM      0
 386
 387 /*
 388  * RTC configuration
 389  */
 390 #define RTC
 391 #define CONFIG_RTC_DS1337               1
 392 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 393
 394 /*DVI encoder*/
 395 #define CONFIG_HDMI_ENCODER_I2C_ADDR  0x75
 396 #endif
 397
 398 /*
 399  * eSPI - Enhanced SPI
 400  */
 401
 402 /*
 403  * General PCI
 404  * Memory space is mapped 1-1, but I/O space must start from 0.
 405  */
 406
 407 #ifdef CONFIG_PCI
 408 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 409 #ifdef CONFIG_PCIE1
 410 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 411 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 412 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 413 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 414 #endif
 415
 416 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 417 #ifdef CONFIG_PCIE2
 418 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 419 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 420 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 421 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 422 #endif
 423
 424 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 425 #ifdef CONFIG_PCIE3
 426 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 427 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 428 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 429 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 430 #endif
 431
 432 /* controller 4, Base address 203000 */
 433 #ifdef CONFIG_PCIE4
 434 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
 435 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
 436 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
 437 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 438 #endif
 439
 440 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 441 #endif  /* CONFIG_PCI */
 442
 443 /* SATA */
 444 #define CONFIG_FSL_SATA_V2
 445 #ifdef CONFIG_FSL_SATA_V2
 446 #define CONFIG_SYS_SATA_MAX_DEVICE      1
 447 #define CONFIG_SATA1
 448 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 449 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 450
 451 #define CONFIG_LBA48
 452 #endif
 453
 454 /*
 455 * USB
 456 */
 457 #define CONFIG_HAS_FSL_DR_USB
 458
 459 #ifdef CONFIG_HAS_FSL_DR_USB
 460 #ifdef CONFIG_USB_EHCI_HCD
 461 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 462 #endif
 463 #endif
 464
 465 #ifdef CONFIG_MMC
 466 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 467 #endif
 468
 469 /* Qman/Bman */
 470 #ifndef CONFIG_NOBQFMAN
 471 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 472 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 473 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 474 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 475 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 476 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 477 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 478 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 479 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 480                                         CONFIG_SYS_BMAN_CENA_SIZE)
 481 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 482 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 483 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 484 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 485 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 486 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 487 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 488 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 489 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 490 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 491 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 492                                         CONFIG_SYS_QMAN_CENA_SIZE)
 493 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 494 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 495
 496 #define CONFIG_SYS_DPAA_FMAN
 497 #define CONFIG_SYS_DPAA_PME
 498
 499 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 500 #endif /* CONFIG_NOBQFMAN */
 501
 502 #ifdef CONFIG_FMAN_ENET
 503 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
 504 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x03
 505 #elif defined(CONFIG_TARGET_T1040D4RDB)
 506 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x01
 507 #elif defined(CONFIG_TARGET_T1042D4RDB)
 508 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x02
 509 #define CONFIG_SYS_SGMII2_PHY_ADDR             0x03
 510 #define CONFIG_SYS_SGMII3_PHY_ADDR             0x01
 511 #endif
 512
 513 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
 514 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x04
 515 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x05
 516 #else
 517 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x01
 518 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x02
 519 #endif
 520
 521 /* Enable VSC9953 L2 Switch driver on T1040 SoC */
 522 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
 523 #define CONFIG_VSC9953
 524 #ifdef CONFIG_TARGET_T1040RDB
 525 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x04
 526 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x08
 527 #else
 528 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR        0x08
 529 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR        0x0c
 530 #endif
 531 #endif
 532
 533 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 534 #endif
 535
 536 /*
 537  * Environment
 538  */
 539 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 540 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 541
 542 /*
 543  * Miscellaneous configurable options
 544  */
 545
 546 /*
 547  * For booting Linux, the board info and command line data
 548  * have to be in the first 64 MB of memory, since this is
 549  * the maximum mapped by the Linux kernel during initialization.
 550  */
 551 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 552 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 553
 554 /*
 555  * Dynamic MTD Partition support with mtdparts
 556  */
 557
 558 /*
 559  * Environment Configuration
 560  */
 561 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 562 #define CONFIG_BOOTFILE         "uImage"
 563 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 564
 565 #define __USB_PHY_TYPE  utmi
 566 #define RAMDISKFILE     "t104xrdb/ramdisk.uboot"
 567
 568 #ifdef CONFIG_TARGET_T1040RDB
 569 #define FDTFILE         "t1040rdb/t1040rdb.dtb"
 570 #elif defined(CONFIG_TARGET_T1042RDB_PI)
 571 #define FDTFILE         "t1042rdb_pi/t1042rdb_pi.dtb"
 572 #elif defined(CONFIG_TARGET_T1042RDB)
 573 #define FDTFILE         "t1042rdb/t1042rdb.dtb"
 574 #elif defined(CONFIG_TARGET_T1040D4RDB)
 575 #define FDTFILE         "t1042rdb/t1040d4rdb.dtb"
 576 #elif defined(CONFIG_TARGET_T1042D4RDB)
 577 #define FDTFILE         "t1042rdb/t1042d4rdb.dtb"
 578 #endif
 579
 580 #ifdef CONFIG_FSL_DIU_FB
 581 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
 582 #else
 583 #define DIU_ENVIRONMENT
 584 #endif
 585
 586 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 587         "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;"                  \
 588         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 589         "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 590         "netdev=eth0\0"                                         \
 591         "video-mode=" __stringify(DIU_ENVIRONMENT) "\0"         \
 592         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 593         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 594         "tftpflash=tftpboot $loadaddr $uboot && "               \
 595         "protect off $ubootaddr +$filesize && "                 \
 596         "erase $ubootaddr +$filesize && "                       \
 597         "cp.b $loadaddr $ubootaddr $filesize && "               \
 598         "protect on $ubootaddr +$filesize && "                  \
 599         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 600         "consoledev=ttyS0\0"                                    \
 601         "ramdiskaddr=2000000\0"                                 \
 602         "ramdiskfile=" __stringify(RAMDISKFILE) "\0"            \
 603         "fdtaddr=1e00000\0"                                     \
 604         "fdtfile=" __stringify(FDTFILE) "\0"                    \
 605         "bdev=sda3\0"
 606
 607 #include <asm/fsl_secure_boot.h>
 608
 609 #endif  /* __CONFIG_H */